CN117097881A - Debugging method and device of image processing module - Google Patents
Debugging method and device of image processing module Download PDFInfo
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Abstract
The invention relates to the technical field of image processing, and provides a debugging method and device of an image processing module. Wherein the method comprises reading pixel data from an external storage medium, generating a data signal from the pixel data; generating a synchronous control signal according to the data signal; and transmitting the data signal and the control signal to an image processing module so that the image processing module can debug according to the data signal and the control signal. The invention uses external storage, thereby flexibly adjusting the source of the pixel data, and adjusting the source of the pixel data according to the debugging requirement of the image processing module so as to meet the requirement of self-defining scenes or testing by using the acquired data of external equipment.
Description
Technical Field
The present invention relates to the field of image processing technologies, and in particular, to a method and an apparatus for debugging an image processing module.
Background
The basic idea of debugging an image processing module in the prior art is that an image sensor outputs an output signal of a mobile industry processor interface (Mobile Industry Processor Interface, abbreviated as mipi) protocol, the output signal is processed by a corresponding IP (Internet protocol) check to obtain a high-performance expansion bus interface protocol data Stream (Advanced eXtensible Interface Stream, abbreviated as AXI Stream or AXI Stream protocol data Stream), and then the AXI Stream is used as an input to debug the image processing module.
Existing such debugging approaches often have several problems:
(1) Based on the basic idea of testing, it is necessary to ensure the reliability of the product, and the module test is a minimum granularity test for imparting obvious functions to the system, which is to test one module, check whether the module has errors according to the function description of the module, and a reliable module test should perform multiple inputs including correct inputs and error inputs on a single module, so as to test whether the module can perform corresponding processing on various inputs. In the prior art, since the test of the image processing module depends on the output of the image sensor, the input of the image processing module is limited in the output range of the image sensor, so that the input of the image processing module is more biased to the system test, and the module test of the image processing module is not realized, so that in the subsequent practical use, if the image sensor is replaced, the reliability of the image processing module is still immeasurable.
(2) The image sensor only supports shooting a live-action or generates a corresponding output signal by using color bars, so that a usable test mode is single, and the image sensor cannot meet the requirement when a user-defined scene is required during testing certain image processing modules or when data acquisition of external equipment is used.
In view of this, overcoming the drawbacks of the prior art is a problem to be solved in the art.
Disclosure of Invention
The invention aims to solve the technical problems that the test mode is single in the existing test mode, the requirement of a user-defined scene or the requirement of testing by using the acquired data of external equipment cannot be met, the current test chart is limited by an actually built scene, and a test image with certain characteristics cannot be designated according to the requirement.
The invention adopts the following technical scheme:
in a first aspect, the present invention provides a method for debugging an image processing module, including:
reading pixel data from an external storage medium, and generating a data signal according to the pixel data;
generating a synchronous control signal according to the data signal;
and transmitting the data signal and the control signal to an image processing module so that the image processing module can debug according to the data signal and the control signal.
Preferably, the reading of the pixel data from the external storage medium specifically includes:
the first state machine writes the pixel data in the external storage medium into the corresponding pixel buffer memory, and the second state machine reads the pixel data from the pixel buffer memory;
And the first state machine and the second state machine are synchronized in state switching so as to realize synchronous reading and writing of pixel data.
Preferably, the synchronization of the state switching between the first state machine and the second state machine specifically includes:
when the position of the read pointer in the pixel buffer is larger than a first preset position, the first state machine is switched from a waiting state to a data writing state so as to write the pixel data in the external storage medium into the residual space of the pixel buffer; wherein the read pointer is a pointer of a second state machine for reading pixel data.
Preferably, the synchronization of state switching between the first state machine and the second state machine further includes:
when the second state machine enters a pre-loading state, a pre-loading command is sent to the first state machine;
the first state machine enters a preloading state according to the preloading command so as to write pixel data in an external storage medium into a pixel cache; when the position of the write pointer in the pixel buffer is larger than a second preset position, a preloading completion command is sent to the second state machine; wherein the write pointer is a pointer used by the first state machine to write pixel data into a pixel cache;
And the second state machine enters a data reading state according to the preloading completion command so as to read pixel data from a pixel cache.
Preferably, the pixel data includes long exposure data and short exposure data, and the pixel buffer is divided into a long buffer for storing the long exposure data and a short buffer for storing the short exposure data; the synchronization of state switching between the first state machine and the second state machine specifically comprises:
when the position of the long data read pointer in the long cache is larger than a third preset position, the first state machine is switched to a long data writing state, so that the first state machine writes long exposure data in an external storage medium into the residual space in the long cache; the long data read pointer is a pointer of a second state machine for reading long exposure data;
when the position of the short data read pointer in the short buffer is larger than a fourth preset position, the first state machine is switched to a short data writing state, so that the first state machine writes short exposure data in an external storage medium into the residual space in the short buffer; wherein the short data read pointer is a pointer of a second state machine for reading short exposure data.
Preferably, the synchronization of state switching between the first state machine and the second state machine further includes:
when the second state machine enters a pre-loading state, a pre-loading command is sent to the first state machine;
the first state machine enters a long cache preloading state according to the preloading command so as to write long exposure data in an external storage medium into a long cache; when the position of the long data write pointer in the long cache is larger than a fifth preset position, a preloading completion command is sent to the second state machine; the long data writing pointer is a pointer used by the first state machine for writing long exposure data into a long cache;
and the second state machine enters a long data reading state according to the preloading completion command so as to read pixel data.
Preferably, the reading of the pixel data specifically includes:
when the second state machine is in a long data reading state, reading long exposure data from a long cache until the number of lines for reading pixel data is greater than a first preset number of lines, and switching to an alternate data reading state;
when the second state machine is in an alternate data reading state, alternately executing a process of reading one line of long exposure data from the long cache and a process of reading short exposure data from the short cache, and switching to a short data reading state until the line number of the read pixel data is larger than a second preset line number;
And when the second state machine is in a short data reading state, reading short exposure data from a short cache.
Preferably, the first state machine writes the pixel data in the external storage medium into the corresponding pixel buffer, and specifically includes:
when the first state machine is in a long cache preloading state, writing long exposure data in an external storage medium into a long cache, and switching to a short cache preloading state when a long data writing pointer reaches the end of the long cache;
and when the first state machine is in a short cache preloading state, writing short exposure data in an external storage medium into a short cache.
Preferably, the control signal includes at least one of a tuser signal, a tlast signal and a tdest signal, and the generating a synchronous control signal according to the data signal specifically includes:
when the first pixel data of the first row in each frame is read, the tuser signal is pulled high until the tuser signal is pulled low after a preset period;
when the last pixel data of each row in each frame is read, the tlast signal is pulled up until the tlast signal is pulled down after a preset period;
a preset encoded tdest signal is generated according to the type of the read pixel data.
In a second aspect, the present invention further provides a debugging device for an image processing module, for implementing the debugging method for an image processing module in the first aspect, where the device includes:
At least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor for performing the method of debugging the image processing module of the first aspect.
In a third aspect, the present invention also provides a non-volatile computer storage medium storing computer executable instructions for execution by one or more processors to perform the method of debugging an image processing module according to the first aspect.
According to the invention, the pixel data is read from the external storage, so that the corresponding data signals and control signals are generated, the AXI Stream output is simulated, the input is provided for the image processing module under the condition of not depending on an image sensor, and meanwhile, the source of the pixel data can be flexibly adjusted due to the use of the external storage, so that the source of the pixel data can be adjusted according to the debugging requirement of the image processing module, and the requirement of a custom scene or testing by using the acquired data of external equipment is met.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are required to be used in the embodiments of the present invention will be briefly described below. It is evident that the drawings described below are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a flow chart of a debugging method of an image processing module according to an embodiment of the present invention;
FIG. 2 is a flowchart of another method for debugging an image processing module according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for debugging an image processing module according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a debugging method of an image processing module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another method for debugging an image processing module according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a debugging method of another image processing module according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a large line period in a debugging method of an image processing module according to another embodiment of the present invention;
Fig. 8 is a schematic diagram of signals of a debugging method of an image processing module according to an embodiment of the present application;
fig. 9 is a schematic diagram illustrating state switching of a second state machine in a debugging method of an image processing module according to an embodiment of the present application;
fig. 10 is a schematic diagram illustrating state switching of a first state machine in a debugging method of an image processing module according to an embodiment of the present application;
fig. 11 is a schematic architecture diagram of a debugging device of an image processing module according to an embodiment of the present application;
FIG. 12 is a schematic diagram of a portion of a debugging device of an image processing module according to an embodiment of the present application;
fig. 13 is a schematic diagram of an architecture of another image processing module device according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The terms "first," "second," and the like herein are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The existing test mode has single test mode, can not meet the requirements of a user-defined scene or test by using collected data of external equipment, and the current test chart is limited by an actually built scene and can not specify a test image with certain characteristics according to the requirements. In order to solve the problem, an embodiment of the present invention provides a method for debugging an image processing module, as shown in fig. 1, including:
in step 201, pixel data is read from an external storage medium, and a data signal is generated according to the pixel data; the reading of the pixel data from the external storage medium is a relatively generalized expression, which represents that the pixel data originates from the external storage medium and is finally read, but does not refer to directly reading from the external storage medium, and taking the external storage medium as an SD (Secure Digital Memory Card, secure digital card) card as an example, the reading of the pixel data from the external storage medium may be loading the pixel data in the external storage medium into a memory, then reading the pixel data from the memory into a corresponding buffer, and finally reading the pixel data from the buffer.
In step 202, generating a synchronized control signal from the data signal; the control signal includes at least one of a tuser signal, a tlast signal and a tdest signal, and in actual use, the control signal also receives an input of a first handshake signal, valid, of the image processing module, and outputs a second handshake signal, tvalid, according to the valid signal. The tdata signal is also used in the subsequent embodiments as an alternative expression for the data signal. Wherein the data signal and the control signal together form an AXI Stream input required by the image processing module.
In step 203, the data signal and the control signal are transmitted to an image processing module, so that the image processing module performs debugging according to the data signal and the control signal.
It should be noted that, the image processing modules in the embodiments of the present invention refer to all modules that take AXI Stream as input, and specific functions executed in the image processing modules are not limited in the embodiments of the present invention.
According to the embodiment of the invention, the pixel data is read from the external storage, so that the corresponding data signals and control signals are generated, the AXI Stream output is simulated, the input is provided for the image processing module under the condition of not depending on an image sensor, and meanwhile, the source of the pixel data can be flexibly adjusted due to the use of the external storage, so that the source of the pixel data can be adjusted according to the debugging requirement of the image processing module, and the requirement of a custom scene or testing by using the acquired data of external equipment is met.
In practical use, the data reading rate of the external storage medium is generally low, and cannot meet the high-speed AXI Stream input requirement of the image processing module, so as to solve the problem, the embodiment of the present invention further provides a preferred implementation manner, that is, the method for reading pixel data from the external storage medium, as shown in fig. 2, specifically includes:
in step 301, a first state machine writes pixel data in an external storage medium into a corresponding pixel buffer, and a second state machine reads the pixel data from the pixel buffer; the size of the pixel buffer is analyzed by a person skilled in the art according to the reading requirement of the pixel data, and the pixel buffer can be used for storing a plurality of frames, a plurality of rows of pixel data in a single frame, a single row of pixel data in a single frame or a corresponding number of pixel data.
In step 302, the state switching between the first state machine and the second state machine is synchronized to realize synchronous reading and writing of pixel data. The first state machine and the second state machine may be implemented by RTL (Register Transfer Level ) codes, and the first state machine and the second state machine perform processing in parallel and may perform corresponding operations in parallel.
In general, the data reading rate in the cache is greater than the data reading rate in the memory and greater than the data reading rate in the external storage medium, and the external storage medium is usually accessed by a plurality of modules, which may happen to be busy. Therefore, in the embodiment, the pixel data in the external storage medium is written into the buffer memory, and then the pixel data is read from the buffer memory, and the synchronization between the two is realized through the synchronous state switching of the first state machine and the second state machine, so that the pixel data can be quickly read, and the high-speed AXI Stream input requirement of the image processing module is met.
When the AXI Stream input requirement of the image processing module is a non-HDR (High Dynamic Range, high dynamic range image) mode, such as an SDR (Standard Dynamic Range, standard dynamic range image) mode or an LDR (Low Dynamic Range, low dynamic range image) mode, the synchronization of state switching between the first state machine and the second state machine specifically includes:
when the position of the read pointer in the pixel buffer is larger than a first preset position, the first state machine is switched from a waiting state to a data writing state so as to write the pixel data in the external storage medium into the residual space of the pixel buffer; wherein the read pointer is a pointer of a second state machine for reading pixel data. The first preset position is obtained by a person skilled in the art through common analysis according to the data reading rate in the pixel buffer, the data writing rate in the pixel buffer and the reading time intervals between the pixel data of different rows, for example, if the size of the pixel buffer is the size of the pixel data of each row, the first preset position needs to satisfy the reading requirement of the pixel data of the next reading period when the reading pointer starts to write the pixel data when reaching the first preset position in the previous reading period.
In a preferred embodiment, the synchronization of the state switching between the first state machine and the second state machine, as shown in fig. 3, further includes:
in step 401, when the second state machine enters a preload state, a preload command is sent to the first state machine.
In step 402, the first state machine enters a pre-loading state according to the pre-loading command, so as to write pixel data in an external storage medium into a pixel cache; when the position of the write pointer in the pixel buffer is larger than a second preset position, a preloading completion command is sent to the second state machine; wherein the write pointer is a pointer used by the first state machine to write pixel data into a pixel cache.
In step 403, the second state machine enters a data reading state according to the preload completion command to read pixel data from the pixel cache. The second preset position is obtained by a person skilled in the art through analysis according to the data reading rate in the pixel buffer and the data writing rate in the pixel buffer, for example, if the size of the pixel buffer is the size of the pixel data of each line, the second preset position needs to satisfy the reading requirement of the pixel data of the corresponding line when the position of the writing pointer in the pixel buffer is larger than the second preset position and the reading of the pixel data is started.
When the AXI Stream input requirement of the image processing module is in an HDR mode, the pixel data comprise long exposure data and short exposure data, and the pixel cache is divided into a long cache for storing the long exposure data and a short cache for storing the short exposure data; the synchronization of state switching between the first state machine and the second state machine specifically comprises:
when the position of the long data read pointer in the long cache is larger than a third preset position, the first state machine is switched to a long data writing state, so that the first state machine writes long exposure data in an external storage medium into the residual space in the long cache; the long data read pointer is a pointer of a second state machine for reading long exposure data; as shown in fig. 4 and 6, each of the dashed line positions represents a timing at which the long data read pointer reaches the third preset position, from which the writing of the long exposure data is started, and when the long exposure data of the corresponding position is read in the next period, the long exposure data of the position has been written in the last writing period.
When the position of the short data read pointer in the short buffer is larger than a fourth preset position, the first state machine is switched to a short data writing state, so that the first state machine writes short exposure data in an external storage medium into the residual space in the short buffer; wherein the short data read pointer is a pointer of a second state machine for reading short exposure data. The third preset position is obtained by common analysis of a person skilled in the art according to the data reading rate in the long cache, the data writing rate in the long cache and the reading time interval from the last line of long exposure data to the next line of long exposure data; the fourth preset position is obtained by common analysis of a person skilled in the art according to the data reading rate in the short buffer, the data writing rate in the short buffer and the reading time interval from the last line of short exposure data to the next line of short exposure data.
The synchronization of state switching between the first state machine and the second state machine may further include the following two embodiments:
first embodiment: when the second state machine enters a preloading state, a preloading command is sent to the first state machine, and the first state machine enters a long cache preloading state according to the preloading command so as to write long exposure data in an external storage medium into a long cache; when the long data write pointer reaches the end of the long cache, entering a short cache pre-loading state to write short exposure data in an external storage medium into the short cache, and when the short cache write pointer reaches the end of the short cache, entering an initial state by a first state machine, sending a pre-loading completion command to a second state machine, and entering a long data reading state by the second state machine according to the pre-loading completion command so as to read pixel data.
Second embodiment: when the second state machine enters a pre-loading state, a pre-loading command is sent to the first state machine; the first state machine enters a long cache preloading state according to the preloading command so as to write long exposure data in an external storage medium into a long cache; in order to shorten the preloading time, when the position of the long data write pointer in the long cache is larger than a fifth preset position, a preloading completion command is sent to the second state machine; the long data writing pointer is a pointer used by the first state machine for writing long exposure data into a long cache; and the second state machine enters a long data reading state according to the preloading completion command so as to read pixel data. As shown in fig. 5, the dashed line position represents that the long data writing pointer reaches the fifth preset position, and enters the long data reading state, and meanwhile, the first state machine continues to write in the long buffer memory preloading state, so that when long exposure data is read, the writing in the subsequent long buffer memory can still be performed, and before corresponding long exposure data is read, the long exposure data is written in the long buffer memory until the long buffer memory is written to the end, and enters the short buffer memory preloading state, and the writing in of the short buffer memory is performed, so as to shorten the preloading time. The fifth preset position is obtained by common analysis of a person skilled in the art according to the data reading rate in the long cache and the data writing rate in the long cache.
In an alternative embodiment, the reading of the pixel data, as shown in fig. 6, specifically includes: when the second state machine is in a long data reading state, reading long exposure data from a long cache until the number of lines for reading pixel data is greater than a first preset number of lines, and switching to an alternate data reading state; when the second state machine is in an alternate data reading state, alternately executing a process of reading one line of long exposure data from the long cache and a process of reading short exposure data from the short cache, and switching to a short data reading state until the line number of the read pixel data is larger than a second preset line number; and when the second state machine is in a short data reading state, reading short exposure data from the short buffer until the number of lines of the read pixel data is greater than a third preset number of lines, switching to an initial state so as to read the next frame. The first preset line number, the second preset line number and the third preset line number are all obtained by analysis of a data source format of debugging of the image processing module by a person skilled in the art. The third preset line number is greater than or equal to the second preset line number, and the second preset line number is greater than or equal to the first preset line number. The number of lines of the read pixel data includes the number of lines of the read long exposure data and short exposure data, which can be counted by a counter.
In the long data reading state, the alternate data reading state and the short data reading state, the pixel data are all read based on the line periods, as shown in fig. 7, fig. 7 is a large line period in the alternate data reading state, a plurality of large line periods are provided in each frame period, two small line periods are provided in each large line period, namely a long exposure line period and a short exposure line period respectively, in the alternate data reading state, the long exposure data are read in an effective section of the long exposure line period (namely a shadow part in the long exposure line period in fig. 7), and the short exposure data are read in an effective section of the short exposure line period (namely a shadow part in the short exposure line period in fig. 7); in a long data reading state, long exposure data is read only in an effective section of a long exposure line period, and is idle in a short exposure line period; in the short data reading state, short exposure data is read only in the effective section of the short exposure line period, and is idle in the long exposure line period.
The first state machine writes pixel data in an external storage medium into a corresponding pixel cache, and specifically includes: when the first state machine is in a long cache preloading state, long exposure data in an external storage medium are written into a long cache, and when a long data writing pointer reaches the end of the long cache, the first state machine is switched to a short cache preloading state. And when the first state machine is in a short cache preloading state, writing short exposure data in an external storage medium into a short cache. In combination with the second embodiment, as shown in fig. 5, after entering the short buffer preloading state and before the short data write pointer reaches the end of the short buffer, if the long data read pointer reaches the third preset position, writing of the short buffer is interrupted, writing is performed on the long buffer, and switching is performed again to continuous writing of the short buffer until the long data write pointer reaches the end of the long buffer, until the short data write pointer reaches the end of the short buffer, and the first state machine enters the initial state.
In an alternative embodiment, the embodiment of the present invention analyzes the rule of the output signal to obtain the association between the control signal and the data signal by collecting the output of the actual image sensor and performing mipi analysis on the output, thereby obtaining the following embodiment, that is, the method for generating the synchronous control signal according to the data signal specifically includes:
when the first pixel data of the first row in each frame is read, the tuser signal is pulled high until the tuser signal is pulled low after a preset period, and the tuser signal is used for representing the beginning of each frame; when the last pixel data of each row in each frame is read, the tlast signal is pulled up until a preset period is later pulled down, and the tlast signal is used for representing the end of each row; a preset coded tdest signal is generated according to the type of the read pixel data, and is used for indicating whether the current pixel data is long exposure data or short exposure data. The tuser, tlast and tdest signals are shown in fig. 8, and tdata is a data signal in fig. 8. The predetermined period and the predetermined code are analyzed by a person skilled in the art based on the data source required by the image processing module.
In the embodiment of the present invention, taking the AXI Stream input requirement of the image processing module as the HDR mode as an example, a first state machine and a second state machine in an optional implementation manner are described in detail, as shown in fig. 9, where the second state machine includes six states, i.e., IDLE, LOAD, LONG, ALTERNATE, SHORT and BLANK, where IDLE is an initial state, and when entering the IDLE state, if an external enable signal is received, the first state machine starts to read a new frame, enters a LOAD state, and sends a preload command to the first state machine.
The LOAD is a preload state, representing data being preloaded into the cache, in which state it waits to enter a LONG state upon receipt of a preload done command from the first state machine.
LONG is a LONG data reading state, LONG exposure data is read in the LONG state, and when the line count row_cnt reaches the first preset line number long_end, the state is set to ALTERNATE.
ALTERNATE is an alternate data reading state in which long exposure data and SHORT exposure data are alternately read in ALTERNATE, and a SHORT state is entered when the row count row_cnt reaches the second preset row number ALTERNATE _end.
SHORT is a SHORT data reading state, SHORT exposure data is read in the SHORT state, and when the row count row_cnt reaches a third preset row number short_end, a BLANK state is entered.
BLANK is idle state, waits in BLANK state, and enters initial state after preset Time is elapsed. The preset time is obtained by empirical analysis by a person skilled in the art, and generally an integer multiple of one reading period (i.e. one large line period) in the data signal is taken as the preset time, and the BLANK state is mainly used for performing mode switching, and specific implementation of mode switching will be described in detail in the following embodiments, which will not be repeated here. Wherein, each line of pixel data (including long exposure data and short exposure data) is read, the line count row_cnt is incremented by one, and when the IDLE state is entered, the line count row_cnt is cleared.
As shown in fig. 10, the first state machine includes five states of IDLE, LONG, SHORT, PRE _long and pre_short, where IDLE is an initial state, and waits in this state, so as to enter one of the LONG, SHORT, and pre_long states when corresponding conditions are satisfied, specifically:
the first state machine enters a pre_long state when receiving a preload command from the second state machine in the IDLE state.
The pre_long is in a LONG cache preloading state, LONG exposure data is written into the LONG cache in the pre_long state, and when a LONG data write pointer wr_l_addr reaches a fifth preset position pre_gate, a preloading completion command is sent to the second state machine. When the long data write pointer wr_l_addr reaches the end l_width of the long cache, the state is switched to the pre_short state.
The pre_short is in a SHORT buffer preloading state, SHORT exposure data is written into the SHORT buffer in the pre_short state, and the SHORT data writing pointer wr_s_addr is switched to an IDLE state when the SHORT data writing pointer wr_s_addr reaches the end s_width of the SHORT buffer.
In the IDLE state, when the LONG data read pointer rd_l_addr reaches the third preset position l_gate, the LONG state is switched to. When the SHORT data read pointer rd_s_addr reaches the fourth preset position s_gate, switching to the SHORT state.
The LONG state is a LONG data writing state in which LONG exposure data is written into the LONG buffer, and when the LONG data writing pointer wr_l_addr reaches the end l_width of the LONG buffer, the state is switched to the IDLE state.
The SHORT state is a SHORT data writing state in which SHORT exposure data is written into the SHORT buffer, and when the SHORT data writing pointer wr_s_addr reaches the end s_width of the long buffer, the state is switched to the IDLE state.
In practical implementation, the module where the second state machine is located may send a data reading command to the module where the first state machine is located, where the data reading command includes at least a reading address, and the module where the first state machine is located reads the buffer memory according to the data reading command and transmits the pixel data obtained by reading to the module where the second state machine is located, so as to implement reading of the pixel data and monitoring of the read pointer and the write pointer by the first state machine.
It should be noted that the second state machine reads the pixel caches in the order from front to back, and the first state machine writes the pixel caches in the order from front to back.
In practical use, considering that there may be a case that pixel data is collected in real time or generated in real time by other external devices, the external devices write the pixel data into an external storage medium, and then the debugging method of the image processing module of the present invention is used to debug the image processing module. In this case, since the pixel data in the external storage medium is written in real time, the writing speed thereof may also affect the debugging process, and the embodiment of the present invention provides the following preferred embodiments for this scenario, specifically including:
The first state machine monitors the process of writing pixel data into an external storage medium, counts the writing speed of writing the pixel data into the external storage medium, and judges whether the writing speed meets the real-time reading requirement of long exposure data and short exposure data in a corresponding mode, namely judges whether the writing speed is greater than or equal to the reading speed of the long exposure data and the short exposure data. There are three cases:
first case: when the writing speed is equal to or higher than the reading speeds of the long exposure data and the short exposure data, it is indicated that the collection of the pixel data is followed by the reading of the data, and the reading of the long exposure data and the short exposure data is performed using the method described in the above embodiment.
Second case: when the writing speed is smaller than the reading speeds of the long exposure data and the short exposure data, the acquisition of the pixel data is not followed by the reading of the data, and at the moment, each time the first state machine monitors that new pixel data is written in the external storage medium, the new pixel data is read from the external storage medium, and the new pixel data is sent to the second state machine.
Third case: in practical use, since the exposure time required for LONG exposure data acquisition is LONG, the acquisition speed is relatively slow, and the exposure time required for SHORT exposure data acquisition is SHORT, and the acquisition speed is relatively fast, it may also happen that the writing speed of the LONG exposure data in the pixel data is smaller than the reading speed of the LONG exposure data, and the reading speed of the SHORT exposure data in the pixel data is larger than the reading speed of the SHORT exposure data, when the second state machine is in the LONG data reading state (LONG) or the SHORT data reading State (SHORT), the data reading can still be performed according to the two conditions.
When the second state machine is in an alternate data reading state (ALTERNATE), the first state machine reads the long exposure data according to the second condition, reads the short exposure data according to the first condition, and correspondingly returns corresponding data serial numbers when the short exposure data and the long exposure data are returned to the second state machine, the data serial numbers of the short exposure data and the long exposure data are sequentially increased and reset to zero after one frame is finished, and the second state machine is spliced with the received short exposure data of the corresponding data serial numbers according to the received data serial numbers of the long exposure data to obtain a data signal. For example, when a long exposure data is collected, the first state machine reads the long exposure data in the external storage medium and returns the long exposure data to the second state machine, and before that, since the short exposure data collection speed is high, the corresponding reading speed is relatively high when the short exposure data is read according to the first condition, if the data serial number of the long exposure data received by the first state machine is 8, the short exposure data with the data serial number of 8 is read in a gap of reading the long exposure data, and then the short exposure data with the data serial number of 8 is spliced in front of or behind the long exposure data with the data serial number of 8 according to the splicing rule of the data signals, so as to form a section of data signal.
The invention is based on the method described in the above embodiment, combines with specific application scenario, and expounds the implementation process under the characteristic scenario of the invention by the technical expression under the relevant scenario.
The embodiment of the invention further provides a debugging device of the image processing module based on the method described in the above embodiment, as shown in fig. 11, where the device includes a configuration module, a logic control module, and a line buffer module, where both the logic control module and the line buffer module may be FPGA (Field-Programmable Gate Array, field programmable gate array) modules in actual use, a second state machine is set in the logic control module, a first state machine is set in the line buffer module, and long buffers and short buffers are set in the line buffer module.
The device is taken as an application scene, and the debugging method of the image processing module comprises the following steps:
the output timing of the actual image sensor is acquired. In the subsequent embodiments, the expression is also made using a sensor as an alternative to the image sensor. Under the normal operation of the sensor, the signal of the sensor after passing through the mipi analysis module is acquired by a logic analyzer to obtain:
tuser signal (single bit): in combination with the characteristics of the sensor and the mipi protocol, the resulting tuser signal indicates the start of a frame, and since the sensor is operating in HDR mode, two tusers are active during a frame period, representing the start of a long exposure frame and the start of a short exposure frame, respectively.
tlast signal (single bit): indicating the end of a line of data.
tdest signal (10 bit): here, it is indicated whether the current line is a long exposure line or a short exposure line, such as representing a short exposure line when encoded as 2b1, and representing a long exposure line when encoded as 2b 0.
tdata signal (16 bit): representing pixel data, if the data format of the sensor output is row10, the valid bit is the lower 10 bits.
tvalid signal: the handshake signals are output.
tdest signal: handshake signals are input.
And drawing a waveform chart of each signal in one frame period according to the real-time acquired signal time sequence and the combination of the sensor characteristics, wherein the waveform chart is shown in fig. 8.
And setting a second state machine in the logic control module, and simulating the output of an actual sensor. The main function of this module is to correctly generate tuser, tlast, tdest, tdata signal under the handshake mechanism of AXI Stream. According to the principle of sensor output pixels: there are 3500 large line periods in each frame period (where the number of large line periods in each frame period may also be different for different sensors), and there are two small line periods in each large line period, respectively a long exposure line period and a short exposure line period, each small line period including a small line active area and a small line blank area (i.e., an idle area). The sensor works in the HDR mode by outputting the 'maximum short exposure line/2' line length exposure data first, then outputting the long exposure data and the short exposure data alternately according to the line, and finally outputting the 'maximum short exposure line/2' line short exposure data, and then outputting the blank line until the frame period is finished. Two counters are defined, one counting a single row is called a column counter, one counting a row is called a row counter, and the state machine can be skipped according to the row counter, wherein the second state machine has 6 states, IDLE, LOAD, LONG, ALTERNATE, SHORT, BLANK respectively, and the IDLE represents an initial state, and the LOAD state represents that pixel data needs to be read from the DDR (Double Data Rate SDRAM, double rate synchronous dynamic random access memory) and temporarily stored in a row buffer. In order to avoid delay in reading the pixels at the next stage; the LONG state indicates that LONG exposure data needs to be output at the moment, wherein the LONG exposure data is read from a LONG line cache; ALTERNATE state indicates that long exposure data and short exposure data need to be alternately output at this time, wherein the short exposure data is read from the short line buffer; the SHORT state indicates that SHORT exposure data needs to be output at the moment, wherein the SHORT exposure data is read from a SHORT cache; finally, the BLANK state is ended and returns to the IDLE state.
The triggering conditions for the state jumps are row counter count (i.e. row count) to load_end, long_ END, ALTERNATE _end, short_end, BLANK_end, respectively. These parameters are configurable, but there are also constraints on each other. These parameters are all analyzed by those skilled in the art and are pre-stored in the configuration module.
The logic control module generates each control signal according to the row count and the dot count while reading the pixel data, and specifically comprises the following steps:
the tuser signal pulls high one clock cycle upon entering the LONG state, upon entering the SHORT state, and outputting the first pixel.
the tlast signal is pulled high one clock cycle at the last pixel output of each row.
the tdest signal is based on the current output line, the long exposure line outputs 2'b0, and the short exposure line outputs 2' b1.
tdata is a data signal generated from pixel data, and outputs long exposure data, short exposure data, or alternately outputs long exposure data and short exposure data, respectively, according to a state machine.
The first state machine is set in the line buffer module, and each state of the first state machine is switched as shown in fig. 10, and the function of the module is to correctly read pixel data from an external storage medium DDR (Double Data Rate SDRAM, double rate synchronous dynamic random access memory) and temporarily store the pixel data in the line buffer. Its function is mainly focused on: when, how many times, from which, how many data is read at a time. The block is controlled by a pure FPGA, master logic for accessing the DDR is written, and data can be waited to be received from the DDR by initiating a command (namely, a data reading command) containing information of 'reading start address + reading length + other', so that the problem of reading from which data and how many data are read each time is solved. When to read, how many times the sensor logic is simulated is determined by the module, and the buffer module uses BRAM (Block RAMs) resources in the FPGA.
Because the sensor is operated in the HDR mode and needs to output long and short exposure lines, the line buffers are divided into long exposure buffers and short exposure buffers, and the same line buffer is not used here because the FPGA has a delay to read data from the DDR, which may exceed the interval duration between two lines output by the sensor. Therefore, the data can be read at high speed by storing the data in different buffer areas.
In DDR, a typical picture is stored in a continuous space, so long exposure data is typically stored separately, i.e., long exposure exists in addr1 (start address of stored image) +frame_size (number of bytes occupied per frame) ×frame_cnt (total frame number), and short exposure data is stored in addr2+frame_size×frame_cnt. In the output short-short exposure alternating stage, the addresses are switched back and forth, and once the error occurs, the image error is caused, so that the read address for reading data from the DDR (i.e. the read address in the data read command) needs to be strictly controlled. A schematic diagram of the state switches of the second state machine is shown in fig. 9.
For example, the configuration of parameters such as frame rate, frame number, line spacing, switching display source, etc. is not a high-speed frequent configuration, so that it is sufficient to use the axilite interface protocol, and it is necessary to write a slave based on the axilite interface. Setting of frame rate, frame number and line spacing is achieved through the interface.
The embodiment of the invention also supports the switching between the debugging of the image processing module by the device of the embodiment of the invention and the debugging of the image processing module by the sensor, and in order to prevent the splitting and cutting of the image during the switching, the embodiment of the invention selects the device or the sensor of the embodiment of the invention by the high-low representation of the signal sel, and selects the device of the embodiment of the invention when the signal sel is at the high level and selects the sensor when the signal sel is at the low level. The embodiment of the invention also generates a corresponding test_frame_end waveform according to the data signal, when the data reading frame is finished, namely, when the second state machine enters a BLANK state, the test_frame_end waveform is pulled high, and when the second state machine exits the BLANK state (namely, enters an IDLE state), the test_frame_end waveform is pulled low, thereby being used for representing the end of the frame. Meanwhile, after the sensor is correspondingly used and subjected to mipi protocol analysis, the mipi_frame_end waveform is output, and at the end of reading each frame, the mipi_frame_end waveform is pulled high, and at the time of reading the next frame, the mipi_frame_end waveform is pulled low.
The control of switching is performed using a digital logic circuit as shown in fig. 12, where sel1=sel & mipi_frame_end, sel2= sel & mipi_frame_end & test_frame_end, so that when switching occurs during reading of the corresponding frame, i.e. waveform sel goes from low to high or from high to low, no processing is performed, and the display source is replaced after the frame ends (e.g. in the blast state of the second state machine), where test represents the device output according to the embodiment of the present invention, and mipi represents the output after the mipi protocol parsing performed on the sensor. If the switching signal comes to be stored first, the switching signal is enabled after the frame is ended.
When in actual use, the SD card file system is loaded, test data in the SD card is read into the DDR, the read data is written into an address interval appointed in the DDR, and a start address read by a long and short frame in the line buffer module is configured through an AXI Lite interface. When the device is switched to be used for debugging, the line buffer module takes out a reading initial address from the DDR, reads data (pixels) of the address interval into a corresponding pixel buffer so as to generate data signals and control signals, and outputs the generated data signals and control signals to the image processing module for debugging.
Fig. 13 is a schematic diagram of a debugging device of an image processing module according to an embodiment of the invention. The debugging device of the image processing module of the embodiment of the invention comprises one or more processors 21 and a memory 22. In fig. 13, a processor 21 is taken as an example.
The processor 21 and the memory 22 may be connected by a bus or otherwise, for example in fig. 13.
The memory 22 is used as a nonvolatile computer-readable storage medium for storing a nonvolatile software program and a nonvolatile computer-executable program, such as the debugging method of the image processing module in the above-described embodiment. The processor 21 executes a debugging method of the image processing module by running a nonvolatile software program and instructions stored in the memory 22.
The memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 22 may optionally include memory located remotely from processor 21, which may be connected to processor 21 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The program instructions/modules are stored in the memory 22, which when executed by the one or more processors 21, perform the debugging method of the image processing module in the above-described embodiments.
It should be noted that, because the content of information interaction and execution process between modules and units in the above-mentioned device and system is based on the same concept as the processing method embodiment of the present invention, specific content may be referred to the description in the method embodiment of the present invention, and will not be repeated here.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the embodiments may be implemented by a program that instructs associated hardware, the program may be stored on a computer readable storage medium, the storage medium may include: read Only Memory (ROM), random access Memory (RAM, random Access Memory), magnetic or optical disk, and the like.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (9)
1. A method for debugging an image processing module, comprising:
reading pixel data from an external storage medium, and generating a data signal according to the pixel data;
generating a synchronous control signal according to the data signal;
transmitting the data signal and the control signal to an image processing module so that the image processing module can debug according to the data signal and the control signal;
the reading of the pixel data from the external storage medium includes:
the first state machine writes the pixel data in the external storage medium into the corresponding pixel buffer memory, and the second state machine reads the pixel data from the pixel buffer memory;
and the first state machine and the second state machine are synchronized in state switching so as to realize synchronous reading and writing of pixel data.
2. The method of debugging an image processing module of claim 1, wherein synchronizing state switching between the first state machine and the second state machine comprises:
When the position of the read pointer in the pixel buffer is larger than a first preset position, the first state machine is switched from a waiting state to a data writing state so as to write the pixel data in the external storage medium into the residual space of the pixel buffer; wherein the read pointer is a pointer of a second state machine for reading pixel data.
3. The method of debugging an image processing module of claim 2, wherein synchronizing state switching between the first state machine and the second state machine further comprises:
when the second state machine enters a pre-loading state, a pre-loading command is sent to the first state machine;
the first state machine enters a preloading state according to the preloading command so as to write pixel data in an external storage medium into a pixel cache; when the position of the write pointer in the pixel buffer is larger than a second preset position, a preloading completion command is sent to the second state machine; wherein the write pointer is a pointer used by the first state machine to write pixel data into a pixel cache;
and the second state machine enters a data reading state according to the preloading completion command so as to read pixel data from a pixel cache.
4. The debugging method of an image processing module according to claim 1, wherein the pixel data comprises long exposure data and short exposure data, and the pixel buffer is divided into a long buffer for storing the long exposure data and a short buffer for storing the short exposure data; the synchronization of state switching between the first state machine and the second state machine comprises:
when the position of the long data read pointer in the long cache is larger than a third preset position, the first state machine is switched to a long data writing state, so that the first state machine writes long exposure data in an external storage medium into the residual space in the long cache; the long data read pointer is a pointer of a second state machine for reading long exposure data;
when the position of the short data read pointer in the short buffer is larger than a fourth preset position, the first state machine is switched to a short data writing state, so that the first state machine writes short exposure data in an external storage medium into the residual space in the short buffer; wherein the short data read pointer is a pointer of a second state machine for reading short exposure data.
5. The method of debugging an image processing module of claim 4, wherein synchronizing state switching between the first state machine and the second state machine further comprises:
When the second state machine enters a pre-loading state, a pre-loading command is sent to the first state machine;
the first state machine enters a long cache preloading state according to the preloading command so as to write long exposure data in an external storage medium into a long cache; when the position of the long data write pointer in the long cache is larger than a fifth preset position, a preloading completion command is sent to the second state machine; the long data writing pointer is a pointer used by the first state machine for writing long exposure data into a long cache;
and the second state machine enters a long data reading state according to the preloading completion command so as to read pixel data.
6. The method for debugging an image processing module of claim 5, wherein the performing the reading of the pixel data comprises:
when the second state machine is in a long data reading state, reading long exposure data from a long cache until the number of lines for reading pixel data is greater than a first preset number of lines, and switching to an alternate data reading state;
when the second state machine is in an alternate data reading state, alternately executing a process of reading one line of long exposure data from the long cache and a process of reading short exposure data from the short cache, and switching to a short data reading state until the line number of the read pixel data is larger than a second preset line number;
And when the second state machine is in a short data reading state, reading short exposure data from a short cache.
7. The method of debugging an image processing module of claim 4, wherein the first state machine writing pixel data in an external storage medium into a corresponding pixel cache comprises:
when the first state machine is in a long cache preloading state, writing long exposure data in an external storage medium into a long cache, and switching to a short cache preloading state when a long data writing pointer reaches the end of the long cache;
and when the first state machine is in a short cache preloading state, writing short exposure data in an external storage medium into a short cache.
8. The method according to any one of claims 1 to 7, wherein the control signal includes at least one of a tuser signal, a tlast signal, and a tdest signal, and the generating the synchronized control signal according to the data signal includes:
when the first pixel data of the first row in each frame is read, the tuser signal is pulled high until the tuser signal is pulled low after a preset period;
when the last pixel data of each row in each frame is read, the tlast signal is pulled up until the tlast signal is pulled down after a preset period;
A preset encoded tdest signal is generated according to the type of the read pixel data.
9. A debugging device of an image processing module, comprising:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor for performing the method of debugging an image processing module of any one of claims 1 to 8.
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