JPH09113560A - Pattern generating device for liquid crystal display panel test - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display(LCD) panel generating no unnecessary picture element signal even when the total number of picture elements of the LCD panel is odd or even by providing switching circuits switching the connection relation between memory regions and buffer memories. SOLUTION: The picture element data read out from the memory regions A, B, C, D of a pattern storage memory 1 having four memory regions A, B, C, D, for example, are inputted to the input terminals I1 , I2 , I3 , I4 of four- input, one-output type switching circuits 11A, 11B, 11C, 11D. Buffer memories 12A, 12B, 12C, 12D are connected to the output sides of the switching circuits 11A-11D. The buffer memories 12A-12D can independently implement writing and reading. An interleaving action can be normally taken even when the number of the total picture elements of an LCD panel to be tested is not a multiple of the number of the memory regions provided on the pattern storage memory 1, high-speed multiplex signals can be generated, and versatility is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for testing a liquid crystal display panel (hereinafter referred to as LCD panel).
The present invention relates to a pattern generator for a CD panel test.

[0002]

2. Description of the Related Art FIG. 6 shows the structure of a conventional LCD panel test pattern generator. In the figure, reference numeral 1 denotes a pattern storage memory in which pixel data for displaying a desired image on the LCD panel under test is stored. This pattern storage memory 1
Has a plurality of storage areas, for example, A, B, C, and D, reads pixel data from the plurality of storage areas A to D, multiplexes the pixel data by a multiplexing circuit 2, and in this example, a pattern storage memory. The image signal is converted into an image signal having a frequency four times the reading speed of 1, converted into a color signal by the conversion table 3, and a color image signal is output from the output terminal 4.

A horizontal synchronizing signal H and a vertical synchronizing signal V are generated and output to the output terminal 5 from a part of bit information of the image signal. The output terminal 6 has a clock generator 7
To output the LCD clock for driving the LCD panel under test. Further, 8 is a control unit, and 9 is an address generation unit for accessing the pattern storage memory 1. As shown in the figure, the pattern storage memory 1 conventionally has a plurality of storage areas A to D, and the plurality of storage areas A to D are simultaneously accessed to read four pixel data from all the storage areas at a time. The four pixel data are multiplexed to obtain an image signal at a speed four times as fast as the reading speed, and a low speed memory is used to obtain a high speed image signal. Since the number of dots in the LCD panel tends to be higher, the speed of the pixel signal is required to be higher and higher. Therefore, a high-speed image signal is obtained by increasing the number of multiplexed signals as compared with the conventional one. Such a technique of multiplexing a plurality of data read from a memory to obtain a high-speed signal is generally called interleaving.

[0004]

Generally, the total number of pixels of an LCD panel is often an even number. When a signal having a frequency higher than the read speed of the pattern storage memory is obtained by the interleave method, the number M of storage areas of the memory 1 and the LCD
With the total number N of pixels of the panel, if the number M is a value that is an integer fraction of the total number of picture elements N, the multiplexing circuit 2 operates normally. That is, assuming that the total number of image elements of the LCD panel is, for example, 9 for simplification, in the example shown in FIG. 6, since the number of storage areas is 4, when the final pixel data 9N is read by the last address. In this case, as shown in FIG. 7, the pixel data 9N + is also stored in the storage areas B, C, and D.
Since 1,9N + 2 and 9N + 3 are read, there arises a problem that unnecessary pixel data 9N + 1, 9N + 2 and 9N + 3 are multiplexed by the multiplexing circuit 2 and output from the output terminal 4.

Therefore, it is conceivable that the storage area of the pattern storage memory 1 can be switched between an odd number and an even number, but normally, although there are many opportunities to operate in the mode of reading from the even number storage area, It is uneconomical because the storage area for operating in the odd mode must be prepared for the odd mode which is used only occasionally.

It is an object of the present invention, in an LCD panel pattern generator for generating high-speed pixel signals by an interleave method, whether the total number of pixels of the LCD panel is odd or even without increasing the capacity of the pattern storage memory. An object of the present invention is to provide a pattern generation device for an LCD panel that does not generate a pixel signal.

[0007]

According to the present invention, the same number of buffer memories as the number of storage areas provided in the pattern storage memory, and the pixel data read from any storage area can be written in this buffer memory. When the writing prohibition to the memory occurs, the switching circuit that operates to write the pixel data read from the top address of the pattern storage memory to the first buffer memory where the writing prohibition occurs, and the buffer memory LCD composed of a multiplexing circuit for multiplexing read pixel data in the order assigned to the buffer memory
A pattern generator for a panel is provided.

According to the structure of the present invention, when the final pixel data to be given to the LCD panel is read from the pattern storage memory, the storage area of the pattern storage memory from which the pixel data is read is given to each storage area. If it is not the final storage area in the specified order, only valid pixel data is written to the buffer memory allocated at that time, writing of pixel data to other buffer memories is prohibited, and the pattern is stored in the next cycle. The leading pixel data read from the memory is written to the buffer memory in which writing is prohibited in order, and the pixel data of the odd number array from these multiple buffer memories is also the last pixel data, followed by the leading pixel data. Data can be generated.

[0009]

FIG. 1 shows an embodiment of the present invention. Parts corresponding to those in FIG. 6 are denoted by the same reference numerals. The pattern storage memory 1 has a case where it has four storage areas A, B, C and D as in the case of FIG. In each of the storage areas A, B, C, D of the pattern storage memory 1, the first pixel data, the second pixel data, the third pixel data are stored in the order of the storage areas A, B, C, D in the same manner as described with reference to FIG. Pixel data of 4th pixel data is stored, the 5th pixel data is returned to the storage area A again, and this is repeated until each pixel data up to the final pixel data is stored in each storage area A, B, C, D. Will be sorted and memorized.

Pixel data read from the respective storage areas A, B, C, D are 4-input 1-output type switching circuits 11A, 11
B, 11C, 11D input terminals I ₁ , I ₂ , I ₃ , I
Entered in ₄ . Input terminals I _{1 to} I _{4 of the} switching circuit 11A
The pixel data read from the storage areas A to D is input to the input terminals I to I _4, and the pixel data read from the storage areas B, C, D, and A is input to the input terminals I _{1 to} I ₄ of the switching circuit 11B in order. , the input terminal I ₁ in ~I ₄ storage area C of the switching circuit 11C, D, a, enter the pixel data read from B in order, the input terminal I ₁ ~I ₄ of the switching circuit 11D storage area D, Pixel data read from A, B, and C are sequentially input. In this way, by shifting the order of the storage areas input to the input terminals I _{1 to} I ₄ by one, each switching circuit 11
When the switching state of A to 11D is switched to the first state in which the input terminal I ₁ is selected, the switching circuit 11A extracts the pixel data read from the storage area A, and the switching circuit 11B outputs the pixel data read from the storage area B. The switching circuit 11C takes out the pixel data read from the storage area C, and the switching circuit 11D takes out the pixel data read from the storage area D.

The switching state of the switching circuits 11A to 11D is set to the second state.
When the state is switched to the state in which the input terminal I ₂ is connected to the output terminal, the switching circuits 11A to 11D output the pixel data read from the storage areas B, C, D, and A, respectively. When switched to the third state where the switching circuit 11A~11D connects the input terminal I ₃ to the output terminal, the switching circuit 11A~11D each storage area C, D, A, and outputs the pixel data read from B. Switching circuit 11A-
When 11D switches to the fourth state in which the input terminal I ₄ is connected to the output terminal, each switching circuit 11A to 11D outputs the pixel data read from the storage areas D, A, B, and C.

Buffer memories 12A, 12B, 12C and 12D are connected to the output sides of the switching circuits 11A to 11D. The buffer memories 12A to 12D can independently perform writing and reading. For example, a FIFO (First In First Out Memory) can be used. Therefore, the write pulse and the read pulse are separately provided in the write pulse generator 13 and the read pulse generator 14,
A write pulse WP is separately provided to each write pulse input terminal W and read pulse input terminal R of each buffer memory 12A to 12D.
And a read pulse RP are supplied.

Pixel data read out from the buffer memories 12A to 12D is input to the multiplexing circuit 2 at respective input terminals I _{1 to} I.
₄ , and the multiplexing circuit 2 outputs high-speed pixel data at a speed about 4 times faster than the reading speed of the pattern storage memory 1. The multiplexed pixel data is converted into color pixel data by the conversion table 3, and the output terminal 4 outputs the color pixel data. Further, the synchronizing signal output terminal 5 generates and outputs a horizontal synchronizing signal H and a vertical synchronizing signal V from the multiplexed high speed data.

In the above configuration, when the total number of pixels of the LCD panel under test is a multiple of 4, the switching circuit 11A
11D are in the first switching state, that is, while the input terminal I ₁ is connected to the output terminal, the buffer memories 12A to 12D
The read outputs of the respective storage areas A to D are supplied to 2D, and are supplied as they are to the multiplexing circuit 2 through the buffer memories 12A to 12D and are multiplexed. If the total number of pixels of the LCD panel under test is a multiple of 4, the final pixel data is always read from the final storage area D among the storage areas A to D ordered in the order of multiplexing. Therefore, the pixel data read in the next cycle is sequentially stored from the head buffer memory 12A and supplied to the multiplexing circuit 2. Therefore, the interleave operation is correctly performed even at the seam of the screen.

Next, the total number of pixels of the LCD panel under test is compared.
If it is a multiple of 5, the screen
The final pixel data 5N should be read from the storage area A
become. The final pixel data 5N is read from the storage area A.
Read from other storage areas B, C, D at that time.
Exposed pixel data X₁, X_Two, X_ThreeIs unnecessary pixel day
Become Therefore, here, the pixels after the last pixel data
Data X₁, X_Two, X _ThreeUnnecessary pixel data, final pixel data
The pixel data before the data is called effective pixel data
To The final pixel data is detected by the LCD panel under test.
Since the total number of pixels in the channel is known, the address generator
It can be detected by the number of addresses output from 9.
The final pixel data is read from any of the storage areas A to D
You can specify what will be served. This detection is a control unit
8 can be executed.

When the final pixel data is read from the storage area A, immediately after that, the control section 8 gives a write inhibit signal to the write pulse generator 13 to open the buffer memory to which the effective pixel data is supplied. The write pulse WP applied to the other buffer memories is excluded. That is, when the final pixel data 5N is read from the storage area A, the write pulse given to the buffer memories 12B, 12C, 12D is prohibited, and the write pulse is given only to the buffer memory 12A.

Here, the writing and reading speeds of the buffer memories 12A to 12D will be described. For example, the FIFO memory can perform writing and reading independently. Therefore, by setting the frequency of the write pulse higher than the frequency of the read pulse, the buffer memories 12A to 12A are
It is possible to always maintain a state in which a certain amount of pixel data is accumulated in D. When the buffer memories 12A to 12D are filled with pixel data, the supply of the write pulse is temporarily stopped. When the amount of pixel data decreases to a certain amount,
Restart writing. The reading of the buffer memories 12A to 12D is executed at a constant speed without being lost once the reading is started.

As described above, the buffer memories 12A ...
Since a certain amount of pixel data is always stored in the 12D, there is no shortage in reading pixel data even if the unnecessary pixel data X ₁ , X ₂ , and X ₃ are not written.
Therefore, the leading pixel data read in the next cycle may be sequentially written to the write-protected buffer memory. This switching of writing is performed by switching circuits 11A to 11D.
Runs. That is, the total number of pixels of the LCD panel under test is 5
If it is a multiple of, the final pixel data 5N will be read from the storage area A at the end of the first image drawing, as shown in FIG. Therefore, the switching circuits 11A to 11
When D is switched from the first switching state (the state in which the input terminal I ₁ is connected to the output terminal) to the second switching state (the state in which the input terminal I ₂ is connected to the output terminal), it is read in the next cycle. Pixel data “1” below the first pixel data,
"2" and "3" are sequentially buffer memories 12B, 12C,
Data can be written in the blank portion of 12D, and the pixel data “4” is written in the buffer memory 12A.

When the second drawing is performed in the second switching state,
The final pixel data 5N is written in and read out from the buffer memory 12B as shown in FIG. Therefore, in this case, the buffer memories 12C and 12D are write-protected and the switching circuits 11A to 1A are used at the start of the third drawing.
If the 1D state is switched to the third switching state (the state in which the input terminal I ₃ is connected to the output terminal), the first pixel data “1” and “2” read in the next cycle are stored in the buffer memories 12C and 12D. The pixel data "3" and "4" are written in the blank portion and written in the buffer memories 12A and 12B.

When the switching circuits 11A to 11D are in the third switching state (the input terminal I ₃ is connected to the output terminal) and the screen is drawn for the third time, the final pixel data 5N is written in the buffer memory 12C and read. Be done. Therefore, in this case, writing is prohibited only for the buffer memory 12D, and the switching states of the switching circuits 11A to 11D are switched to the fourth switching state (the state in which the input terminal I ₄ is connected to the output terminal). As a result, the leading pixel data "1", "2", "3", "4" read in the next cycle are buffer memories 12D, 12A, 12B, 12C as shown in FIG.
Are written in order.

The switching state of the switching circuits 11A to 11D is the fourth.
When one screen is drawn in the switching state, the final pixel data 5N is read from the storage area D. Therefore, in this case, write prohibition does not occur and the switching circuits 11A to 11A
The state of D is returned to the first switching state. As a result, the leading pixel data “1” read in the next cycle,
“2”, “3” and “4” are buffer memories 12A and 12
B, 12C, and 12D are written in this order, the state returns to the initial state, and this is repeated thereafter.

FIG. 4 shows pixel data read from the pattern storage memory 1 and the buffer memories 12A, 12B, 1
The relationship between the pixel data written in 2C and 12D and the relationship between the write pulses of the buffer memories 12A to 12D is shown in a waveform diagram. This example also shows a case where the storage area provided in the pattern storage memory 1 is 4, and the total number of pixels of the LCD panel under test is a multiple of 5. Therefore, the final pixel data 5N of the first drawing is read from the buffer memory 12A.
At this time, unnecessary pixel data X ₁ , X ₂ , X ₃ are read from the storage areas B, C, D. The buffer memory 12B to which the unnecessary pixel data X ₁ , X ₂ , X ₃ are given,
12C, the 12D, the supply of the write pulse is inhibited as shown between time points T ₁ through T ₂ in FIG.

At the same time, the switching circuits 11A to 11D switch from the first state to the second state, so that the buffer memories 12B, 12C and 12D in which writing is prohibited read at the beginning of the next cycle. Pixel data of "1",
"2" and "3" are written, and the pixel data "4" is written in the buffer memory 12A. Buffer memory 1
Since the writing speed of 2A to 12D is selected to be faster than the reading speed, each of the buffer memories 12A to 1D is selected.
A certain amount of pixel data is always stored in 2D. Therefore, even if the writing of the pixel data is temporarily prohibited, the reading will not be hindered. After the final pixel data 5N is written in the buffer memory 12A, the buffer memories 12B, 12C, 12D are indicated by the dotted line in the next cycle.
Writing is performed in the order of.

FIG. 5 shows a state of pixel data read from the buffer memories 12A to 12D and multiplexed pixel data. FIG. 5A shows buffer memories 12A to 12D.
Shows the read pulse applied to. 5B shows pixel data read from each of the buffer memories 12A to 12D by a read pulse, and FIG. 5C shows a multiplexed output of the multiplexing circuit 3.
In the above description, the case where the number of storage areas of the pattern storage memory 1 is 4 and the total number of pixels of the LCD panel under test is a multiple of 4 and 5 has been explained, but even if the total number of pixels is a multiple of 3. ,
The interleave operation can be controlled to operate normally by switching the switching circuits 11A to 11D.
Even if the total number of pixels is not a multiple of 3, 4, or 5, the same control can be performed when the total number of pixels is a multiple of 2 or a multiple of 6. 4
In the case of an even multiple other than the multiple of, the buffer memories into which the final pixel data is written are 12B and 12D. When the last pixel data is written in the buffer memory 12D and drawing of one screen is completed, the switching circuits 11A to 11D maintain the first switching state, and when the last pixel data is written in the buffer memory 12B. , Switching circuits 11A-1
It is only necessary to switch 1D to the third switching state, that is, to write the first pixel data “1” read from the storage area A into the buffer memory 12C.

Also, the number of storage areas provided in the pattern storage memory 1 can be selected to a number other than four. If the number of storage areas is increased, the advantage that the reading speed of the pattern storage memory 1 can be slowed down is obtained.

[0026]

As described above, according to the present invention, by providing the buffer memory and the switching circuit for switching the pixel data read from the plurality of storage areas and supplying the same to the buffer memory, the LCD panel to be tested is provided. Even when the total number of pixels is not a multiple of the number of storage areas provided in the pattern storage memory 1, the interleave operation can be performed normally and the high speed multiplexed signal can be generated. Therefore, it is possible to provide a highly versatile LCD panel test pattern generator.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an LCD panel test pattern generator according to the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a diagram for explaining the operation of the embodiment shown in FIG.

4 is a waveform chart for explaining the operation of the embodiment shown in FIG.

5 is a waveform diagram for explaining the operation of the embodiment shown in FIG.

FIG. 6 is a block diagram for explaining a conventional technique.

FIG. 7 is a diagram for explaining the operation of FIG.

[Explanation of symbols]

 1 Pattern Storage Memory 2 Multiplexing Circuit 11A-11D Switching Circuit 12A-12D Buffer Memory 13 Write Pulse Generator 14 Read Pulse Generator

Claims (1)

[Claims] 1. A. First Embodiment A pattern storage memory having n storage areas ordered from 1 to n according to a multiplexing order of n pixel data read at one time; N pixel memories to which n pieces of pixel data read from the pattern storage memory are written, and writing and reading can be independently performed; If the buffer memory in which the last pixel data to be given to the LCD panel under test is written is a buffer memory other than the buffer memory corresponding to the nth storage area in the ordered storage area, the last pixel from the first buffer memory in the above order. A write pulse generator that applies a write pulse to each buffer memory up to the buffer memory in which data is written, and disables writing to the other buffer memories; When writing prohibition occurs, the connection between the above storage area and the buffer memory is provided so that the pixel data at the beginning of the screen read in the next cycle is given to the beginning buffer memory where writing is prohibited. A pattern generation device for a liquid crystal display panel test, comprising a switching circuit for switching relationships.