JPH10173520A5 - - Google Patents
Info
- Publication number
- JPH10173520A5 JPH10173520A5 JP1996329462A JP32946296A JPH10173520A5 JP H10173520 A5 JPH10173520 A5 JP H10173520A5 JP 1996329462 A JP1996329462 A JP 1996329462A JP 32946296 A JP32946296 A JP 32946296A JP H10173520 A5 JPH10173520 A5 JP H10173520A5
- Authority
- JP
- Japan
- Prior art keywords
- signal
- outputs
- control signal
- control
- feedback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8329462A JPH10173520A (ja) | 1996-12-10 | 1996-12-10 | Ｐｌｌ回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8329462A JPH10173520A (ja) | 1996-12-10 | 1996-12-10 | Ｐｌｌ回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10173520A JPH10173520A (ja) | 1998-06-26 |
| JPH10173520A5 true JPH10173520A5 (cs) | 2004-11-11 |
Family
ID=18221653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8329462A Pending JPH10173520A (ja) | 1996-12-10 | 1996-12-10 | Ｐｌｌ回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10173520A (cs) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4623787B2 (ja) * | 1999-11-15 | 2011-02-02 | 三洋電機株式会社 | Ｐｌｌシンセサイザ回路 |
| KR100652390B1 (ko) | 2004-12-11 | 2006-12-01 | 삼성전자주식회사 | 데드락 방지회로를 구비하는 위상동기 루프 회로 및 이의데드락 방지방법 |
| JP5229125B2 (ja) | 2009-06-15 | 2013-07-03 | 富士通株式会社 | Ｐｌｌ回路および電圧制御発振器 |
| JP5006417B2 (ja) | 2010-01-28 | 2012-08-22 | 日本電波工業株式会社 | Ｐｌｌ発振回路 |
-
1996
- 1996-12-10 JP JP8329462A patent/JPH10173520A/ja active Pending
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