JPH10135936A - Clock selection method, clock switching method and clock selection unit for line switching device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress as much as possible errors of signal transmission at the time of clock changeover and to output a stable master clock by selecting a maximum level within a clock reproducing level range, set beforehand from the input signals of plural systems. SOLUTION: The level detection judging parts 110-1n0 of this clock selection unit 10 input the input signals BIP1-BIPn of the (n) systems and output data signals DATA1-DATAn and output clock signals CKL1-CKLn to the outside. In this case, a level rage judging part 113 judges the clock reproducing level range by minimum and maximum setting signals MIN and MAX which has been set beforehand from the minimum level setting part 200 and a maximum level setting part 300 and inputs level range judgment signals DETEC1-DETECn to a clock selection system judgment part 400. In this case, the output clock signal of BIPm of the input signals maximum within the level range is selected, and the selected clock signal MASTERCLK is outputted through a clock selection part 500.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication signal line switching apparatus, and more particularly to a master clock selection method, a switching method, and a selection unit.

[0002]

2. Description of the Related Art In the prior art, a predetermined clock among the clocks of a transmission line is selected as a master clock of a line switching device for communication signals, and switching to another clock due to failure of the selected transmission line or the like is not possible. Then, the interruption of the input signal from the transmission line is determined, and the clock signal of another transmission line is selected and switched in a predetermined order.

[0003]

In the conventional clock selection method and switching method, the master clock is selected in a predetermined order, so that the clock of the selected transmission line is not optimal, and the selected transmission line is not selected. When switching to another clock due to a failure in the path, etc., the switching of the clock signal is performed because the clock signal of the other transmission path is selected in a predetermined order after judging the interruption of the input signal of the selected transmission path. In some cases, the master clock is also interrupted because the clock signal has been interrupted so far, and there is a problem that an error in signal transmission occurs.

In order to prevent the master clock from being interrupted, even if a method is adopted in which the clock signal is switched when the clock signal serving as the master clock falls below a predetermined level, the level of the clock signal may fluctuate on the time axis. There is a problem that the clock signal is easily switched.

An object of the present invention is to provide a clock selection method, a switching method, and a selection unit which enable a signal transmission by selecting a stable clock as a master clock and minimizing a signal transmission error at the time of clock switching. It is in.

[0006]

A clock selection method for a line switching device according to the present invention is a clock selection method for starting a line switching device, which is a master clock of the line switching device connected to a plurality of input signals. A clock recovery unit that separates an input signal into a data signal and an output clock signal defines a maximum level and a minimum setting level that can be clock-reproduced, and a predetermined safe level margin with respect to the maximum level and the minimum level. Set the maximum setting level and the minimum setting level by adjusting, detect the level of each of a plurality of input signals, each of the detected levels,
Judge whether it is within the range between the maximum setting level and the minimum setting level, judge and select the clock signal that is within the range between the maximum setting level and the minimum setting level and has the highest level, The clock signal is output as a master clock to the system in the line switching device.

A clock switching method according to the present invention is a clock switching method for a clock serving as a master clock during the operation of a line switching device, wherein a clock recovery unit for separating an input signal into a data signal and an output clock signal is used. Specify the maximum and minimum levels that can be played, set the maximum and minimum levels by adjusting the level margin on the safe side with respect to the maximum and minimum levels, and set the maximum and minimum levels for the master clock. Detects the level of the input signal, and detects the level of each of the multiple input signals input to the line switching device when the level of the detected input signal falls below the minimum setting level or above the maximum setting level Each of the detected levels is within the range between the maximum and minimum setting levels. Judge whether or not there is a clock signal that is within the range between the maximum setting level and the minimum setting level, and select the clock by judging the clock signal of the highest level, and select the clock from the previous master clock. ,
The clock is switched to the selected clock and output to the system in the line switching device as the master clock.

A clock selection unit according to the present invention is a clock selection unit for selecting a clock serving as a master clock of a line switching device connected to a plurality of input signals, and includes a maximum level setting unit for setting a maximum setting level, A minimum level setting unit that sets the setting level, a clock recovery unit that corresponds to each of multiple input signals, separates the output data signal and output clock signal from each input signal, and detects the level of the input signal A level detection unit that outputs a level detection signal and a level range determination unit that determines whether the level detection signal is in a level range between the minimum setting signal and the maximum setting signal and outputs a level determination signal. Having a plurality of level detection determination units, and a level signal input from the plurality of level detection determination units, and a level determination signal, A clock selection system determining unit that determines a clock to be a star clock and outputs a clock selection signal; and, based on the clock selection signal, an output clock signal to be a master clock from output clock signals input from a clock recovery unit. A clock selection unit for selecting and outputting the selected clock signal to the outside.

In a system in which one system is selected from clock signals extracted from a plurality of transmission paths to be used as a master clock and used as a synchronization source of an internal clock signal, a clock signal is selected from a plurality of clock signals when the clock signal is selected. Since the clock signal level is within a range having a preset safety-side level margin with respect to the clock reproducible minimum and maximum levels and selects the highest level of the clock signal, the master which mainly needs to switch due to the level drop is generated. As a clock, the selected clock signal has stability.

The switching of the clock signal serving as the master clock is performed not only after the output of the clock signal is cut off, but also when the clock signal becomes lower than the minimum set level having a safe margin to the minimum level of clock reproducibility. Since the switching is performed when the clock reproducible maximum level becomes equal to or lower than the maximum set level having a safe level margin, the clock signal is not likely to be interrupted, and the signal transmission can be performed with a minimum signal transmission error.

The minimum setting level is a safe and lowest level.
Since the maximum setting level is set to the safe and maximum level, the allowable range is wide, and the maximum setting level is not easily changed by the time-series fluctuation of the clock signal serving as the master clock.

[0012]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a clock selection unit of a line switching apparatus according to the present invention. In the figure, reference numeral 10 denotes a clock selection unit, 110 denotes a 1-system level detection determination unit, 111 denotes a clock recovery unit, 112 denotes a level detection unit,
113 is a level range judgment unit, 1n0 is an n-system level detection judgment unit (n is a positive natural number), 200 is a minimum level setting unit,
300 is a maximum level setting unit, 400 is a clock selection system determination unit, 500 is a clock selection unit, BIPI is a 1-system input signal, DATAAl is a 1-system output data signal, CLKl is a 1-system output clock signal, and LEVl is 1 The system level signal DETECTl is the system level determination signal BIPn
Is an n-system input signal, CLKn is an n-system output clock signal, LEVn is an n-system level signal, and DETECTn is n
System level judgment signal, MIN is a minimum setting signal, MAX is a maximum setting signal, CLK SEL is a clock selection signal, M
ASTER CLK is a selection clock signal.

FIG. 2 is a timing chart at the time of clock switching according to the embodiment of the present invention. In the drawing, reference symbol min0 denotes a minimum clock reproducible level, max0 denotes a clock reproducible maximum level, min denotes a minimum setting level, and max denotes a maximum setting. Level, LEVk is a k-system level detection signal, LE
Vm is an m-system level detection signal, α is a level range, and β is a clock reproduction level range.

In the clock selection unit 10 of the present invention,
As shown in FIG. 2, a level range in which the clock can be reproduced by the clock reproduction unit 111 is defined as a minimum clock reproducible level min0 to a maximum clock reproducible level max0 (hereinafter referred to as a clock reproduction level range β). Further, the range in which the clock can be reliably reproduced within the clock reproduction level range β is defined as a minimum setting level min to a maximum setting level max
Is set to the level range α indicated by.

As shown in FIG. 1, according to the present invention, a clock selection unit 10 to which input signals BIP1 to BIPn from n transmission lines are input corresponds to a system of each transmission line and converts each input signal BIP1 to BIPn. Received output data signals DATA1 to DATAn, output clock signal CK
L1 to CKLn, level signals LEV1 to LEVn, and n number of level detection / determination units 110 to 1n0 that output the level determination signals DETECT1 to DETECTn, and a minimum level setting unit 2 that sets the minimum setting level min described above.
00, a maximum level setting unit 300 for setting the maximum set level max, and a clock to be used as the master clock MASTER CLK based on the level signals LEV1 to LEVn input from the level detection determination units 110 to 1n0 and the level determination signals DETECT1 to DETECTn. And a clock selection system determining unit 400 that outputs a clock selection signal CLKSEL
Output clock signals CLK1 to CLK input by EL
and a clock selection unit 500 that selects an output clock signal to be used as a master clock from n and outputs the selected clock signal as a selected clock signal MASTER CLK.

The 1-system level detection / judgment unit 110 receives the input signal B
A clock recovery unit 111 that separates and outputs an output data signal DATA1 and an output clock signal from IP1, and a level detection signal LEV1 that detects the level of an input signal BIP1
, And a level detection signal LE
A level range determining section 113 for determining whether or not V1 is within a level range α between the minimum setting signal MIN and the maximum setting signal MAX, and outputting a level determination signal DETEC1, and an n-system level detection determining section 1n1 And the other level detection determination units have the same configuration.

In the minimum level setting section 200, the minimum setting level min exceeding the clock reproducible minimum level min0
Is output, and the maximum level setting unit 300 outputs a maximum setting signal MAX indicating a maximum level max lower than the clock reproducible maximum level max0. A level range α having a predetermined level margin with respect to the clock reproduction level range is set by the minimum setting signal MIN and the maximum setting signal MAX, and is input to the level range determination unit 113.

The clock recovery section 111 of the system 1 level detection judging section 110 separates and outputs the system 1 output data signal DATA1 and the system 1 output clock signal CLK1 from the system 1 input signal BIPN1. The output level detecting section 112 detects the level of the primary system input signal BIPI, outputs the primary system level detection signal LEVl, and outputs the level range determination section 113.
In the level range α, the 1-system level detection signal LEVl
Is determined, and a 1-system level range determination signal DETECTl is output. The same operation is performed with the same configuration for input signals from n transmission paths,
The level signals LEVl to LV
EVn and level range judgment signals DETECTl to DET
ECTn is input.

At the start-up of the device, the clock selection system determining unit 400 determines whether or not the input signals BIPI to BIPn
Based on the level range determination signals DETECTl to DETECTn, the input signal levels of the input signals BIPl to BIPn fall within the level range α, and the system of the input signal BIPm (m: natural number of 1 ≤ m ≤ n) having the highest level among them. Is output, and the clock selection unit 500 outputs the clock selection signal CLK SE
L selects the m-system output clock signal CLKm, outputs the selected clock signal MASTER CLK, and uses it as the synchronization source for the clock signal of the system in the device (initial state in FIG. 2).

The input levels of the input signals BIP1 to BIPn fluctuate on the time axis and the input level of the other system may exceed the input level of the input signal BIPm. However, in the embodiment of the present invention, the selected m is selected. As long as the input level of the system is within the set level range α, the clock is not switched (the clock selection range of the m system in FIG. 2).

The clock selection determining unit 400 determines that the level detection signal LEVm of the selected m-system input signal BIPm is out of the level range α indicated by the minimum setting signal MIN and the maximum setting signal MAX. in case of,
The clock selected by the selected clock signal MASTER CLK is switched. In this case, the clock selection system judging unit 4 performs the same sequence as when the device starts up.
In the input signals BIPl to BIPn, the input levels of the input signals BIPl to BIPn are within the level range α by the level range determination signals DETECTl to DETECTn, and the input signal BIPk ( A clock selection signal CLK SEL for selecting a system of k: 1 ≦ k ≦ n is output. The clock selection unit 500 selects the k-system output clock signal CLKk by the clock selection signal CLK SEL, and selects the selected clock signal MASTER. CLK is output and used as a synchronization source of the internal clock signal (k-system clock selection range in FIG. 2).

[0022]

As described above, in the present invention, one system is selected from clock signals extracted from a plurality of transmission paths to be used as a master clock and a clock signal is selected in a system used as a synchronization source of a clock signal in the device. If you do
From among a plurality of clock signals, the clock signal level is within a range having a preset safety-side level margin with respect to the clock reproducible minimum maximum level, and the clock signal of the highest level is selected. The selected clock signal has the effect of having stability as a master clock that requires switching due to a drop.

The switching of the clock signal serving as the master clock is performed not when the clock signal output is cut off but when the clock signal falls below the minimum set level having a safe margin for the clock reproducible minimum level. Therefore, there is no danger that the clock signal will be interrupted, and there is an effect that signal transmission can be performed while minimizing signal errors during signal switching.

Further, since the minimum setting level is set to the safe and minimum level and the maximum setting level is set to the safe and maximum level, the tolerance for the time-series fluctuation of the clock signal serving as the master clock is reduced. The effect is that the master clock is stable because it is wide and not easily changed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock selection unit of a line switching device according to the present invention.

FIG. 2 is a timing chart at the time of clock switching according to the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 clock selection unit 110 1 system level detection judgment unit 111 clock regeneration unit 112 level detection unit 113 level range judgment unit 1n0 n system level detection judgment unit 200 MIN level setting unit 300 MAX level setting unit 400 clock selection system judgment unit 500 clock selection Unit BIPL 1-system input signal DATAI 1-system output data signal CLKl 1-system output clock signal LEV1 1-system level signal DETECT1 1-system level determination signal BIPn n-system input signal CLKnn n-system output clock signal LEVn n-system Level signal DETECTn n-system level determination signal MIN minimum setting signal MAX maximum setting signal CLK SEL clock selection signal MASTER CLK selection clock signal min0 minimum clock reproducible level max0 clock recovery Ability maximum level min minimum setting level max maximum set level LEVk k based level detection signal LEVm m based level detection signal α level range β clock reproduction level range of

Claims (3)

[Claims] 1. A method for selecting a clock, which is a master clock of a line switching device connected to a plurality of input signals, when starting up the line switching device, wherein the input signal is converted into a data signal and an output clock signal. A maximum level and a minimum level at which the clock can be reproduced by the clock regeneration unit to be separated are defined, and a maximum setting level and a minimum setting level are set by adjusting a predetermined safety-side level margin with respect to the maximum level and the minimum level. Detecting a level of each of the plurality of input signals; determining whether each of the detected levels is within a range between the maximum setting level and the minimum setting level; Determining and selecting the highest level of the clock signal that is in a range between the level and the minimum set level; A method for selecting a clock for a line switching device, comprising: outputting a signal as the master clock to a system in the line switching device. 2. A clock switching method for a clock serving as the master clock during operation of the line switching device, wherein a clock recovery unit that separates the input signal into a data signal and an output clock signal can perform clock recovery. A maximum level and a minimum level, a maximum setting level and a minimum setting level obtained by adjusting a predetermined safety-side level margin with respect to the maximum level and the minimum level, and a clock serving as the master clock. A plurality of the input signals input to the line switching device when the detected level of the input signal becomes one of the minimum set level or less and the maximum set level or more. Each of the levels is detected, and each of the detected levels is the maximum set level and Determining whether the clock signal is within the range between the minimum setting level and the clock signal having the highest level within the range between the maximum setting level and the minimum setting level. A clock of the line switching device, wherein the selected clock is switched from the clock as the master clock to the selected clock, and is output to the system in the line switching device as the master clock. Switching method. 3. A clock selection unit for selecting a clock serving as a master clock of a line switching device connected to a plurality of input signals, comprising a maximum level setting unit for setting a maximum setting level, and a minimum for setting a minimum setting level. A level setting unit, a clock recovery unit corresponding to each of the plurality of input signals, separating and outputting an output data signal and an output clock signal from each of the input signals, and detecting a level of the input signal to obtain a level. A level detection unit that outputs a detection signal; and a level range determination unit that outputs a level determination signal by determining whether the level detection signal is in a level range between the minimum setting signal and the maximum setting signal. A plurality of level detection determination units having the level signals input from the plurality of level detection determination units, and the level determination signal A clock selection system determining unit that determines a clock to be the master clock and outputs a clock selection signal; and the master clock is selected from the output clock signal input from the clock recovery unit by the clock selection signal. A clock selecting unit for selecting an output clock signal to be output and outputting the selected clock signal to the outside as a selected clock signal.