JPH10135344A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a lower electrode having a small parasitic capacitance and low resistance. SOLUTION: On a semiconductor substrate 10 with element isolating regions 18, a Si-Ge layer 21 and Si layer 22 are formed, the Si layer 22 is patterned to form an emitter regions 22a of a bipolar transistor. The Si-Ge layer 21 is patterned to form a base region 21a of the bipolar transistor and resistor 21b and lower electrode 21c of a capacitor element on the element isolating regions 18. Thus the base region 21a, resistor 21b and lower electrode 21c of the capacitor element are formed in the same step to obtain a semiconductor device. The capacitive element is disposed on the element-isolating region to result in a small parasitic capacitance. The lower electrode 21c is composed of the Si-Ge layer 21, this lowering the resistance value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a capacitive element provided on a surface side of a semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art Capacitors provided on the front side of a semiconductor substrate include, for example, those having a lower electrode made of a diffusion layer provided on a surface layer of the semiconductor substrate and those provided on an element isolation region of the semiconductor substrate. Some have a lower electrode made of polysilicon. Such a capacitive element has a configuration including a dielectric film provided on the upper surface of the lower electrode and an upper electrode provided on the upper surface of the dielectric film.

[0003] The lower electrode formed of a diffusion layer is formed in the same step as the collector extraction diffusion layer of a vertical bipolar transistor provided on the surface side of the same semiconductor substrate when a capacitor is arranged, for example. The lower electrode made of polysilicon is formed in the same step as the polysilicon base electrode of the bipolar transistor, for example.

By forming the lower electrode as described above, a semiconductor device having a bipolar transistor and a capacitor can be manufactured with a smaller number of steps.

[0005]

However, the semiconductor device having the above-described capacitance element has the following problems. That is, the collector extraction diffusion layer of the vertical bipolar transistor needs to be formed at a sufficient depth and high concentration to be connected to the buried collector in the semiconductor substrate. For this reason, the lower electrode formed in the same step as the collector extraction diffusion layer reaches a depth reaching the opposite conductive type substrate main material on which the buried collector is arranged and has a high impurity concentration. Therefore, a large parasitic capacitance occurs at the PN junction between the main substrate material and the lower electrode.

When the capacitor has a lower electrode made of polysilicon, the lower electrode is disposed on the element isolation region, so that the parasitic capacitance formed below the lower electrode is greatly reduced. Can be reduced. However, when the lower electrode is formed in the same step as the polysilicon base electrode of the bipolar transistor, the resistance value is determined by the characteristics of the bipolar transistor. For this reason, there is a problem that the resistance value of the lower electrode increases and the frequency characteristics deteriorate.

[0007]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing a semiconductor device which have been made to solve the above-mentioned problems. That is, the semiconductor device according to claim 1 of the present invention is a semiconductor device in which a capacitive element is arranged on an element isolation region of a semiconductor substrate made of silicon.
The lower electrode of the capacitor is formed of a semiconductor film having higher carrier mobility than silicon. As the semiconductor film, silicon containing germanium is preferably used.

In the above semiconductor device, since the lower electrode is formed of a semiconductor film having a higher carrier mobility than silicon, the resistance value of the lower electrode is lower than that of the lower electrode made of polysilicon or the semiconductor substrate made of silicon. The resistance value with respect to the impurity amount is smaller than that of the lower electrode made of the diffusion layer. In addition, since the lower electrode of the capacitor is arranged on the element isolation region, the parasitic capacitance formed below the lower electrode is reduced.

According to a third aspect of the present invention, there is provided a semiconductor device in which a heterojunction bipolar transistor is arranged together with the capacitive element on the front surface side of a semiconductor substrate, wherein a base region of the bipolar transistor and the capacitive element are provided. The upper electrode is made of the same semiconductor film as described above. Further, a resistor made of the semiconductor film may be provided on the element isolation region,
Further, as the semiconductor film, silicon containing germanium is preferably used.

In the semiconductor device according to the third aspect, the base region of the bipolar transistor and the lower electrode of the capacitive element are formed of a semiconductor film having higher carrier mobility than silicon. For this reason, the lower electrode is provided in the first aspect.
The resistance value is small similarly to the lower electrode in the described semiconductor device, and furthermore, it is formed in the same step as the base region of the bipolar transistor. Moreover, since the lower electrode is arranged on the element isolation region, the parasitic capacitance formed below the lower electrode is reduced. When a resistor made of the semiconductor film is provided on the element isolation region, the resistor has a smaller resistance value than a resistor made of polysilicon.

According to a sixth aspect of the present invention, in the semiconductor device, the lower electrode of the capacitor provided on the element isolation region of the semiconductor substrate has a two-layer structure of a lower polysilicon film and an upper semiconductor film. It is characterized by consisting of. As the semiconductor film, silicon containing germanium is preferably used.

In the semiconductor device, the lower electrode of the capacitor has a two-layer structure of a polysilicon film and the semiconductor film. Become.

According to an eighth aspect of the present invention, there is provided a semiconductor device in which a heterojunction bipolar transistor is arranged together with the capacitive element according to the sixth aspect on the surface side of the semiconductor substrate. The region is made of the semiconductor film, and the base extraction region is made of the semiconductor film and a polysilicon film thereunder. Further, a resistor composed of the semiconductor film and the polysilicon film may be provided on the element isolation region, and silicon containing germanium is preferably used as the semiconductor film.

In the semiconductor device according to the present invention, the base extraction region of the bipolar transistor and the lower electrode of the capacitor are formed in a two-layer structure of a semiconductor film having a higher carrier mobility than silicon and a polysilicon film. For this reason, the lower electrode has a lower resistance than the lower electrode in the semiconductor device according to the first aspect, and can have a lower resistance as in the case of the base extraction region of the bipolar transistor. Further, the lower electrode is formed in the same step as the base extraction region. Moreover, since the lower electrode is arranged on the element isolation region, the parasitic capacitance formed below the lower electrode is reduced. When a resistor made of the semiconductor film and the polysilicon film is provided on the element isolation region, the resistor has a smaller resistance value than a resistor made of polysilicon.

Further, a method of manufacturing a semiconductor device according to claim 11 of the present invention is a method of manufacturing a semiconductor device in which a heterojunction bipolar transistor and a capacitor are provided on a surface side of a semiconductor substrate made of silicon. Do as follows. First, a semiconductor film having higher carrier mobility than silicon is formed over a semiconductor substrate provided with an element isolation region. Next, a base region made of the semiconductor film is formed on the active region in the bipolar transistor formation region by patterning the semiconductor film,
A lower electrode of the capacitor composed of the semiconductor film is formed on the element isolation region.

In the above-described method of manufacturing a semiconductor device, a base region of a bipolar transistor and a lower electrode of a capacitor are formed by patterning a semiconductor film having a higher carrier mobility than silicon. For this reason, a low-resistance lower electrode is formed in the same manufacturing process as that of the bipolar transistor. Further, since the lower electrode is provided on the element isolation region, a capacitor with small parasitic capacitance can be obtained.

A method of manufacturing a semiconductor device according to a thirteenth aspect of the present invention is a method of manufacturing a semiconductor device comprising a bipolar transistor and a capacitor as in the eleventh aspect, and is performed as follows. First, claim 1
A polysilicon film is formed on the same semiconductor substrate as in No. 1, and an opening reaching the active region in the bipolar transistor forming portion of the semiconductor substrate is provided in the polysilicon film. Next, a semiconductor film having a higher carrier mobility than silicon is formed on the polysilicon film so as to cover the inner wall of the opening. Thereafter, a base region made of the semiconductor film is formed by patterning the semiconductor film and the polysilicon film, and a base extraction region made of the polysilicon film and the semiconductor film and a lower electrode of the capacitor are formed on the element isolation region. Form.

In the above-described method of manufacturing a semiconductor device, the base region of the bipolar transistor and the lower electrode of the capacitor are formed by patterning the polysilicon film and the semiconductor layer laminated thereon. For this reason,
The lower electrode having a lower resistance than that of the eleventh aspect is formed by the same manufacturing process as that of the bipolar transistor.
Further, since the lower electrode is provided on the element isolation region, a capacitor with small parasitic capacitance can be obtained.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device and a method of manufacturing the semiconductor device according to the present invention will be described. Here, a description will be given of a manufacturing procedure of a semiconductor device in which an NPN-type heterojunction bipolar transistor, a resistor, and a capacitor are provided on a surface side of a semiconductor substrate made of silicon.
In each embodiment, the same components will be described using the same reference numerals. In addition, the bipolar transistor is replaced by PNP.
In the case of using a mold, all the conductivity types in the embodiment are reversed.

(First Embodiment) FIGS. 1 and 2 are views showing an example of a method of manufacturing a semiconductor device according to the present invention. The first embodiment of the present invention will be described below with reference to these drawings. I do.

First, as shown in FIG. 1A, a P-type silicon substrate 11 having a bipolar transistor formation section A, a resistance element formation section B, and a capacitance element formation section C on the surface side is provided with 900 to 1000 parts. A silicon oxide film 12 is formed to a thickness of about 300 nm by steam oxidation at about ° C.
Next, after an opening 13 for forming a buried collector is formed in the silicon oxide film 12 on the bipolar transistor forming portion A, the opening 13 is formed using a solid diffusion source.
An N-type impurity is diffused into the silicon substrate 11 at the bottom of the opening 13 at a temperature of about 0 to 1250 ° C. by this,
N-type buried collector 1 in the surface layer of silicon substrate 11
4 is formed. As the solid diffusion source, for example, S
b ₂ O ₃ is used. In this case, Sb is diffused into the buried collector 14 as an N-type impurity.

Next, after removing the silicon oxide film 12,
As shown in FIG. 1B, an N-type silicon epitaxial layer 15 having a resistivity of about 0.3 to 5.0 Ω · cm is formed on a silicon substrate 11 to a thickness of about 0.7 to 2.0 μm. I do. As a result, the N-type impurities in the buried collector 14 are diffused into the epitaxial layer 15. Next, a pad oxide film 16 is formed on the epitaxial layer 15 by 10 to 50 n.
m, and a low pressure CVD (Chemic
An anti-oxidation film 17 made of silicon nitride is formed to a thickness of about 50 to 70 nm by an Al Vapor Deposition method.

Thereafter, a resist pattern (not shown) covering the base formation portion and the collector take-out portion of the bipolar transistor formation portion A is formed on the antioxidant film 17, and this resist pattern is used as a mask to form the antioxidant film. 17, the pad oxide film 16 and the surface layer of the epitaxial layer 15 are removed by etching. This etching is performed by RIE
(Reactive Ion Etching), and then the resist pattern is removed.

Next, as shown in FIG.
An element isolation region 18 made of silicon oxide having a thickness of about 0.6 to 1.2 μm is formed on the surface layer of the epitaxial layer 15 exposed from the oxidation preventing film (17) by steam oxidation at about 1100 ° C. Film. As a result, the element isolation region 1 is formed on the surface layer of the epitaxial layer 15 comprising the silicon substrate 11 and the epitaxial layer 15 on the upper surface.
8 is formed.

Thereafter, an antioxidant film (1) on the epitaxial layer 15 is wet-etched with hot phosphoric acid.
7) is removed. Next, a resist pattern (not shown)
Is used as a mask to form an N-type collector extraction region 19 in the bipolar transistor formation portion A by ion implantation and subsequent heat treatment. At this time, in the ion implantation, 5 × 10 ¹⁵ to 2 × 10 ¹⁶ phosphorus ions / c are used.
m ² , and the heat treatment is performed at a temperature of about 950 to 1100 ° C.

Thereafter, a P-type isolation diffusion layer 20 is formed below the element isolation region 18 by ion implantation using a further resist pattern (not shown) as a mask and subsequent heat treatment. At this time, in the above-described ion implantation, boron ions are used as P-type impurities in an amount of 5 × 10 ^{13 to} 5 × 1.
0 ¹⁴ pieces / cm ² are introduced, and the heat treatment is performed for 900 to 10
This is performed at a temperature of about 00 ° C.

Next, the pad oxide film (16) on the epitaxial layer 15 is removed by wet etching using a hydrofluoric acid-based chemical. Then, a mixed crystal layer (Si—Ge layer) 2 of silicon and germanium is formed on the semiconductor substrate 10.
1 is formed, and an N-type silicon layer 22 is formed continuously on this upper surface. This Si-Ge layer 21 becomes a semiconductor film described in the claims. These layers are formed by ultrahigh vacuum CVD or molecular beam epitaxy. Thereafter, a silicon nitride film 23 is formed on the silicon layer 22 to a thickness of 50 to 60 nm by a low pressure CVD method.
The film is formed with a film thickness of about.

Next, as shown in FIG. 1D, a resist pattern 24 is formed on the silicon nitride film 23 in a portion where the emitter region of the bipolar transistor is formed. Then, by etching using the resist pattern 24 as a mask, the silicon nitride film 23 and the silicon layer 22 are etched to form an N-type emitter region 22a made of the silicon layer 22. At this time, the Si-Ge layer 21 is also reduced in film thickness due to the over-etching of the silicon layer 22.

Next, after the resist pattern 24 is removed, as shown in FIG. 1 (5), the Si-Ge layer 21 is patterned, and the base formed of the Si-Ge layer 21 is formed in the bipolar transistor forming portion A. A region 21 a is formed, a resistor 21 b made of the Si—Ge layer 21 is formed in the resistance element forming portion B on the element isolation region 18, and the Si element is formed in the capacitance element forming portion C on the element separation region 18.
-A lower electrode 21c made of the Ge layer 21 is formed.

Thereafter, the bipolar transistor forming portion A
The side wall 25 made of silicon oxide is formed on the side wall of the upper emitter region 22a and the silicon nitride film 23 on the upper surface thereof.
To form

Next, as shown in FIG. 2 (6), the resist pattern 2 covering at least the collector extraction region 19 is formed.
Then, a P-type impurity is introduced into the Si-Ge layer 21 by ion implantation using the resist pattern 26, the silicon nitride film 23, and the sidewalls 25 as a mask. At this time, for example, boron ions or boron difluoride ions are introduced at about 5 × 10 ^{14 to} 5 × 10 ¹⁵ / cm ² .

At this time, the silicon nitride film 23 serves as a mask, and no P-type impurity is introduced into the N-type emitter region 22a. A base region 21a at the side lower portion of the emitter region 22a and the sidewall 25;
That is, a P-type impurity is selectively introduced only into a portion to be a base extraction region. Thereby, the resistance value of the resistor 21b and the lower electrode 21c composed of the Si—Ge layer 21 whose film thickness has been reduced by the over-etching of the silicon layer 22 can be reduced.

Next, the resist pattern 26 is removed, and the silicon nitride film 23 is removed by wet etching using hot phosphoric acid. Then, as shown in FIG. 2 (7), each component composed of the Si—Ge layer 21, the emitter region 22a and the side wall 2 are formed by the CVD method.
5 on the semiconductor substrate 10 so as to cover
An interlayer insulating film 27 made of silicon oxide having a film thickness of about 30 nm is formed.

Thereafter, a heat treatment is performed at a temperature of about 900 to 1000 ° C. to activate the P-type impurity introduced into the Si—Ge layer 21 in the previous step.

Next, an opening 28 reaching the lower electrode 21c is formed in the interlayer insulating film 27 by etching using a resist pattern (not shown) as a mask. The capacitance value of the capacitor is determined by the opening area of the opening 28. Next, after removing the resist pattern,
A dielectric film 29 is formed on the interlayer insulating film 27 so as to cover the inner wall of the opening 28. At this time, a silicon nitride film having a thickness of about 20 to 50 nm is formed by a low pressure CVD method, and this silicon nitride film is used as the dielectric film 29.

Next, as shown in FIG.
9 is patterned to form a capacitive element forming portion C
The dielectric film 29 is connected to the lower electrode 21c only above.
Leave. The patterning here is performed by RIE using a resist pattern (not shown) as a mask, and after the patterning, the resist pattern is removed.

Next, as shown in FIG. 2 (9), an interlayer insulating film 27 is formed using a resist pattern (not shown) as a mask.
Is etched, and the base region 2 is
Contact hole 30a reaching emitter 1a, emitter region 2
2a, the contact hole 30c reaching the collector take-out region 19, the resistor 2
Contact holes 3 individually reaching both ends of 1b
A contact hole 30f reaching 0d, 30e and the lower electrode 21c is formed.

Next, as shown in FIG. 2 (10), a wiring 31 connected to the bottom of each of the contact holes 30a to 30f and disposed on the dielectric film 29 is formed. The wiring 31 is made of titanium (Ti) and titanium nitride oxide (TiON).
Metal and titanium (Ti) sequentially laminated, and a 0.6-0.8 μm film formed on the barrier metal
It is made of aluminum having a film thickness of the order.

As described above, the heterojunction bipolar transistor 1 is placed on the surface side of the semiconductor substrate 10 made of silicon.
a and a lower electrode 21 having a resistor a and a resistor 21b
The semiconductor device 1 provided with the MIS-type capacitance element 1c having the dielectric film 29 and the dielectric film 29 is formed. The base region 21a of the bipolar transistor 1a and the resistor 21
b and the lower electrode 21 c are made of the Si—Ge layer 21.

Here, the mobility of electrons in Ge is 3
900 cm ² / Vsec, and the hole mobility is 190
0 cm ² / Vsec. On the other hand, the mobility of electrons in Si is 1350 cm ² / Vsec,
The mobility of the holes is 480 cm ² / Vsec. For this reason, the resistor 21b and the lower electrode 21c composed of the Si—Ge layer 21 composed of a mixed crystal of Si and Ge are connected to the base region 2
The resistance can be sufficiently reduced with an appropriate impurity concentration as 1a. In addition, since the lower electrode 1c is provided on the element isolation region 18, a large parasitic capacitance is not formed in the semiconductor substrate 10 below the lower electrode 1c. Therefore, it is possible to obtain the capacitive element 1c having a high Q (Quality) value, a high frequency characteristic, and a low parasitic capacitance.

Moreover, in the above-described manufacturing method, the base region 21a of the bipolar transistor 1a, the resistor 1b, and the lower electrode 1c can be formed in the same step.

(Second Embodiment) FIGS. 3 and 4 are views showing an example of a method of manufacturing a semiconductor device according to the present invention. The second embodiment of the present invention will be described below with reference to these drawings. I do.

First, the step shown in FIG.
Performed in the same manner as described with reference to FIG.
A buried collector 14 is formed in a bipolar transistor forming portion A of a silicon substrate 11. Then, FIG. 3 (2)
Are performed in the same manner as described in the first embodiment with reference to FIG. 1 (2), and the surface layer of the epitaxial layer 15, the pad oxide film 16 and the oxidation prevention film 17 on the silicon substrate 11 are formed in a predetermined pattern. Etching.

Thereafter, as shown in FIG. 3C, an element isolation region 18 is formed on the surface of the epitaxial layer 15 in the same manner as described in the first embodiment with reference to FIG. 1C.
Thus, the semiconductor substrate 10 including the silicon substrate 11 and the epitaxial layer 15 on the upper surface and having the element isolation region 18 provided on the surface layer of the epitaxial layer 15 is formed. Next, on the front side of the semiconductor substrate 10, the first
The collector extraction region 19 and the separation diffusion layer 20 are formed in the same manner as in the embodiment.

The following steps are different from those in the first embodiment and the second embodiment. That is,
In the present embodiment, a polysilicon film 41 having a thickness of about 100 to 200 nm is formed on the semiconductor substrate 10 by a CVD method. Next, a P-type impurity is introduced into the polysilicon film 41 by ion implantation. here,
As a P-type impurity, boron ions or boron difluoride ions are introduced in an amount of about 5 × 10 ^{14 to} 5 × 10 ¹⁵ / cm ² .

Thereafter, as shown in FIG. 3D, the polysilicon film 41 is patterned. Here, the polysilicon film 41 is removed by etching while leaving the polysilicon film 41 on the element isolation region 18.

Next, the Si—Ge layer 21 and the silicon layer 2 are formed on the semiconductor substrate 10 so as to cover the polysilicon film 41.
2 and a silicon nitride film 23 are formed. These layers are formed in the same manner as described in the first embodiment with reference to FIG.

Thereafter, in the step shown in FIG. 3 (5), the silicon nitride film 23 and the silicon layer 22 are etched in the same manner as described in the first embodiment with reference to FIG. N type emitter region 2 comprising 22
2a is formed. At this time, the Si-Ge layer 21 is also reduced in film thickness due to the over-etching of the silicon layer 22.

Next, as shown in FIG. 4 (6), the Si—Ge layer 21 and the polysilicon film 41 are patterned by etching using a resist pattern (not shown) as a mask. As a result, a base region 21a composed of the Si-Ge layer 21 and a base extraction region 41a composed of the Si-Ge layer 21 and the polysilicon film 41 are formed in the bipolar transistor forming portion A. Further, the Si-Ge is formed in the resistance element forming portion B on the element isolation region 18.
A resistive element 41b composed of the layer 21 and the polysilicon film 41 is formed, and the capacitive element forming portion C on the element isolation region 18 is formed.
Then, a lower electrode 41c composed of the Si-Ge layer 21 and the polysilicon film 41 is formed.

Thereafter, the steps shown in FIGS. 4 (7) to 4 (11) correspond to FIGS. 2 (6) to 2 (1) in the first embodiment.
0) is performed in the same manner as described above. Thus, as shown in FIG. 4 (11), a semiconductor device 4 in which the heterojunction bipolar transistor 4a, the resistor 4b, and the capacitor 4c are formed on the same semiconductor substrate 10 as the front surface is completed.

In the semiconductor device 4, the base region 21 a of the bipolar transistor 4 a is made of the Si—Ge layer 21. Further, the base extraction region 41a of the bipolar transistor 4a and the resistor 41b of the resistance element 4b
And the lower electrode 41c of the capacitive element 4c is the Si—Ge layer 2
1 and a polysilicon film 41 thereunder.

The base take-out area 41a, the resistor 4
As described in the first embodiment, the lower electrode 1b and the lower electrode 41c have a two-layer structure of the Si-Ge layer 21 having high carrier mobility and the polysilicon film 41 provided on the lower surface thereof. Therefore, the resistance value can be further reduced as compared with the resistor (21b) and the (lower electrode 21c) of the first embodiment.

Further, as in the first embodiment, since the lower electrode 41c of the capacitor 4c is provided on the element isolation region 18, the semiconductor substrate 1 under the lower electrode 41c is formed.
No large parasitic capacitance is formed during zero. Therefore, it is possible to obtain the capacitive element 4c having a high Q (Quality) value, high frequency characteristics, and low parasitic capacitance.

Moreover, in the above-described manufacturing method, the base region 21a and the base extraction region 41a of the bipolar transistor 4a, the resistor 41b and the lower electrode 41c can be formed in the same step.

[0055]

As described above, according to the semiconductor device of the present invention, the lower electrode of the capacitor, the base region and the base extraction region of the hetero-junction bipolar transistor, and the resistor of the resistor are formed of silicon such as Si-Ge. With a semiconductor film having a higher carrier mobility than that of the semiconductor film or a two-layer structure of the semiconductor film and the polysilicon film, the lower electrode and the resistor can have low resistance. Further, since the lower electrode is disposed on the element isolation region, the capacitance element has low parasitic capacitance. Therefore, it is possible to obtain a capacitor having a high Q value, good frequency characteristics, and small parasitic capacitance.

In the method of manufacturing a semiconductor device according to the present invention, the lower electrode of the capacitor, the base region and the base extraction region of the heterojunction bipolar transistor, and the resistor of the resistor are formed by patterning the same semiconductor film. By doing so, a part of the manufacturing process of the capacitor having the low-resistance lower electrode can be used also as a part of the manufacturing process of the bipolar transistor, and the manufacturing process of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a view for explaining a first embodiment of the present invention (part 1);
It is.

FIG. 2 is a view for explaining a first embodiment of the present invention (part 2);
It is.

FIG. 3 is a view for explaining a second embodiment of the present invention (part 1);
It is.

FIG. 4 illustrates a second embodiment of the present invention (part 2).
It is.

[Explanation of symbols]

1,4 Semiconductor device 1a, 4a Bipolar transistor 1c, 4c Capacitance element 10 Semiconductor substrate 18
Element isolation region 21 Si-Ge layer (semiconductor film) 21a Base region 21b, 41b Resistor 21c, 41c Lower electrode 41 Polysilicon film 41a Base extraction region A Bipolar transistor forming portion

Claims (14)

[Claims] 1. A semiconductor device in which a capacitor is provided on an element isolation region on a surface side of a semiconductor substrate made of silicon, wherein a lower electrode of the capacitor is made of a semiconductor film having higher carrier mobility than silicon. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein said semiconductor film is made of silicon containing germanium. 3. A semiconductor device in which a heterojunction bipolar transistor is provided on a surface side of a semiconductor substrate made of silicon, and a capacitor is provided on an element isolation region on a surface side of the semiconductor substrate, wherein the capacitor is provided on the semiconductor substrate. A semiconductor device, wherein a base region of the bipolar transistor and a lower electrode of the capacitor are formed of a semiconductor film having higher carrier mobility than silicon. 4. The semiconductor device according to claim 1, wherein:
The semiconductor device according to claim 3, wherein a resistor made of the semiconductor film is provided. 5. The semiconductor device according to claim 3, wherein said semiconductor film is made of silicon containing germanium. 6. A semiconductor device in which a capacitive element is provided on an element isolation region on a surface side of a semiconductor substrate made of silicon, wherein a lower electrode of the capacitive element has a carrier mobility higher than that of a lower polysilicon film and silicon. A semiconductor device having a two-layer structure including a high upper semiconductor film. 7. The semiconductor device according to claim 6, wherein said semiconductor film is made of silicon containing germanium. 8. A semiconductor device in which a heterojunction bipolar transistor is provided on a surface side of a semiconductor substrate made of silicon, and a capacitor is provided on an element isolation region on the surface side of the semiconductor substrate, wherein the semiconductor device is provided on the semiconductor substrate. The base region of the bipolar transistor is made of a semiconductor film having a higher carrier mobility than silicon. The base extraction region of the bipolar transistor and the lower electrode of the capacitor are formed of the semiconductor film and a polysilicon film thereunder. A semiconductor device having a layer structure. 9. The semiconductor device according to claim 1, wherein:
9. The semiconductor device according to claim 8, wherein a resistor having a two-layer structure of the semiconductor film and a polysilicon film thereunder is provided. 10. The semiconductor device according to claim 8, wherein said semiconductor film is made of silicon containing germanium. 11. A method for manufacturing a semiconductor device, comprising: providing a heterojunction bipolar transistor on a surface side of a semiconductor substrate made of silicon; and providing a capacitor on an element isolation region on the surface side of the semiconductor substrate. Forming a semiconductor film having a higher carrier mobility than silicon on the semiconductor substrate provided with the region; and patterning the semiconductor film to form a semiconductor film on an exposed surface of an active region in the semiconductor substrate. Forming a base region of a bipolar transistor comprising: and forming a lower electrode of the capacitive element on the element isolation region. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the base region and the lower electrode includes:
A method of manufacturing a semiconductor device, comprising forming a resistor made of the semiconductor film on the element isolation region by patterning the semiconductor film. 13. A method for manufacturing a semiconductor device, comprising: providing a heterojunction bipolar transistor on a surface side of a semiconductor substrate made of silicon; and providing a capacitive element on an element isolation region on the surface side of the semiconductor substrate. Forming a polysilicon film on the semiconductor substrate provided with the region, and providing an opening in the polysilicon film to reach an exposed surface of the active region in the semiconductor substrate; and covering the inner wall of the opening. Forming a semiconductor film having a higher carrier mobility than silicon on the polysilicon film, and patterning the semiconductor film and the polysilicon film to form a semiconductor film on the exposed surface of the active region. Forming a base region including the semiconductor film and the polysilicon film on the element isolation region. Forming a lower region and a lower electrode of the capacitive element. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the step of forming the base region and the lower electrode includes:
A method of manufacturing a semiconductor device, comprising: forming a resistor made of the semiconductor film and the polysilicon film on the element isolation region by patterning the semiconductor film and the polysilicon film.