JPS63248147A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce parasitic capacitance, and to improve the degree of integration easily by forming a wiring layer onto a trench filled with an insulator. CONSTITUTION:An N<+> buried layer 11 and an N epitaxial layer 12 are superposed onto a P-type Si substrate 10, and a trench 1 reaching the substrate 10 is shaped together with isolation trenches 3 through RIE, and filled with SiO2, Si3N4, etc. The trench 1 is formed where coincident with the pattern of an Al wiring layer 2. According to the constitution, element forming regions 4 are not narrowed due to bird beaks because a selective oxidation method is not used, thus reducing parasitic capacitance, then easily improving the degree of integration.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor device in which required wiring layers are formed;
In particular, the semiconductor device is characterized by its wiring technology.

80 Summary of the Invention The present invention provides a semiconductor device in which a required wiring layer is formed, in which a trench filled with an insulating material is provided from the surface of a semiconductor substrate, and at least a portion of the wiring layer is filled with the trench filled with an insulating material. By forming the capacitance on the top of the capacitor, it is possible to reduce the wiring capacitance.

C1 Prior Art Wiring for electrical connection between elements in a semiconductor device such as a bipolar LSI has conventionally been performed using a technique as shown in FIG.

Here, an example of this conventional semiconductor device will be briefly described with reference to FIG. 4. First, a semiconductor substrate 1
On the surface of 01 is i! Field oxide film (
A LOGO3 film) 102 is formed. A trench is dug adjacent to this field oxide film 102 by RIE method or the like, and the trench is filled with silicon oxide or the like to form a trench isolation section 103. This trench isolation section 103 is formed for the purpose of increasing the speed and integration of the device, reducing parasitic capacitance, etc.
Surrounded by this trench isolation portion 103, an element formation region 104 is formed in which an emitter, a heath, a collector region (not shown), etc. are provided. Further, on the field oxide film 102, a field wiring N105 is formed for connecting to, for example, an emitter region.

D1 Problems to be Solved by the Invention As shown in FIG.
By forming the wiring layer 105, the wiring capacitance can be made smaller than if the Aff wiring layer were directly formed on the substrate.

However, if the scaling down progresses in accordance with the recent trend of miniaturization, the wiring capacitance becomes a problem even when the A1 wiring layer 105 is formed on the field oxide film 102.

That is, when the degree of integration of a semiconductor device is improved, the line width of the wiring layer becomes narrower, and the length l of the wiring becomes longer due to the necessity of routing the wiring. Generally, it is known that the amount of delay τ in the operation caused by wiring is proportional to the square of its length l, and also proportional to the values of the wiring layer 1c and the resistance R. When the line width becomes thinner, the value of the resistance R increases, and the value of the length l increases due to the routing of the wiring, it becomes necessary to decrease the value of the capacitance C in order to decrease the delay amount τ. It turns out. However, the field oxide film 102 as described above becomes thinner due to scaling down, making it increasingly difficult to sufficiently reduce parasitic capacitance.

Furthermore, the field oxide film 102 formed by the selective oxidation method has a bird's beak 1 as shown in FIG.
The area of the field oxide film 102 expands as the area of the field oxide film 102 develops. Therefore, the area for forming elements is narrowed, which is disadvantageous for high integration.

Furthermore, when forming a field oxide film by selective oxidation, -C requires high-temperature oxidation treatment, which is also disadvantageous for high integration. In addition, in forming the trench isolation portion 103, it is desired that the process be performed using surface heat. Therefore, in view of the above-mentioned problems, the present invention aims to reduce wiring capacitance, etc., and facilitates high integration. The purpose is to provide a semiconductor device that can be used for various purposes.

Means for Solving the Problems The present invention provides a method in which a trench filled with an insulating material is formed from the surface of a semiconductor substrate, and at least a part of the wiring layer is formed on the top of the trench filled with the insulating material. The above-mentioned problems are solved by a semiconductor device having characteristics.

Here, the groove on which at least a part of the wiring layer is formed is formed by filling it with an insulator, but a structure in which another element isolation groove is arranged between the element forming region and the element forming area is used. can do.

F0 Effect Conventionally, a wiring layer was formed on an element isolation region made of a field oxide film, but in the present invention, a wiring layer is formed above a trench filled with an insulator. Therefore, the thickness of the insulator directly under the wiring layer becomes sufficiently thick, and the value of parasitic capacitance is reduced. Further, problems such as bird's beak and high temperature heat treatment can be effectively solved.

G. Example Preferred embodiments of the present invention will be described with reference to the drawings.

First, the structure of the semiconductor device of the embodiment will be explained with reference to FIG.

In the semiconductor device of this embodiment, as shown in FIG. 1, an N0 type buried layer 11 is laminated on a P type silicon substrate 10, and an N type epitaxially grown layers 12 are stacked. In the semiconductor device of this embodiment, grooves are particularly formed from the surface of the substrate having such a laminated structure. That is,
As shown in FIG. 1, a wiring layer lower trench 1 and an element isolation trench 3 are formed as trenches filled with a silicon oxide layer, which is an insulator. An An wiring layer 2 whose wiring capacitance is reduced is provided in a patterned manner above the wiring layer lower groove l.

The wiring layer lower groove l is a groove filled with an insulator to reduce the wiring capacitance of the A1 wiring N2, and is etched from the surface by anisotropic etching such as RYE (reactive ion etching) method. It is formed to a depth that reaches the P-type silicon substrate 10. This depth is, for example, 4 to 7
The depth can be on the order of μm. The insulator to be filled is, for example, silicon oxide, but silicon nitride, a 5OG (spin-on glass) layer, or other insulating layers may also be used, and materials with a low dielectric constant are used to reduce parasitic capacitance. It is effective in reducing This wiring layer lower part a1 is an Al wiring layer 2
The wiring capacitance can be reduced by forming the lower part of the wiring layer l#1 at a position that matches the pattern of the Ax wiring layer 2, as described later. . This wiring layer lower trench 1 can be formed together with the element isolation trench 3, and can be formed easily in terms of process. Furthermore, the element isolation a3 may be formed to extend. Further, as will be described later, since the conventional selective oxidation method is not used, the element formation region 4 is not narrowed by bird's beaks, and the dimensions of the field portion indicated by A in the figure can be reduced. Additionally, the trenches filled with insulators are formed at low temperatures, which solves the problem of high-temperature heat treatment.

The Aff wiring layer 2 is a wiring layer for electrically connecting terminals such as an emitter, a heath, and a collector in a bipolar transistor.

In this embodiment, the An interconnect N,'A layer 2 is formed particularly above the wiring layer lower groove 1, and its wiring capacitance is low, resulting in faster operation and higher integration. This will contribute to In addition, in this embodiment, the wiring layer is A1 wiring 2
However, the material is not limited to this, and other metal materials, polysilicon, oxide, polycide, and other materials may be used. Alternatively, the Al wiring layer 2 may be formed via an interlayer insulating layer.

The width of the pattern of this Al wiring layer 2 is preferably smaller than the width of the wiring layer - lower part/A I, but it is also possible to reduce the parasitic capacitance even if the width is the same or larger. .

Further, the element isolation groove 3 is formed so as to surround an element formation region 4 in which regions such as an emitter region and a base region are formed, and the wiring layer lower groove 1 is formed in an area other than the element formation region 4. It is arranged to be sandwiched between or extended between the element isolation/jI3. This element isolation trench 3 is formed to electrically isolate each element in the element forming region 4, and can be formed simultaneously with the wiring layer lower trench 1, as will be described later.

In the semiconductor device of this embodiment having such a structure, first, since the wiring layer lower groove l is formed under the Al wiring layer 2, the wiring capacitance of the A1 wiring layer 2 can be reduced. can. Therefore, the delay amount τ of the Al wiring layer 2 can be reduced, the semiconductor device can operate at high speed, and high integration can be realized.

Furthermore, as will be described later, the semiconductor device of this example does not form a field oxide film by selective oxidation.
The element formation area does not become smaller due to the bird's beak. That is, the parasitic capacitance of the wiring layer is sufficiently reduced by the wiring layer lower part/IS1, and a groove is formed approximately in the depth direction by anisotropic etching, and the dimension IF of the field portion is small. Become. Therefore, the area occupied by the element formation region can be expanded, and the semiconductor device can be highly integrated. Further, high temperature processing is not performed.

Further, the semiconductor device of this example has the above-mentioned wiring layer lower trench 1.
and the element isolation trench 3 can be formed in the same process,
Part of the element isolation groove 3 is placed! This can be the A-layer lower groove l. This makes the process easy and
Bad effects such as mask displacement can be prevented.

Next, an example of a layout for a bipolar transistor element will be described with reference to FIG.

As shown in FIG. 2, a pair of bipolar transistors are formed on a half-quad substrate 21, each having collector terminals 22, 22, emitter terminals 23, 23, and heath terminals 24, 24.

And emitter terminal 23.23 and collector terminal 2
2. Element A1 filled with insulator to surround 22 (
i! ! 25.25 are formed, and A1 wiring layers 26.26 are patterned to connect to the emitter terminals 23.23 and collector terminals 22.22, respectively.

Here, this patterned A7! Wiring layer 26.2
6 is a substantially T-shaped pattern and is commonly used for each terminal of a pair of emitters or collectors,
In particular, wiring layer lower grooves 20, 20 are formed in the lower part thereof, extending the element isolation grooves 25, 25 along the pattern of the AI wiring layer 26, 26. Therefore, as described above, it is possible to reduce the wiring capacitance, and it is possible to realize faster operation. Furthermore, in the semiconductor device of this embodiment, the pattern of the element isolation grooves 25 and 25 used for isolation between elements is changed, and A1
Place i! in the area where the wiring layers 26 and 26 will be formed! For the element, iiiI groove 25,
25 is extended. Then, the wiring layer lower groove 20
．． Since the trenches 20 and 25 are formed at the same time as the isolation trenches 25 and 25, and no separate process is required, loss of area due to mask shift can be prevented. Further, there is no bird's beak, and a large area of the element formation region can be secured.

Next, in order to more clearly explain the semiconductor device of this embodiment, a manufacturing method thereof will be described with reference to FIGS. 3a to 3e.

(al First, as shown in FIG. 3a, an N-type buried layer 32 and an N-type epitaxial growth layer 33 are laminated on a P-type Noricon substrate 31, and element isolation grooves are formed by, for example, RIE method.) 34 and wiring layer lower groove 3
5 are simultaneously formed using the same mask. This element u
The region surrounded by /R34 functions as a region for forming elements such as transistors. In addition, “1 wiring layer lower groove 35
An A1 wiring layer is formed by patterning, and its wiring capacitance is reduced. The depth of these element isolation grooves 34 and wiring layer lower groove 35 reaches as far as the P-type silicon substrate 31, and can be, for example, about 4 to 7 μm.

fbl Next, element isolation? 334 and the bottom of the wiring layer lower groove 35, a P-type impurity region 36 is formed.
Furthermore, as shown in Figure 3, the above element isolation? ;! i3
4 and the wiring layer lower trench 35 are filled with silicon oxide as an insulator. Filling with silicon oxide can be performed, for example, by using so-called TEO3 decomposition, and by this TEO3 decomposition, even narrow grooves are sufficiently filled with silicon oxide. FIG. 3 shows a silicon oxide layer 37 formed over the entire surface.

The insulating material filling the element isolation trench 34 and the wiring layer lower trench 35 may be silicon nitride or a colored material such as SOG. In addition, the lower the dielectric constant, the lower the parasitic capacitance. Alternatively, it may be filled with a combination of polycrystalline silicon layers.

tc+ After forming the silicon oxide layer 37, the entire surface is etched back as shown in FIG. 3C. The pattern of the wiring layer lower groove 35 exposed to the surface by this etchback follows the pattern of the A1 wiring layer to be formed later.

fd) Next, approximately 40
A thin field region 38 of 00 Å or less is formed, and in the region surrounded by the element isolation a34, elements such as transistors, resistors, diodes, etc. are formed (not shown).

Then, as shown in FIG. 3d, the field area 3
The upper part of the element formation region No. 8 is opened to form a contact hole 3.
9 is formed, and an A1 layer 40 serving as an AN wiring is formed on the entire surface.

(lft) After the formation of the A7! layer!0, the A1 layer 40 is patterned to form an Al wiring layer 41, as shown in FIG. 3e.This AA wiring layer 4117
)-411 is connected to the element formation region through the contact hole 39, but the Ai wiring layer 41 is also provided on the wiring layer lower groove 35, and in this way, the A1 wiring layer 41
is formed above the wiring layer lower groove 35, so that
The wiring capacitance of the lA1 wiring layer 41 is reduced, and the delay amount τ becomes sufficiently small.

It is possible to manufacture the semiconductor device of this example through the steps described above, but first, AI! The wiring layer lower groove 35 for reducing the wiring capacitance of the wiring layer 41 is formed at the same time as the element isolation groove 34 used for isolation between elements, and has excellent process consistency, and is formed separately. The complexity of the case can be avoided. Furthermore, there is no problem with mask misalignment between the wiring layer lower trench 35 and the element isolation trench 34, and there is no need to provide a margin in terms of area.

Further, as described above, in the semiconductor device of this embodiment, a field oxide film is not formed by selective oxidation, and isolation between elements is mainly performed by the element isolation groove 34. This reduces the number of steps in which semiconductor substrates are processed at high temperatures.
It is advantageous in terms of processing because it can be processed at low temperatures. Furthermore, no bird's beak is formed, and the field area is reduced, which is advantageous for higher integration of devices.

In addition, in the above-mentioned embodiment, although the bipolar transistor was explained, it is not limited to this, and CMO3
It goes without saying that the present invention can also be applied to semiconductor devices having devices such as transistors (or MOS) transistors. Furthermore, in addition to transistors, various elements such as resistors, capacitors, and diodes can be formed in the element formation region.

1 (0 Effects of the Invention) As described above, in the semiconductor device of the present invention, since the groove filled with an insulator is formed in the lower part of the wiring layer, the wiring capacitance can be reduced, and the semiconductor device can be operated at high speed. It is possible to achieve higher integration and higher integration.

In addition, it can be manufactured without problems with bird's beaks or high-temperature processing, especially when the groove filled with an insulator is formed at the same time as the groove for element isolation at the bottom of the wiring layer.
This means that it can be formed without any difficulty in the process.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view for explaining the structure of an example of the semiconductor device of the present invention, FIG. 2 is a schematic plan view showing a part of the layout on a plane of another example of the semiconductor device of the present invention, 3
Figures a to 3e are schematic cross-sectional views for explaining the manufacturing method of the semiconductor device according to the present invention step by step. Further, FIG. 4 is a schematic cross-sectional view of an example of a conventional semiconductor device. l... Wiring layer lower groove 2..., l Wiring layer 3... Element isolation groove 4... Element formation area Patent Applicant: Sony Corporation Representative Patent attorney: Koike Mimi Fl] Murakae - Figure 1 Figure 2 Figure 3 a Figure 3 Figure 3 C Figure 3 d Figure 3 e Figure 4

Claims (1)

[Claims] A trench filled with an insulator is formed from the surface of the semiconductor substrate,
A semiconductor device characterized in that at least a part of the wiring layer is formed above the trench filled with an insulator.