JPH08321510A - Bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE: To enhance operation characteristics by reducing a cell area and decreasing parasitic capacitance between the base and collector by forming with insulation films having the smallest thickness possible for insulating separation between a collector electrode, a base electrode and an emitter electrode. CONSTITUTION: A collector layer 14 on a semiconductor substrate 10; a base layer 15 on part of an upper layer of the collector layer 14; and an emitter layer 18 are formed on part of an upper layer of the base layer 15 respectively in this order; a collector electrode 23 to be connected to the collector layer 14 through a first insulating film 21 on the semiconductor substrate 10; its one end is arranged on the boundary between the base layer 15 and the collector layer 14 on the surface of the semiconductor substrate 10, and a second insulation film 29 is formed in a state of covering the collector electrode 23. Then, on said film, a base electrode 31 to be connected to the base layer 15 is formed, its one end is arranged on the boundary between the emitter layer 18 and the base layer 15 on the surface of semiconductor substrate 10, a third insulating film 33 is formed in a state of covering the base electrode 31, and an emitter electrode 34 to be connected to the emitter layer 18 is formed on the third insulating film 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and a manufacturing method thereof, and more particularly to a bipolar transistor formed in a self-aligned manner and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional bipolar transistor having a so-called double polysilicon structure will be described with reference to the manufacturing process chart of FIG.

As shown in FIG. 6A, after an N ⁺ type buried diffusion layer 62 is formed on a P type silicon substrate 61, an N type epitaxial layer 63 is formed on the silicon substrate 61. To do. Further, a LOCOS oxide film 64 for element isolation is formed on the surface side of the epitaxial layer 63. The LOCOS oxide film 64 is formed in a state in which the base layer formation planned region and the collector extraction layer formation planned region are opened.

Then, the buried diffusion layer 62 is formed in a region of the epitaxial layer 63 where a collector extraction layer is to be formed.
An N ⁺ -type collector take-out layer 65 connected to is formed. Then, after forming the first interlayer insulating film 66, the opening 6 is formed in the first interlayer insulating film 66 on the region where the base layer is to be formed.
Form 7.

Then, as shown in FIG. 6B, a base electrode forming layer 68 and a second interlayer insulating film 69 are laminated and formed. The base electrode forming layer 68 is formed in a state where P-type impurities are doped. Alternatively, after forming a film, a P-type impurity is doped by an ion implantation method. Then, from the second interlayer insulating film 69 to the epitaxial layer 63.
After forming the opening 70 communicating with the P type base layer 71, the upper layer of the epitaxial layer 63 is doped with P type impurities through the opening 70.

Next, as shown in FIG. 6C, after forming a sidewall insulating film 72 on the sidewall of the opening 70, the base electrode forming layer 68 is patterned together with the second interlayer insulating film 69. Lever base electrode forming layer (6
In 8), the base electrode 73 is formed. Subsequently, after forming an emitter electrode forming layer in a state of being connected to the base layer 71, the emitter electrode forming layer is patterned to form an emitter electrode 74. The emitter electrode forming layer is formed with N-type impurities being doped. Alternatively, N-type impurities may be doped after the film formation.

Thereafter, as shown in FIG. 6 (4), a third interlayer insulating film 75 is formed. Further, heat treatment is performed to remove P-type impurities from the base electrode 73 into the epitaxial layer 63.
To form a graft base layer 76 connected to the base layer 71. At the same time, N-type impurities are diffused from the emitter electrode 74 to the upper layer of the base layer 71 to form the emitter layer 77. The base electrode 73 and the emitter electrode 7 are formed on the first, second and third interlayer insulating films 66, 69 and 75.
4. After opening the contact holes leading to the collector take-out layer 65, plugs 81, 8 are formed in the respective contact holes.
2, 83 are formed, and electrodes 84, 85, 86 connected to the respective plugs 81 to 83 are formed. In this way, the bipolar transistor 60 is formed.

[0008]

However, in the above bipolar transistor, the LOCOS for element isolation is used.
The base layer and the collector extraction layer are separated by the oxide film. Therefore, the cell area of the bipolar transistor becomes large. Further, since the distance between the base layer and the collector layer is wide, the parasitic capacitance formed between them becomes large, so that the operating speed is particularly slow as a bipolar transistor characteristic.

An object of the present invention is to provide a bipolar transistor in which the cell area is reduced and the parasitic capacitance between the base and the collector is reduced, and a manufacturing method thereof.

[0010]

SUMMARY OF THE INVENTION The present invention is a bipolar transistor and a method for manufacturing the same made to achieve the above object. That is, the collector layer formed on the semiconductor substrate, the base layer formed on a part of the upper layer of the collector layer, and the emitter layer formed on a part of the upper layer of the base layer are provided. A first insulating film having an opening is formed on the semiconductor substrate.
A collector electrode connected to the collector layer is formed on the first insulating film, and one end is arranged at a boundary between the collector layer and the base layer on the surface of the semiconductor substrate and a second insulating film is formed so as to cover the collector electrode. Has been done. This second
A base electrode connected to the base layer is formed on the insulating film, one end is arranged at a boundary between the base layer and the emitter layer on the surface of the semiconductor substrate, and a third insulating film is formed so as to cover the base electrode. . Further, an emitter electrode connected to the emitter layer is formed on the third insulating film.

In the method of manufacturing a bipolar transistor, a collector layer is formed on a semiconductor substrate in a first step, a first insulating film is formed on a semiconductor substrate in a second step, and a first insulating film on the collector layer is first formed. Form an opening. In the third step, a collector electrode forming layer is formed on the first insulating film in a state of being connected to the collector layer, and then the collector electrode forming layer is patterned to form a collector electrode. In the fourth step, the first interlayer insulating film and the base electrode forming layer are laminated and formed so as to cover the collector electrode, and then the base electrode forming layer is patterned to form the upper base electrode. In the fifth step, after forming the second interlayer insulating film so as to cover the upper base electrode, a second opening portion is formed from the second interlayer insulating film to the collector layer,
Then, a first electrode is formed on each side wall of the collector electrode and the first interlayer insulating film.
A sidewall insulating film is provided, and the first interlayer insulating film and the first sidewall insulating film form a second insulating film. In a sixth step, a base layer is formed on the upper side of the semiconductor substrate inside the first sidewall insulating film, and then a side base electrode is formed to connect to the side of the base layer and the patterned upper base electrode. In a seventh step, a second sidewall insulating film connected to the second interlayer insulating film is formed so as to cover the side base electrode. In the eighth step, an emitter electrode is formed on the side of the third insulating film so as to be connected to a portion on the base layer, and then an emitter layer is formed on a portion of the upper layer of the base layer by impurity diffusion from the emitter electrode. A method of manufacturing a transistor.

[0012]

In the bipolar transistor having the above structure, the base layer is formed on a part of the upper layer of the collector layer formed on the semiconductor substrate, and the emitter layer is formed on a part of the upper layer of the base layer, and is connected to the collector layer. The collector electrode and the base electrode connected to the base layer are separated by a second insulating film having one end located at the boundary between the collector layer and the base layer on the surface of the semiconductor substrate, and the emitter connected to the base electrode and the emitter layer. Since the electrodes are separated by the third insulating film whose one end is arranged at the boundary between the base layer and the emitter layer on the surface of the semiconductor substrate, the planes of the second and third insulating films separating the electrodes on the surface of the semiconductor substrate. The visual occupancy area is reduced. Therefore, the cell area of the bipolar transistor is reduced. Moreover, since the distance between the base electrode and the collector electrode is narrowed, the parasitic capacitance formed between the base and the collector is reduced.

In the method of manufacturing a bipolar transistor having the above structure, the collector electrode, the first interlayer insulating film, the upper base electrode and the second interlayer insulating film are formed so as to be laminated, and the second interlayer insulating film is connected to the collector layer. After the second opening is formed, a first sidewall insulating film that covers the collector electrode on the side wall of the second opening, a side base electrode that connects the base layer and the upper base electrode, a side base electrode that covers the side base electrode, and A second sidewall insulating film connected to the second interlayer insulating film,
A second emitter electrode connected to a part of the upper layer of the base layer
Since the openings are sequentially formed from the side wall side in a so-called self-aligned manner, the area occupied by the isolation region on the surface of the semiconductor substrate in plan view is reduced. Therefore, the cell area of the bipolar transistor is reduced. Further, since the first side wall insulating film separates the side base electrode and the collector electrode, the distance between them becomes narrow. Therefore, the parasitic capacitance formed between the base and the collector is reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the bipolar transistor of the present invention will be described with reference to the schematic sectional view of FIG. In the figure, an NPN vertical bipolar transistor is shown as an example.

As shown in FIG. 1, the bipolar transistor 1 has the following structure. That is, an N ⁺ type implantation diffusion layer 12 [for example, antimony (Sb ⁺ ) diffusion] is formed on the P type silicon substrate 11. An N type epitaxial layer 13 is formed on the silicon substrate 11.
(For example, an N-type silicon layer having a sheet resistance of 1Ω / □ and a thickness of 1 μm) is formed. The semiconductor substrate 10 is configured in this way.

Epitaxial layer 1 of the semiconductor substrate 10
3, the first insulating film 21 for separating the element formation regions is L
It is formed of an OCOS (Local Oxidation of Silicon) oxide film. Then, the first opening 22 of the first insulating film 21 is formed on the element forming region. The epitaxial layer 13 below the first opening 22 becomes the collector layer 14.

A base layer 15 is formed on a part of the upper layer of the collector layer 14. The base layer 15 is P
The mold intrinsic base layer 16 and the P ⁺ -type graft base layer 17 formed so as to be connected to the side of the mold intrinsic base layer 16. An N ⁺ type emitter layer 18 is formed on a part of the upper layer of the intrinsic base layer 16.

A collector electrode 23 is formed on the first insulating film 21 and is connected to the collector layer 14 via an N ⁺ -type collector extraction diffusion layer 19. The collector electrode 23 is composed of, for example, arsenic (As ⁺ ) or phosphorus (P ⁺ ) doped polycrystalline silicon.

A first interlayer insulating film 24 is formed so as to cover the collector electrode 23, and an upper base electrode 25 is formed on the first interlayer insulating film 24. Further, a second interlayer insulating film 26 is formed so as to cover the upper base electrode 25. The first interlayer insulating film 24 is made of, for example, silicon oxide having a thickness of 200 nm, and the upper base electrode 25 is made of, for example, a polycrystal silicon film having a thickness of 150 nm doped with boron difluoride (BF ₂ ⁺ ). Become. The second interlayer insulating film 26 has a thickness of 200 n, for example.
m silicon oxide.

A second opening 27 reaching the semiconductor substrate 10 is formed in the second interlayer insulating film 26, the upper base electrode 25, the first interlayer insulating film 24 and the collector electrode 23 on the base layer 16.

A first side wall insulating film 28 is formed on the side wall of the second opening 27 so as to be connected to the first interlayer insulating film 24 so as to cover the collector electrode 23 on the side wall of the second opening 27. Has been done. The first sidewall insulating film 28 is formed to have a thickness of 100 nm to 150 nm, for example. In this way, the first interlayer insulating film 24 and the first
A second insulating film 29 is formed by the sidewall insulating film 28. Therefore, the second insulating film 29 is arranged such that one end side of the first sidewall insulating film 28 is located at the boundary between the collector layer 14 and the base layer 15 on the surface of the semiconductor substrate 10.

Further, a side base electrode 30 for connecting the graft base layer 17 of the base layer 15 and the upper base electrode 25 is formed on the side of the first side wall insulating film. The side base electrode 30 has, for example, a boron difluoride (BF ₂ ⁺ )-doped thickness of 10
It is made of 0 nm polycrystalline silicon. In this way, the upper base electrode 25 and the side base electrode 30 are combined to form the base electrode 31.
Is formed.

A second sidewall insulating film 32 connected to the second interlayer insulating film 26 on the sidewall of the second opening 27 is formed in a state of covering the side base electrode 30.
The second sidewall insulating film 32 has a thickness of 3
It is made of 00 nm silicon oxide. As described above, the second interlayer insulating film 26 and the second sidewall insulating film 32 form a third layer.
The insulating film 33 is formed. Therefore, the third insulating film 33 is arranged such that one end of the second sidewall insulating film 32 is located at the boundary between the intrinsic base layer 16 and the emitter layer 18 on the surface of the semiconductor substrate 10.

Furthermore, the second sidewall insulating film 32
An emitter electrode 34 connected to the emitter layer 18 is formed on the side portion of the. The emitter electrode 34 is, for example, arsenic (As ⁺ )-doped and has a thickness of 150 nm.
Made of polycrystalline silicon. The emitter electrode 34 may be formed on the third insulating film 33 so as to be drawn out.

In the bipolar transistor 1 having the above structure, one end side of the collector electrode 23 and the side base electrode 30 is disposed inside the second opening 27 at the boundary between the collector layer 14 and the base layer 15 on the surface of the semiconductor substrate 10. The second insulating film 3 including the first sidewall insulating film 28
A third side wall insulating film 32 whose one end side is disposed at the boundary between the intrinsic base layer 16 and the emitter layer 18 on the surface of the semiconductor substrate 10 by separating the side base electrode 30 and the emitter electrode 34 with each other. Since the insulating film 33 is used for separation, the area occupied by the separation region on the surface of the semiconductor substrate 10 in plan view is reduced. Therefore, the cell area of the bipolar transistor 1 is reduced. Further, since the distance between the side base electrode 30 and the collector electrode 23 becomes narrow, the parasitic capacitance formed between the base and collector becomes small.

Next, a method of manufacturing the bipolar transistor will be described with reference to manufacturing process diagrams (No. 1), (No. 2) and (No. 3) of FIGS. In the figure, FIG.
The same reference numerals are given to the same components as those described in.

As shown in FIG. 2A, in the first step,
For example, the N ⁺ type buried layer 12 is formed on the upper layer portion of the P type silicon substrate 11 by antimony (Sb ⁺ ) diffusion. Then, in a second step, an N type epitaxial layer 13 is grown to a thickness of, for example, 1 μm on the surface of the silicon substrate 11 by an epitaxial growth method. The dose amount for the epitaxial layer 13 is 5 × 10 ¹⁵ pieces / cm ²
At that time, the sheet resistance becomes 1Ω / □. In this way, the semiconductor substrate 10 is formed. Then, a part of the epitaxial layer 13 becomes the collector layer 14.

Then, a first insulating film 21 for separating the element formation regions is formed by a LOCOS oxide film by the LOCOS oxidation method. Then, the element forming region becomes the first opening 22 of the first insulating film 21, and the epitaxial layer 13 below the first opening 22 becomes the collector layer 14.

Next, in the third step, chemical vapor deposition (hereinafter, referred to as
The first conductive film 41 is formed of a polycrystalline silicon film having a thickness of 100 nm, for example, by the CVD, which is an abbreviation for Chemical Vapor Deposition. After that, for example, arsenic (As ⁺ ) or phosphorus (P ⁺ ) is ion-implanted as an N-type impurity by an ion implantation method. As the ion implantation conditions, for example, when the first conductive film 41 is formed of a polycrystalline silicon film having a thickness of 100 nm, the implantation energy is 30 keV to 40 keV and the dose is 1
It is set to × 10 ¹⁶ pieces / cm ² .

Then, as shown in (2) of FIG. 2, the above-mentioned first process is performed by a lithography technique (for example, resist coating, exposure, development, baking, etc.) and etching.
The conductive film (41) is patterned to form the collector electrode 23.

Then, a fourth step shown in FIG. 2C is performed. In this step, the first interlayer insulating film 24 is deposited by the CVD method. The first interlayer insulating film 24 is made of silicon oxide having a thickness of 200 nm, for example. Subsequently, the second conductive film 42 is formed of polycrystalline silicon having a thickness of 150 nm, for example. Then, the second conductive film 42 is doped with P-type impurities by the ion implantation method. As the ion implantation conditions at this time, for example, boron difluoride (BF ₂ ⁺ ) is used as the doping material, and the implantation energy is 30 ke.
V and dose amount are set to 5 × 10 ¹⁵ pieces / cm ² .

After that, as shown in FIG. 2D, the second conductive film 42 is patterned by the lithography technique (eg resist coating, exposure, development, baking, etc.) and etching to form the upper base electrode 25. To form.

Next, the fifth step shown in FIG. 3A is performed. In this step, the second interlayer insulating film 26 is formed of, for example, 200 nm thick silicon oxide in a state of covering the upper base electrode 25 by, for example, the CVD method. Next, after forming a resist mask 43 by a lithography technique (for example, resist application, exposure, development, baking, etc.), the second opening reaching the semiconductor substrate 10 from the second interlayer insulating film 26 by etching using the resist mask 43. The part 27 is formed.

Then, the resist mask 43 is removed by, for example, ashing or wet treatment. Next, as shown in FIG. 3B, the sidewall insulating film 44 is formed of silicon oxide having a thickness of 300 nm, for example, by the CVD method. Then, by etching back the sidewall insulating film 44 (portion indicated by a chain double-dashed line), the first sidewall insulation is formed on each sidewall of the collector electrode 23 and the first interlayer insulating film 24 in the second opening 27. The film 28 is formed to have a thickness of 100 nm to 150 nm, for example. In this way, the second insulating film 29 is formed by the first interlayer insulating film insulating film 24 and the first sidewall insulating film 28.

Next, the sixth step shown in FIG. 3C is performed.
In this step, for example, boron difluoride (BF ₂ ⁺ ) is used as a P-type impurity by the ion implantation method in the semiconductor substrate 1.
The upper layer of 0 is doped to form the intrinsic base layer 16. Ion implantation conditions at this time are, for example, implantation energy of 100 keV and dose of 2 × 10 ¹³ /
set to cm ² ~5 × 10 ¹³ pieces / cm ^2.

Next, as shown in FIG. 3D, the third conductive film 45 is formed of, for example, polycrystalline silicon to a thickness of 100 nm by, for example, the CVD method. After that, for example, boron difluoride (BF ₂ ⁺ ) is ion-implanted as a P-type doping substance by an ion implantation method. The ion implantation condition at this time is, for example, implantation energy of 30.
The keV and dose amount are set to 5 × 10 ¹⁵ pieces / cm ² .
Alternatively, when boron (B ⁺ ) is used as the doping material, the implantation energy is 5 keV and the dose amount is 5 × 1.
It is set to 0 ¹⁵ pieces / cm ² .

Then, as shown in FIG. 4A, the side base electrode 30 connecting the upper base electrode 25 and the intrinsic base layer 16 is formed by etching back the third conductive film (45). . Since over-etching is performed when the above-mentioned etch back is performed, a part of the upper layer of the semiconductor substrate 10 is also etched.

Next, the seventh step shown in FIG. 4B is performed. In this step, the sidewall insulating film 46 is formed of silicon oxide having a thickness of 300 nm, for example. After that, by etching back the portion indicated by the chain double-dashed line of the side wall insulating film 46, the second side wall insulating film 32 that covers the side base electrode 30 and is connected to the second interlayer insulating film 26 is formed. Insulating film (4
It is formed in 6). In this way, the first interlayer insulating film 26 and the second sidewall insulating film 32 form a third insulating film 33.

Then, the eighth step shown in FIG. 4C is performed. In this step, the fourth conductive film 47 is formed by the CVD method.
Is formed of polycrystalline silicon having a thickness of 150 nm, for example. After that, for example, arsenic (As ⁺ ) as an N-type doping substance is ion-implanted into the fourth conductive film 47 by an ion implantation method. As the ion implantation conditions at this time, for example, implantation energy is 30 keV and dose is 1
It is set to × 10 ¹⁶ pieces / cm ² .

Thereafter, as shown in (4) of FIG. 4, the fourth conductive film (4) is formed by a lithography technique (resist coating, exposure, development, baking, etc.) and etching.
7) is patterned to form the emitter electrode 34.
Subsequently, the fourth insulating film 48 is formed of, for example, silicon oxide by the CVD method, and then heat treatment (for example, furnace annealing, 900 ° C., 30 minutes) is performed to form the emitter electrode 3.
4 forms an N ⁺ type emitter layer 18 by diffusion, and forms a P ⁺ type graft base layer 17 connected to the intrinsic base layer 16 by diffusion from the base electrode 31 (side base electrode 30). An N ⁺ type collector extraction layer 19 is formed by diffusion from the electrode 23. In this way, the bipolar transistor 1 is completed.

Further, as shown in FIG. 5, the base electrode 31 is reached by penetrating the fourth insulating film 48 and the third insulating film 33 by a lithography technique (resist coating, exposure, development, baking, etc.) and etching. Through the contact hole 51 and the fourth insulating film 48
Contact hole 52 reaching 4th, 4th, 3rd, 2nd
A contact hole 53 that penetrates the insulating films 48, 31, and 29 and reaches the collector electrode 23 is formed. After that, by the wiring forming technique, the plugs 54 to 56 are formed in the contact holes 51 to 53, and then the wirings 57 to 59 connected to the plugs 54 to 56 are formed.

The resist mask (not shown) formed by the lithography technique in the above description is, of course, removed by ashing, wet treatment or the like after etching using the resist mask. Further, the collector electrode 23, the base electrode 25, the emitter electrode 34, etc. may be formed of polycide.

In the method of manufacturing the bipolar transistor having the above structure, the collector electrode 23, the first interlayer insulating film 24, the upper base electrode 25 and the second interlayer insulating film 26 are formed,
After forming the second opening 27 from the second interlayer insulating film 26 to the collector layer 14, a first sidewall insulating film 28 covering the collector electrode 23 on the sidewall of the second opening 27,
A side base electrode 30 connecting the base layer 15 and the upper base electrode 25, a second side wall insulating film 32 covering the side base electrode 30 and connecting to the second interlayer insulating film 26,
Since the emitter electrode 34 connected to a part of the upper layer of the intrinsic base layer 16 is sequentially formed from the side wall side of the second opening 27, the plan view occupation area of the isolation region on the surface of the semiconductor substrate 10 is reduced. Therefore, the cell area of the bipolar transistor 1 is reduced. Further, since the side base electrode 30 and the collector electrode 23 are separated by the first sidewall insulating film 28, the distance between them becomes narrow. Therefore, the parasitic capacitance formed between the base and the collector is reduced.

[0044]

As described above, according to the bipolar transistor of the present invention, the base layer is partially formed on the upper layer of the collector layer, and the emitter layer is formed on the upper layer of the base layer. An emitter connected to the base electrode and the emitter layer by separating a collector electrode connected to the base layer and a base electrode connected to the base layer by a second insulating film having one end located at the boundary between the collector layer and the base layer on the surface of the semiconductor substrate. Since the electrodes are separated by the third insulating film whose one end is arranged at the boundary between the base layer and the emitter layer on the surface of the semiconductor substrate, the second and third insulating films for separating the electrodes on the surface of the semiconductor substrate are viewed in plan view. Occupied area is reduced. Therefore, the cell area of the bipolar transistor can be reduced to achieve high integration. Moreover, since the distance between the base electrode and the collector electrode can be narrowed, the parasitic capacitance formed between the base and the collector can be reduced. Therefore, the operating speed of the bipolar transistor can be improved.

In the method of manufacturing the bipolar transistor having the above structure, the collector electrode, the first interlayer insulating film, the upper base electrode and the second interlayer insulating film are formed so as to be stacked, and the second interlayer insulating film is connected to the collector layer. After the second opening is formed, a first sidewall insulating film that covers the collector electrode on the side wall of the second opening, a side base electrode that connects the base layer and the upper base electrode, a side base electrode that covers the side base electrode, and A second sidewall insulating film connected to the second interlayer insulating film,
A second emitter electrode connected to a part of the upper layer of the base layer
Since the openings are sequentially formed from the side wall side in a so-called self-aligning manner, the area occupied by each insulating film on the semiconductor substrate surface in plan view can be reduced. Therefore, the cell area of the bipolar transistor can be reduced. Also the first
By forming the sidewall insulating film in a self-aligned manner, the distance between the side base electrode and the collector electrode becomes narrow. Therefore, the parasitic capacitance formed between the base and the collector can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram (1) of the embodiment according to the manufacturing method of the present invention.

FIG. 3 is a manufacturing process diagram (2) of the example according to the manufacturing method of the present invention.

FIG. 4 is a manufacturing process diagram (3) of the embodiment according to the manufacturing method of the present invention.

FIG. 5 is an explanatory diagram of a wiring forming method.

FIG. 6 is a manufacturing process diagram of a conventional example.

[Explanation of symbols]

 1 Bipolar Transistor 10 Semiconductor Substrate 14 Collector Layer 15 Base Layer 18 Emitter Layer 21 First Insulating Film 23 Collector Electrode 29 Second Insulating Film 31 Base Electrode 33 Third Insulating Film 34 Emitter Electrode

Claims (3)

[Claims] 1. A bipolar transistor comprising a collector layer formed on a semiconductor substrate, a base layer formed on a part of an upper layer of the collector layer, and an emitter layer formed on a part of an upper layer of the base layer, wherein the collector A first insulating film formed on the semiconductor substrate by opening a layer, a collector electrode formed on the first insulating film for connecting to the collector layer, and the collector layer on the surface of the semiconductor substrate A second insulating film having one end disposed at a boundary with the base layer and covering the collector electrode; a base electrode connected to the base layer and formed on the second insulating film; A third one having one end arranged at a boundary between the base layer and the emitter layer on the surface of the semiconductor substrate and covering the base electrode. Enmaku a bipolar transistor, characterized in that it comprises an emitter electrode formed on said third insulating film in which connected to the emitter layer. 2. The bipolar transistor according to claim 1, wherein the second insulating film is formed on a first interlayer insulating film that covers the collector electrode, the second insulating film is connected to the first interlayer insulating film, and is formed on a sidewall of the collector electrode. 1 side wall insulating film, the base electrode is formed on the first interlayer insulating film, and the base is formed on a side portion of the first sidewall insulating film and connected to the upper base electrode. A side base electrode connected to a layer, and the third insulating film is formed on a second interlayer insulating film covering the upper base electrode and on the side of the side base electrode and connected to the second interlayer insulating film. And a second sidewall insulating film described above. 3. A first method for forming a collector layer on a semiconductor substrate
A second step of forming a first insulating film on the semiconductor substrate and forming a first opening in the first insulating film on the collector layer, and a second step of connecting to the collector layer. A third step of forming a collector electrode forming layer on the first insulating film and then patterning the collector electrode forming layer to form a collector electrode; and a first interlayer insulating film and a base electrode forming layer so as to cover the collector electrode. A fourth step of patterning the base electrode forming layer to form an upper base electrode, and forming a second interlayer insulating film so as to cover the upper base electrode, A second opening is formed from the interlayer insulating film to the collector layer, and then a first sidewall insulating film is provided on each side wall of the collector electrode and the first interlayer insulating film to form the first interlayer insulating film and the first interlayer insulating film. First side wall A fifth step of forming a second insulating film with the insulating film, and forming a base layer on the upper side of the semiconductor substrate inside the first side wall insulating film, and then on the side of the first side wall insulating film. A sixth step of providing a side base electrode connected to the base layer and the upper base electrode to a part to form a base electrode with the upper base electrode and the side base electrode, and a state of covering the side base electrode. A seventh step of providing a second sidewall insulating film connected to the second interlayer insulating film and forming a third insulating film by the second interlayer insulating film and the second sidewall insulating film; Forming an emitter electrode on the side of the third insulating film in a state of being connected to a part of the third insulating film, and then forming an emitter layer on a part of the upper layer of the base layer by impurity diffusion from the emitter electrode. Be prepared Method of manufacturing a bipolar transistor to be butterflies.