JPH10133960A5 - - Google Patents

Info

Publication number
JPH10133960A5
JPH10133960A5 JP1997275545A JP27554597A JPH10133960A5 JP H10133960 A5 JPH10133960 A5 JP H10133960A5 JP 1997275545 A JP1997275545 A JP 1997275545A JP 27554597 A JP27554597 A JP 27554597A JP H10133960 A5 JPH10133960 A5 JP H10133960A5
Authority
JP
Japan
Prior art keywords
memory
self
refresh mode
scanning
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997275545A
Other languages
English (en)
Japanese (ja)
Other versions
JP4083847B2 (ja
JPH10133960A (ja
Filing date
Publication date
Priority claimed from US08/720,960 external-priority patent/US5754557A/en
Application filed filed Critical
Publication of JPH10133960A publication Critical patent/JPH10133960A/ja
Publication of JPH10133960A5 publication Critical patent/JPH10133960A5/ja
Application granted granted Critical
Publication of JP4083847B2 publication Critical patent/JP4083847B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP27554597A 1996-10-10 1997-10-08 メモリ・リフレッシュ方法及びシステム Expired - Fee Related JP4083847B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/720,960 US5754557A (en) 1996-10-10 1996-10-10 Method for refreshing a memory, controlled by a memory controller in a computer system, in a self-refresh mode while scanning the memory controller
US720,960 1996-10-10

Publications (3)

Publication Number Publication Date
JPH10133960A JPH10133960A (ja) 1998-05-22
JPH10133960A5 true JPH10133960A5 (https=) 2005-06-23
JP4083847B2 JP4083847B2 (ja) 2008-04-30

Family

ID=24895954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27554597A Expired - Fee Related JP4083847B2 (ja) 1996-10-10 1997-10-08 メモリ・リフレッシュ方法及びシステム

Country Status (4)

Country Link
US (1) US5754557A (https=)
JP (1) JP4083847B2 (https=)
DE (1) DE19740223C2 (https=)
GB (1) GB2320774B (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5999481A (en) 1997-08-22 1999-12-07 Micron Technology, Inc. Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals
US6295618B1 (en) * 1998-08-25 2001-09-25 Micron Technology, Inc. Method and apparatus for data compression in memory devices
JP2001290696A (ja) * 2000-04-07 2001-10-19 Minolta Co Ltd メモリ基板
JP4689087B2 (ja) * 2000-08-22 2011-05-25 キヤノン株式会社 情報処理装置及び省電力移行制御方法
US6901359B1 (en) * 2000-09-06 2005-05-31 Quickturn Design Systems, Inc. High speed software driven emulator comprised of a plurality of emulation processors with a method to allow high speed bulk read/write operation synchronous DRAM while refreshing the memory
US7383381B1 (en) 2003-02-28 2008-06-03 Sun Microsystems, Inc. Systems and methods for configuring a storage virtualization environment
US7290168B1 (en) 2003-02-28 2007-10-30 Sun Microsystems, Inc. Systems and methods for providing a multi-path network switch system
US7236987B1 (en) 2003-02-28 2007-06-26 Sun Microsystems Inc. Systems and methods for providing a storage virtualization environment
US8166128B1 (en) 2003-02-28 2012-04-24 Oracle America, Inc. Systems and methods for dynamically updating a virtual volume in a storage virtualization environment
US7107394B2 (en) 2003-03-28 2006-09-12 Hewlett-Packard Development Company, L.P. Apparatus for capturing data on a debug bus
JP3811143B2 (ja) * 2003-07-09 2006-08-16 株式会社東芝 メモリ制御回路
JP5082727B2 (ja) * 2007-09-28 2012-11-28 ソニー株式会社 記憶制御装置、記憶制御方法およびコンピュータプログラム
US8495287B2 (en) 2010-06-24 2013-07-23 International Business Machines Corporation Clock-based debugging for embedded dynamic random access memory element in a processor core
WO2013076529A1 (en) * 2011-11-23 2013-05-30 Freescale Semiconductor, Inc. System-on-chip, method of manufacture thereof and method of controlling a system-on-chip
US11586383B2 (en) * 2018-10-16 2023-02-21 Micron Technology, Inc. Command block management
US11543996B2 (en) 2020-05-20 2023-01-03 Western Digital Technologies, Inc. Systems and methods for power management in a data storage device
US11137823B1 (en) * 2020-05-20 2021-10-05 Western Digital Technologies, Inc. Systems and methods for power management in a data storage device
CN112328305B (zh) * 2020-10-30 2022-10-18 歌尔光学科技有限公司 一种眼图测试方法、装置、电子设备及可读存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4827476A (en) * 1987-04-16 1989-05-02 Tandem Computers Incorporated Scan test apparatus for digital systems having dynamic random access memory
JPH02255925A (ja) * 1988-11-30 1990-10-16 Hitachi Ltd メモリテスト方法および装置
US5255381A (en) * 1990-07-03 1993-10-19 Digital Equipment Corporation Mode switching for a memory system with diagnostic scan
AU1524395A (en) * 1994-01-05 1995-08-01 Norand Corporation Safe-stop mode for a microprocessor operating in a pseudo-static random access memory environment
JP3260583B2 (ja) * 1995-04-04 2002-02-25 株式会社東芝 ダイナミック型半導体メモリおよびそのテスト方法

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