JPH10133855A - Coincidence detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a high speed operation without generating malfunction by judging the coincidence/non-coincidence for every input of one bit of data and successively storing judged results. SOLUTION: Comparision between the values of 1 bit up to m bits (m is integers of 1 to n) already inputted out of data 10 to be inputted and corresponding bit values in reference data is executed for every clock and respective stored results are stored in a 8-stage shift register and successively shifted to post stages synchronously with a clock 20. An output from the final stage of the shift register becomes a coincidence detection result between the input data 10 and the reference data. The shift register is constituted of D type flip flops (DFFs) N1 to N8 connecting eight stages in cascade. Plural AND gates AND2 to AND8 are inserted into intervals between respective stages and outputs from respective AND gates AND2 to AND8 are stored in succeeding DFFs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coincidence detecting circuit, and more particularly to a coincidence detecting circuit for detecting coincidence between input serial data and data in a certain bit arrangement.

[0002]

2. Description of the Related Art There is a circuit shown in FIG. 3 as a circuit for detecting whether or not input serial data is a certain bit. The circuit shown in FIG. 1 includes a shift register 1 that holds serially input data (DATA) 10 and a comparison circuit 2 that receives an output of the shift register 1 as an input.

In FIG. 1, a shift register 1 has a configuration in which D-type flip-flops (hereinafter, referred to as “DFFs”) N1 to N8 operating in synchronization with a clock (CLK) 20 are cascaded. Then, each output of the DFFN1 to N8 is input to the comparison circuit 2. In this example, the bit to be detected, that is, the reference bit is “101101”.
10 ". Therefore, the Q output of DFFN1, the inverted Q output of DFFN2, the Q output of DFFN3,
Q output of FFN4, inverted Q output of DFFN5, DFFN
6, Q output of DFFN7, inverted Q of DFFN8
The outputs are input to the comparison circuit 2 respectively.

Here, the comparison circuit 2 is composed of two stages connected in multiple stages.
It consists of an input AND gate. Therefore, in order to detect coincidence of n (n is a positive integer, the same applies hereinafter) bits, the number of AND gates in the comparison circuit 2 is:
Log ₂ (n). In this example, since eight DFFs are included, the number of AND gates in the coincidence detection circuit 2 is Log ₂ (8) = 3.

[0005] The match detection result output from the comparison circuit 2 is held in the DFFN 9 and output as a match output.

The operation of the conventional coincidence detecting circuit having such a configuration will be described with reference to a time chart of FIG. Each waveform shown in FIG. 4 is denoted by the same reference numeral as the corresponding reference numeral in FIG.
As shown in FIG. 4, signal DATA is clock C
It is held in DFFN1 at the rising timing of LK, and is sequentially sent to DFFN2 to N8 at the subsequent stage. And D1 to D
In a state where each bit of 8 is held in each of the DFFN1 to N8 (the hatched portion in FIG. 4), the output of the comparison circuit 2 becomes "1". The output of the comparison circuit 2 is held in the DFFN 9 and sent out as a coincidence output.

[0007]

In the above-mentioned conventional circuit, all the bits are determined at the same time while all bits are held in the shift register. Therefore, as the number of bits increases, the number of gate stages, that is, the value of Log ₂ (n) increases, and there is a disadvantage that the match determination time increases. Therefore, if the match detection circuit having a large number of bits is operated at a high speed, the match determination result may not be processed within one clock, and in such a case, a malfunction may occur.

[0008] Further, since all bits are determined at the same time after all bits are held in the shift register, more gates are connected in multiple stages as the number of bits increases. For this reason, there is a drawback that the time until the coincidence detection result is output depends on the number of bits to be compared, and it is not possible to detect a multi-bit coincidence value at high speed.

In Japanese Patent Application Laid-Open No. 2-257333, the circuit scale is a problem, and the above-mentioned disadvantages of the prior art cannot be solved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a match detection circuit capable of detecting a match at high speed regardless of the number of data bits. is there.

[0011]

The coincidence detecting circuit according to the present invention is a circuit for comparing n-bit (n is an integer of 2 or more, the same applies hereinafter) reference data with n-bit input data sequentially input in synchronization with a clock. A match detection circuit for detecting a match,
1 to m bits (m
Is an integer from 1 to n, the same applies hereinafter) and the value of the corresponding bit of the reference data are compared every clock, and the comparison result is held and the synchronization result is sequentially synchronized with the clock. An n-stage shift register that shifts to a subsequent stage, wherein an output of the last stage of the shift register is derived as a match detection result between the input data and the reference data.

In short, the match detection circuit does not judge whether or not a match is made while all bits are held, but judges whether or not a match is made every time one bit of data is input. Are sequentially held.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a coincidence detecting circuit according to the present invention. 3, the same parts as those in FIG. 3 are denoted by the same reference numerals, and detailed description of those parts will be omitted.

In FIG. 1, the coincidence detection circuit is a circuit for detecting coincidence between 8-bit reference data and 6-bit input data 10 sequentially input in synchronization with a clock 20. In this circuit, as in the case of FIG. 3, the bit to be detected, that is, the reference bit is "101101".
10 ".

The present circuit compares the value of 1 to m bits (m is an integer from 1 to n) of the input data 10 with the value of the corresponding bit of the reference data by one. The comparison is performed for each clock, and the comparison result is stored in an eight-stage shift register and sequentially shifted to the subsequent stage in synchronization with the clock 20. Then, the output of the last stage of the shift register becomes a result of detecting a match between the input data 10 and the reference data.

More specifically, an eight-stage cascade-connected DF
A shift register is constituted by FN1 to N8. Then, AND gates AND2 to AND8 are inserted between the stages of the shift register. The output of each of the AND gates AND2 to AND8 is held in the DFF of the next stage.

Here, the bit numbers of the detected bit arrangement are represented by b1, b2, b3, b4, b5, b6, b7, b8.
When the detected signal b1 is "1", the signal input as data 10 is connected to the data input of DFFN1. On the other hand, when the detected signal b1 is “0”, the signal input as data
After being inverted by V, it is input to DFFN1.

The detected signals b2 to b8 are "1".
In this case, the signal input as data 10 is connected to one of the inputs of AND gates AND2 to AND8, respectively. On the other hand, when the detected signals b2 to b8 are "0", the signal input as the data 10 is inverted by the inverter INV and then connected to one input of the AND gates AND2 to AND8. The Q outputs of DFFN1 to N7 are connected to the other inputs of AND gates AND2 to AND8. That is, the reference data is generated by inverting or non-inverting the input data and inputting it to the AND gate.

In this embodiment, "10110110" is detected. In this case, since b1 = “1”, the signal input as data 10 is connected to the input of DFFN1. Also,
Since b3 = b4 = b6 = b7 = “1”, a signal input as data 10 is connected to one input of each of the AND gates AND3, AND4, AND6, and AND7.
Further, since b2 = b5 = b8 = "0", a signal input as data 10 to one of the inputs of the AND gates AND2, AND5, and AND8 is inverted and then connected. The Q outputs of DFFN1 to N7 are connected to the other inputs of AND gates AND2 to AND8.

In this configuration, when the signals input as data 10 are defined as D1, D2, D3,..., D8 as shown in the time chart of FIG. Is stored in the DFFN1. In addition, the logical product of the D output of DFFN1 and the Q output of DFFN1, which is the result of comparison between b1 and D1, is held in DFFN2.

Therefore, DFFN2 is "1" when D1 and D2 are continuously coincident with bit arrangements b1 and b2.
, And "0" otherwise. Similarly, the comparison result between Dm and bm is input to one of the inputs of the AND gate ANDm, and D1 to Dm-1 and b1 to bm-1
The logical AND with the comparison result up to is taken and held in DFFNm. The DFFNm outputs "1" only when D1 to Dm continuously match the bit sequence b1 to bm to be compared, and outputs "0" otherwise.

At this time, the data held in the DFFNm, which is the m-th bit flip-flop, is a value for which a match / mismatch of m-bit continuous bit sequences has been determined.
As described above, the coincidence detection circuit determines whether data matches or not, each time one bit of data is input (the hatched portion in FIG. 2), and sequentially holds the determination results. In short, in this circuit, since the clock coincidence detection is performed for each bit, even when detecting multiple bits, the gates are not connected in multiple stages, which is suitable for high-speed operation.

In the above description, the case where n = 8, that is, the coincidence detection of 8-bit data is performed is described. However, the value of n is not limited to “8”. The effect becomes remarkable.

The present invention can take the following aspects in connection with the description of the claims.

(4) The coincidence detecting circuit according to any one of claims 1 to 3, wherein the reference data is generated by performing one of inversion and non-inversion of input data.

(5) The inversion of the input data is as follows:
2. The method according to claim 1, wherein the step is performed by an inverter.
5. The coincidence detection circuit according to any one of claims 1 to 4.

[0028]

As described above, according to the present invention, it is not determined whether or not each bit is held while all bits are held, but each time one bit of data is input, it is determined whether or not each bit is matched. , By sequentially storing the determination results,
Even when multi-bit detection is performed for each bit by performing clock coincidence detection for each bit, there is an effect that gates are not connected in multiple stages and high-speed operation can be performed without malfunction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a coincidence detection circuit according to an embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the coincidence detection circuit of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a conventional coincidence detection circuit.

FIG. 4 is a time chart illustrating an operation of the coincidence detection circuit of FIG. 3;

[Explanation of symbols]

 N1 to N8 D-type flip-flop AND2 to AND8 AND gate INV Inverter

Claims (3)

[Claims] 1. A match detection circuit for detecting a match between n-bit (n is an integer of 2 or more, the same applies hereinafter) reference data and n-bit input data sequentially input in synchronization with a clock, 1 to m already input in the input data
Comparing means for comparing the value of a bit (m is an integer from 1 to n, the same applies hereinafter) with the value of a corresponding bit of the reference data every clock, and holding the comparison result to synchronize with the clock And an n-stage shift register that sequentially shifts to a subsequent stage, and derives an output of the last stage of the shift register as a result of detecting a match between the input data and the reference data. 2. The comparing means, which is inserted between each stage of the shift register and has one input to which the output of the previous stage of the register is applied and the other input to which the value of the corresponding bit of the reference data is applied 2. The coincidence detecting circuit according to claim 1, further comprising a gate circuit whose output is held at a stage subsequent to said register. 3. The shift register according to claim 1, wherein the shift register is an n-stage cascade-connected flip-flop.
Or the coincidence detection circuit according to 2.