JPH1012880A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid causing a potential in a gate insulation film to prevent the damage of this film even in case of a nonuniform potential distribution in a wafer plane by forming a second insulation film on an insulative electrode forming film, selectively etching the second film and activating an impurity to obtain electrodes. SOLUTION: Without heat treating a work 100, i.e., activating an impurity 106a doped in a polysilicon film 106, the process proceeds to a next step of coating a resist film on the film 16 to do specified resist process and then doing specified etching and resist removal to form gate electrodes from the film 106. The film 106 with the gate electrodes is regarded as an insulation film and hence no potential occurs in this film if the plasma density at a plasma etching is uniform.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally performed semiconductor devices,
For example, a semiconductor wafer having a MOS (metal oxide semiconductor) element (hereinafter, referred to as a “wafer”)
One embodiment of the manufacturing method will be described below with reference to the flowcharts shown in FIGS.

First, a flowchart shown in FIG. 7 (step S
As shown in 10 to 22), the surface of the object to be processed, for example, the surface of a silicon wafer is subjected to a thermal oxide film treatment using, for example, a thermal oxide film apparatus, thereby forming a silicon oxide film to be a gate insulating film. (Step S1)
2) Then, a polysilicon film is formed on the silicon oxide film by, for example, a plasma CVD device (Step S14). After doping predetermined ions, so-called impurities, into the polysilicon film formed in step S14 by, for example, an ion implanter (step S16), the wafer is subjected to a heat treatment by a heating means, so that the polysilicon film is formed in the polysilicon film. The doped impurity is activated, and a p-type or n-type polysilicon film (hereinafter, referred to as “p-type”) is formed.
This is referred to as “active polysilicon film”. ) Is formed (step S18).

[0004] A resist film is applied on the active polysilicon film formed in step S18 by, for example, a resist coating device, and a predetermined resist process is performed. Then, the active polysilicon film is subjected to, for example, a plasma process. By performing a predetermined etching process by the apparatus (Step S20), the active polysilicon film on the wafer becomes a gate electrode (Step S22).

Further, a flowchart shown in FIG.
24 to 36), a predetermined silicon oxide film other than the gate electrode formed in step S22 is doped with, for example, LDD (lightly doped drain) ions by, for example, an ion implanter (step S22). S24) A silicon oxide film serving as an insulating film is formed on the wafer by, for example, a plasma CVD device (Step S26). Further, after performing a predetermined resist process on the insulating film, an anisotropic etching process is performed by, for example, a plasma processing apparatus to form an LDD spacer at a peripheral portion of the gate electrode on the wafer (step S28). .

After doping source ions, drain ions, and the like in predetermined portions of the peripheral portion of the gate electrode with, for example, an ion implantation device (step S30), an interlayer insulating film is formed on the wafer by, for example, a plasma CVD device. A silicon oxide film is formed (Step S32).
After performing a predetermined resist process on the interlayer insulating film, a contact hole is formed at a predetermined location on the wafer by performing an etching process using, for example, a plasma processing apparatus (step S34). Thereafter, the wafer is subjected to a heat treatment by a heating means to activate ions or the like doped in each layer on the wafer (step S36). Thereafter, a predetermined wiring material is formed in the contact hole by, for example, a plasma CVD apparatus. After performing various processes such as forming an electrode by evaporating an aluminum alloy, for example, a semiconductor device is completed.

[Problems to be solved by the invention]

In the above-described conventional method for manufacturing a semiconductor device, the gate electrode is formed by doping the polysilicon film with impurities, activating the polysilicon film by heat treatment, and then selectively etching. Furthermore, thereafter, the formation and etching of the insulating film are appropriately repeated using a plasma CVD apparatus, a plasma etching apparatus, or the like, thereby forming an LDD spacer, a contact hole, and the like.

However, with recent high integration and miniaturization of semiconductor devices, the gate insulating film is also made to have a fine multilayer, and an etching process for forming the gate electrode, the LDD spacer or the contact hole, for example, plasma etching. During processing, due to the non-uniformity of the plasma density, the self-bias voltage changes in the wafer surface, and a voltage corresponding to the change in the self-bias is applied to the gate insulating film between the gate electrode and the wafer, for example, the thickness of the gate insulating film. Is 10 nm, for example, when the potential difference is about 10 V, the gate insulating film is broken.

[0009] With the recent ultra-high integration and miniaturization of semiconductor devices, a plasma CVD apparatus capable of low-temperature processing is often used when forming an insulating film in each process. The gate insulating film may be destroyed in the same manner as in the above-described plasma etching process when the wafer is processed by the method described above, and the gate insulating film may also be destroyed due to charge-up occurring during ion implantation of impurities or the like. there were.

The present invention has been made in view of the above-mentioned problems of the conventional method of manufacturing a semiconductor device, and has not been subjected to heat treatment after impurity doping, that is, non-activated polysilicon. Focusing on the fact that the film can be regarded as almost an insulating film, after performing each processing step in the above-mentioned semiconductor device manufacturing, the wafer is heated at the stage of the so-called final step, and the impurities in each layer are activated to perform plasma processing. Even when the potential distribution becomes non-uniform in the wafer surface during
An object of the present invention is to provide a new and improved method for manufacturing a semiconductor device in which a potential is not generated in a gate insulating film and the gate insulating film is not broken.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and a first insulating film formed on the first insulating film. A method for manufacturing a semiconductor device having an electrode structure having an electrode formed and a second insulating film covering the electrode, comprising: forming an insulating electrode material film on the semiconductor substrate; After the impurities are introduced into the material film, the insulating electrode forming material film is selectively etched, a second insulating film is formed on the insulating electrode forming material film, and the second insulating film is selectively formed. The method includes a step of obtaining an electrode by activating the impurities after the etching, so that when the plasma processing is performed by the plasma etching apparatus or the plasma CVD apparatus, the plasma density is not uniform. Even if the potential distribution in the plane becomes non-uniform, the electrode forming material film that has not been activated after the introduction of the impurity can be regarded as almost an insulating film. Since no potential is generated in the insulating film and no charge-up occurs when impurities are doped using an ion implantation apparatus, the semiconductor device can be manufactured at a uniform and high yield without breaking the gate insulating film. Can be manufactured.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment in which the method of manufacturing a semiconductor device according to the present invention is applied to a method of manufacturing a semiconductor device having a MOS element using a silicon wafer will be described in detail. In the following description, components having substantially the same functions and configurations will be denoted by the same reference numerals, and redundant description will be omitted.

First, as shown in FIG. 1A, a silicon oxide film 104 is formed on a bare silicon wafer 102 (step S100) using, for example, a thermal oxide film apparatus as shown in FIG. Is formed (step S102). A part of the silicon oxide film 104 functions as a gate insulating film after performing a predetermined process described later. Further, a polysilicon film 106 is formed on the silicon oxide film 104 by, for example, a plasma CVD apparatus as shown in FIG. 1C (step S10).
4). Next, as shown in FIG.
As shown in (1), predetermined ions, so-called impurities 106a, are doped by, for example, an ion implantation apparatus (step S106).

According to the present embodiment, the object to be processed 100 is not heated, that is, the polysilicon film 1 is not heated.
In this case, the process proceeds to the next step without activating the impurity 106a doped in the polysilicon film 106.
For example, after applying a resist film by a resist coating device and performing a predetermined resist process, the polysilicon film 10 is formed.
For example, by performing a predetermined etching process (Step S108) and removing the resist by using a plasma processing apparatus, the polysilicon film 106 becomes
The gate electrode portion is as shown in FIG. 2E (step S110).

As described above, according to the present embodiment, since the activation of the impurity 106a is not performed immediately after the step S106, the polysilicon film forming the gate electrode portion can be regarded as almost an insulating film. Therefore, even when the potential distribution becomes non-uniform in the wafer surface due to non-uniform plasma density during the plasma etching process described above and below or during the formation of the insulating film by the plasma CVD apparatus described below, the potential is applied to the gate insulating film. Does not occur. Therefore, for example, even when the self-bias voltage changes in the wafer surface, a voltage corresponding to the change of the self-bias does not occur in the gate insulating film, so that the gate insulating film is not broken.

As shown in FIG. 2F, a predetermined impurity is formed on the predetermined silicon oxide film 104 other than the polysilicon film 106 at a predetermined location on the back surface of the silicon oxide film 104 by, for example, an ion implantation apparatus. , For example, LDD
Doping with the ions 102a (Step S11)
2). According to the present embodiment, even when doping impurities using the ion implantation apparatus described above and below, charge-up does not occur, so that the gate oxide film can be prevented from being broken.

On the silicon oxide film 104 and the polysilicon film 106 serving as a gate electrode, for example, plasma CV
The silicon oxide film 108 serving as an insulating film is formed as shown in FIG. 3G by the D apparatus (step S114). Further, as shown in FIG. 3H, a resist process is performed on the silicon oxide film 108 in the same manner as described above, and then an anisotropic etching process is performed using, for example, a plasma processing apparatus. LD on the periphery of the gate electrode
A D spacer is formed (Step S116).

From above the silicon oxide film 104, FIG.
As shown in (I), a source ion or a drain ion 102c is formed in a predetermined place (a place other than the polysilicon film 106 and the silicon oxide film 108) on the back surface of the silicon oxide film 104 by, for example, an ion implantation apparatus.
Is doped (step S118). Thereafter, a silicon oxide film 110 serving as an interlayer insulating film is again formed on the object 100 by, for example, a plasma CVD apparatus as shown in FIG.
It is formed as shown in (J) (step S120). As shown in FIG. 4K, the silicon oxide film 110 is subjected to a predetermined resist process similar to the above, and then is subjected to an etching process using, for example, a plasma processing apparatus, to thereby perform a predetermined process on the object 100 to be processed. Contact hole 112
Is formed (step S122).

According to the present embodiment, after the semiconductor device manufacturing process up to the formation of the contact hole 112 is performed, that is, after all the etching processes and the like on the object 100 are completed, the object 100 Is heated by a heating means to activate the impurities 102a, 102c and 106a doped in each layer on the object 100, as shown in FIG.
The LDD region 102b, the source or drain region 102d, and the gate electrode 106b are respectively formed (Step S124). After that, after performing various steps such as vapor deposition of a predetermined wiring material, for example, an aluminum alloy to form an electrode in the contact hole 112 or the like by, for example, a plasma CVD apparatus, a semiconductor device is completed.

As described above, the preferred embodiment of the present invention has been described by taking as an example a method of manufacturing a semiconductor device having MOS elements using a silicon wafer, but the present invention is not limited to such a configuration. A person skilled in the art should be able to conceive various modifications and changes within the scope of the technical concept of the claims, and it is understood that these also naturally belong to the technical scope of the present invention.

For example, in the above embodiment, the heat treatment for activating the impurities doped in each film formed on the object to be processed is performed after the formation of the contact hole. However, the present invention is not limited to the above embodiment. However, in the manufacturing process of a semiconductor device, the above-described heat treatment can be applied to any manufacturing process in which the gate insulating film is not broken. Also, the present invention
The present invention can be applied not only to the above gate insulating film but also to any insulating film on a semiconductor device for preventing destruction due to a potential load generated in the above manufacturing process.

Further, in the above-described embodiment, polysilicon has been described as an example of a constituent material of the gate electrode. However, the present invention is also applicable to polycide. For example, phosphorus or boron may be used. The present invention can be applied to doped polysilicon (Doped polysilicon). Further, the present invention can be applied to use of any doping ions, and can be applied not only to the semiconductor device described in the above embodiment, but also to a glass substrate for LCD and the like.

[0023]

As described above, according to the present invention,
After the doping of the impurities, the heat treatment is not performed, that is, the polysilicon film of the gate electrode portion that is not activated can be regarded as almost an insulating film, and after performing each processing step in the manufacture of the semiconductor device, By heating the wafer at the stage of the so-called final process and activating the impurities of each layer, even if the potential distribution becomes uneven in the wafer surface during the plasma processing, no potential is generated in the gate insulating film. Does not destroy the gate insulating film. Also, when doping impurities, charge-up does not occur, so that a semiconductor device can be manufactured with a uniform and high yield without destroying the gate insulating film. This is a manufacturing method suitable for miniaturization.

[Brief description of the drawings]

FIG. 1 shows an M using a silicon wafer to which the present invention can be applied.
FIG. 4 is a schematic cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device having an OS element.

FIG. 2 is a diagram showing an M using a silicon wafer to which the present invention can be applied;
FIG. 4 is a schematic cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device having an OS element.

FIG. 3 is a diagram showing an M using a silicon wafer to which the present invention can be applied;
FIG. 4 is a schematic cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device having an OS element.

FIG. 4 is a diagram showing an M using a silicon wafer to which the present invention can be applied;
FIG. 4 is a schematic cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device having an OS element.

FIG. 5 is a diagram showing an M using a silicon wafer to which the present invention can be applied;
5 is a flowchart illustrating an embodiment of a method for manufacturing a semiconductor device having an OS element.

FIG. 6 is a diagram showing an M using a silicon wafer to which the present invention can be applied;
5 is a flowchart illustrating an embodiment of a method for manufacturing a semiconductor device having an OS element.

FIG. 7 is a flowchart showing one embodiment of a method for manufacturing a semiconductor device having a MOS element using a conventional silicon wafer.

FIG. 8 is a flowchart showing one embodiment of a method for manufacturing a semiconductor device having a MOS element using a conventional silicon wafer.

[Explanation of symbols]

 Reference Signs List 100 object 102 bare silicon wafer 102a LDD ion 102b LDD region 102c source or drain ion 102d source or drain region 104 silicon oxide film 106 polysilicon film 106a impurity 106b gate electrode 108 silicon oxide film 110 silicon oxide film 112 contact hole S step

Claims (1)

[Claims] A semiconductor substrate; a first insulating film formed on the semiconductor substrate; an electrode formed on the first insulating film; and a second insulating film covering the electrode. A method for manufacturing a semiconductor device having an electrode structure, comprising: forming an insulating electrode material film on a semiconductor substrate; introducing an impurity into the insulating electrode material film; and selecting the insulating electrode forming material film. Etching, and a second insulating film is formed on the insulating electrode forming material film.
And a step of obtaining an electrode by activating the impurity after selectively etching the insulating film.