JPS61296740A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent disconnection at the stepped portion of aluminum to be generated at the gate shoulder portion on the occasion of vapor deposition of aluminum wiring pattern by forming a poly-Si gate of a MOS semiconductor device with the trapozoidal sectional view. CONSTITUTION:A tapered portion 11a is provided to the shoulder part of a poly-Si gate 11 and the sectional view of such gate 11 is formed in the trapezoidal form. This tapered portion 11a improves flatness by high concentration PSG 9 and also improves the shape of stepped portion of vapor deposited aluminum 8 and thereby disconnection at the stepped portion of aluminum 8 to generated at the shoulder part of gate 11 can be prevented. On the occasion of etching the vapor deposited aluminum 8, the shoulder part of gate 11 may be uniformly coated with PR of aluminum 8 and the etching can be done only in the necessary part.

Description

[Detailed Description of the Invention] Industrial Retired King Skin and Minutes! The present invention relates to an MO3 type semiconductor device, and more particularly to the shape of its polysilicon gate.

As an example of a pill-suppressing MO5 type semiconductor device, a polysilicon gate P-channel transistor is shown below with reference to FIG. As shown in the figure, the transistor (1) has N
Silicon oxide lit! type silicon substrate (hereinafter referred to as Si substrate) (2) (Hereinafter referred to as 5t02 membrane) (3)
At the same time, a gate wiring of polysilicon (hereinafter referred to as poly-Si) (4) is formed on the 5i02 film (3).
P-type impurities are implanted into the i-substrate (2) to form a source region (6) and a drain region (
After forming 7), wiring was formed by vapor deposition of aluminum (hereinafter referred to as 8!) (8). Further, as will be described later, phosphor glass (hereinafter referred to as PSG) (9) is formed by chemical vapor deposition to flatten the convex portion of the polygon 5i (4).

Here, the outline of the manufacturing process of the transistor (1) is as follows:
The following will be described with reference to FIGS. 7 to 10. First, as shown in FIG. 7, a Si substrate (2) is heated to
Heating to around 0℃, Sing Il was formed on the surface by thermal oxidation.
! J! (3) is formed. Then, poly 5i (4) is formed on the entire surface of the 5to2 film (3), and after applying photoresist (hereinafter referred to as PR') (10) to the gate wiring pattern, poly 5t (4) is formed by ion etching. Etching is performed to leave a poly 5t (4) gate as shown in Fig. 8. At this time, the poly 5t (4) gate shown in Fig. 8 has a size of 2 to 3 μ(m). Therefore, it is etched by ion etching, which is anisotropic etching, and the cross-sectional shape is almost vertical, creating a step. As shown in Figure 8, near the gate of poly 5i (4), P-type impurities are implanted into the thin portion of the 5io2 film (3) to form a source region (6) and a drain region (7). After forming the gate (4), source (6), and drain region (7) in this manner, Af (8) is deposited to form a predetermined wiring pattern in order to take out electrodes from each region. However, as mentioned above, the poly 5i (4) gate has a nearly vertical cross-sectional shape and a sharp step, so if Af (8) is directly deposited,
The wiring is more likely to break than the shoulder part (4a) of the gate. Therefore, as shown in FIG. 9, after pouring high-concentration PSG (9) to fill the recess near the gate of poly 5i (4) and flatten it, as shown in FIG. ), followed by source and drain regions (6) (7).
At the same time, an electrode is taken out and patterning is performed to form a polygonal gate electrode 5t (4).

However, as mentioned above, in a MOS type semiconductor device, in order to prevent breakage that occurs at the gate shoulder part (48) of poly 5t (4) when depositing Af (8), high concentration is applied. The surface is flattened by PSG (9), but 81 (
The step coverage of step 8) is insufficient, and step breakage still tends to occur at the gate shoulder (4a) as shown by the arrow in FIG. Also, AI! In order to form the wiring (8) in a predetermined pattern, PR (
When etching Al(8) by coating (not shown),
The PR becomes thinner at the gate shoulder (4a). Therefore,
A problem arises in that the resist in this area becomes defective and etching is performed on unnecessary areas.

A method for solving the problems The present invention is characterized in that a polysilicon gate electrode in a MOS type semiconductor device is formed into a substantially trapezoidal cross section by providing a taper at the shoulder portion.

(2) A polysilicon gate electrode in a MOS type semiconductor device is formed to have a substantially trapezoidal cross section, and the edges of the shoulder portion are eliminated to prevent aluminum from breaking.

One embodiment of the present invention will be described below with reference to FIGS. 1 to 5. The same reference numerals as in FIG. 6 indicate the same parts, and the explanation thereof will be omitted. First, in FIG. 1, (2) is St
Substrate, (3) is 5i02 film, (8) is ^/, (9) is P
S G, (11) is a gate made of polySt0 The feature of the present invention is that a taper (11a') is provided at the shoulder of the gate '(11) made of polySi, so that the gate (11) has a substantially trapezoidal cross section. It was formed. The taper (11a) improves the flattening caused by the high concentration PSG (9), and also improves the step shape of the deposited Ai' (8),
It is possible to prevent breakage of Af (8) occurring at the shoulder portion of (11). Also, evaporated eight! When etching (8), PR of Af (8) can be applied to a uniform thickness even on the shoulder portion of the gate (11), making it possible to etch only the necessary portion.

Next, taper (
11a) will be described below with reference to FIGS. 2 to 5. First, as shown in FIG. 2, the same Si substrate (2) as in the conventional method is heated and Sing M! is deposited on the surface. (
After forming 3), poly 5i (11) is formed and PR (12) is applied to the gate wiring pattern. Thereafter, the poly 5t (11) is etched by about % to about half of its thickness by isotropic etching such as plasma etching or wet etching. In this case, the isotropic process 7 etches the polySt (11) equally in the vertical and horizontal directions, so it wraps around below the PR (12) and etches the polySi as shown in Figure 3.
(11) is etched to form a taper (11a).Next, when etching is performed by anisotropic etching such as ion etching, as shown in FIG. The lower half of (11) is etched almost vertically to form the gate of the board JSi (11) with a substantially trapezoidal cross section as shown in FIG. Bye.

According to the present invention, since the poly-Si gate of the MOS type semiconductor device is formed to have a substantially trapezoidal cross section, when the Ai' wiring pattern is deposited, the A/ step break that occurs at the gate shoulder can be avoided. can be prevented. Further, it is possible to apply A/PR to a uniform thickness on the gate shoulder portion, making it possible to etch only the necessary portions.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part showing an embodiment of a MOS type semiconductor device according to the present invention, and FIGS. 2 to 5 are explanations of the process of forming a polySt gate in the MOS type semiconductor device of FIG. 1. 6 are sectional views of essential parts of a conventional MOS type semiconductor device, and FIGS. 7 to 10 are explanatory diagrams of the manufacturing process of the MOS type semiconductor device of FIG. 6. (11) −: Polysilicon gate electrode, (lla)
-Taper.

Claims (1)

[Claims] (1) A semiconductor device characterized in that a gate electrode of polysilicon in a MOS type semiconductor device is formed to have a substantially trapezoidal cross section by providing a taper at the shoulder portion.