JPH10116246A5 - - Google Patents

Info

Publication number
JPH10116246A5
JPH10116246A5 JP1997196149A JP19614997A JPH10116246A5 JP H10116246 A5 JPH10116246 A5 JP H10116246A5 JP 1997196149 A JP1997196149 A JP 1997196149A JP 19614997 A JP19614997 A JP 19614997A JP H10116246 A5 JPH10116246 A5 JP H10116246A5
Authority
JP
Japan
Prior art keywords
bus
bridge
cycles
decoding
subtractively
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1997196149A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10116246A (ja
Filing date
Publication date
Priority claimed from US08/684,584 external-priority patent/US5864688A/en
Application filed filed Critical
Publication of JPH10116246A publication Critical patent/JPH10116246A/ja
Publication of JPH10116246A5 publication Critical patent/JPH10116246A5/ja
Pending legal-status Critical Current

Links

JP9196149A 1996-07-19 1997-07-22 バス上のアドレスの絶対的及び減算的デコード装置及び方法 Pending JPH10116246A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US684584 1996-07-19
US08/684,584 US5864688A (en) 1996-07-19 1996-07-19 Apparatus and method for positively and subtractively decoding addresses on a bus

Publications (2)

Publication Number Publication Date
JPH10116246A JPH10116246A (ja) 1998-05-06
JPH10116246A5 true JPH10116246A5 (enExample) 2005-04-07

Family

ID=24748657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9196149A Pending JPH10116246A (ja) 1996-07-19 1997-07-22 バス上のアドレスの絶対的及び減算的デコード装置及び方法

Country Status (5)

Country Link
US (1) US5864688A (enExample)
EP (1) EP0820021B1 (enExample)
JP (1) JPH10116246A (enExample)
DE (1) DE69724884T2 (enExample)
TW (1) TW337007B (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3403284B2 (ja) * 1995-12-14 2003-05-06 インターナショナル・ビジネス・マシーンズ・コーポレーション 情報処理システム及びその制御方法
US6047349A (en) * 1997-06-11 2000-04-04 Micron Electronics, Inc. System for communicating through a computer system bus bridge
US6076128A (en) * 1998-01-28 2000-06-13 International Business Machines Corp. Data transfer method between buses, bridge devices for interconnecting buses, and data processing system including multiple buses
US6260093B1 (en) * 1998-03-31 2001-07-10 Lsi Logic Corporation Method and apparatus for arbitrating access to multiple buses in a data processing system
US6178469B1 (en) * 1998-06-30 2001-01-23 Compaq Computer Corporation Enabling access to a selected one of two detected same type peripheral devices connected to separate peripheral slots in a computer
US6216192B1 (en) * 1998-06-30 2001-04-10 Compaq Computer Corporation Dynamic resource allocation across bus bridges
US7734852B1 (en) 1998-08-06 2010-06-08 Ahern Frank W Modular computer system
US6119191A (en) * 1998-09-01 2000-09-12 International Business Machines Corporation Performing PCI access cycles through PCI bridge hub routing
US6336158B1 (en) * 1998-10-30 2002-01-01 Intel Corporation Memory based I/O decode arrangement, and system and method using the same
US6321174B1 (en) * 1999-02-09 2001-11-20 Winbond Electronics Corp. Apparatus and method for testing add-on device of a computer system
US6574233B1 (en) * 1999-04-09 2003-06-03 Avaya Technology Corp. Arrangement for redefining an interface while maintaining backwards compatibility
US6457091B1 (en) * 1999-05-14 2002-09-24 Koninklijke Philips Electronics N.V. PCI bridge configuration having physically separate parts
US6574752B1 (en) 1999-07-15 2003-06-03 International Business Machines Corporation Method and system for error isolation during PCI bus configuration cycles
EP1594066A3 (en) * 2000-02-14 2006-07-05 Tao Logic Systems LLC Computer docking system and method
TW457420B (en) * 2000-03-29 2001-10-01 Mitac Int Corp Single-step debugging card device applied in PCI interface and the method thereof
US6594719B1 (en) 2000-04-19 2003-07-15 Mobility Electronics Inc. Extended cardbus/pc card controller with split-bridge ™technology
US7080187B2 (en) * 2001-12-20 2006-07-18 Intel Corporation Bug segment decoder
US7219176B2 (en) * 2002-09-30 2007-05-15 Marvell International Ltd. System and apparatus for early fixed latency subtractive decoding
JP2008276691A (ja) * 2007-05-07 2008-11-13 Kwok-Yan Leung ハードディスクインターフェースを模擬したインターフェースカード
US8396998B2 (en) 2010-12-10 2013-03-12 Kingston Technology Corp. Memory-module extender card for visually decoding addresses from diagnostic programs and ignoring operating system accesses
TW201344445A (zh) * 2012-04-27 2013-11-01 Sunix Co Ltd 可分配低階輸入輸出埠其介面位址的ｐｃｉ介面裝置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5467295A (en) * 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
US5588125A (en) * 1993-10-20 1996-12-24 Ast Research, Inc. Method and apparatus for increasing bus bandwidth on a system bus by inhibiting interrupts while posted I/O write operations are pending
US5568621A (en) * 1993-11-10 1996-10-22 Compaq Computer Corporation Cached subtractive decode addressing on a computer bus
US5625829A (en) * 1994-03-25 1997-04-29 Advanced Micro Devices, Inc. Dockable computer system capable of symmetric multi-processing operations
US5572688A (en) * 1994-09-30 1996-11-05 Tyan Computer Corporation Primary bus processing element with multifunction interconnection to secondary bus
US5621902A (en) * 1994-11-30 1997-04-15 International Business Machines Corporation Computer system having a bridge between two buses with a direct memory access controller and an alternative memory access controller
US5557758A (en) * 1994-11-30 1996-09-17 International Business Machines Corporation Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one of the buses
US5642489A (en) * 1994-12-19 1997-06-24 International Business Machines Corporation Bridge between two buses of a computer system with a direct memory access controller with accessible registers to support power management
US5594882A (en) * 1995-01-04 1997-01-14 Intel Corporation PCI split transactions utilizing dual address cycle
US5559968A (en) * 1995-03-03 1996-09-24 Compaq Computer Corporation Non-conforming PCI bus master timing compensation circuit
US5596729A (en) * 1995-03-03 1997-01-21 Compaq Computer Corporation First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus
US5621900A (en) * 1995-05-17 1997-04-15 Intel Corporation Method and apparatus for claiming bus access from a first bus to a second bus prior to the subtractive decode agent claiming the transaction without decoding the transaction

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