CA2181704A1 - Highly pipelined bus architecture - Google Patents

Highly pipelined bus architecture

Info

Publication number
CA2181704A1
CA2181704A1 CA002181704A CA2181704A CA2181704A1 CA 2181704 A1 CA2181704 A1 CA 2181704A1 CA 002181704 A CA002181704 A CA 002181704A CA 2181704 A CA2181704 A CA 2181704A CA 2181704 A1 CA2181704 A1 CA 2181704A1
Authority
CA
Canada
Prior art keywords
transactions
bus
deferred
transaction
bus architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002181704A
Other languages
French (fr)
Other versions
CA2181704C (en
Inventor
Nitin V. Sarangdhar
Gurbir Singh
Konrad Lai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority claimed from PCT/US1995/002505 external-priority patent/WO1995024678A2/en
Publication of CA2181704A1 publication Critical patent/CA2181704A1/en
Application granted granted Critical
Publication of CA2181704C publication Critical patent/CA2181704C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)

Abstract

A computer system (15), as shown , incorporating a pipelined bus (20) that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system (15) includes bus agents (2, 4, 6, 8, 10, 12, 14) having in-order queues (100) that track multiple outstanding transactions across a system bus (20) and that perform snops in response to transaction request, providing snoop results and modified data within one transaction.
Additionally, the system (15) supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
CA002181704A 1994-03-01 1995-03-01 Highly pipelined bus architecture Expired - Fee Related CA2181704C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US20638294A 1994-03-01 1994-03-01
US08/206,382 1994-03-01
US39096995A 1995-02-21 1995-02-21
US08/390,969 1995-02-21
PCT/US1995/002505 WO1995024678A2 (en) 1994-03-01 1995-03-01 Highly pipelined bus architecture

Publications (2)

Publication Number Publication Date
CA2181704A1 true CA2181704A1 (en) 1995-09-14
CA2181704C CA2181704C (en) 2006-08-08

Family

ID=36791714

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002181704A Expired - Fee Related CA2181704C (en) 1994-03-01 1995-03-01 Highly pipelined bus architecture

Country Status (1)

Country Link
CA (1) CA2181704C (en)

Also Published As

Publication number Publication date
CA2181704C (en) 2006-08-08

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