JPH10289120A - Information processor - Google Patents

Information processor

Info

Publication number
JPH10289120A
JPH10289120A JP9095530A JP9553097A JPH10289120A JP H10289120 A JPH10289120 A JP H10289120A JP 9095530 A JP9095530 A JP 9095530A JP 9553097 A JP9553097 A JP 9553097A JP H10289120 A JPH10289120 A JP H10289120A
Authority
JP
Japan
Prior art keywords
memory
coprocessor
cpu
bus
arithmetic processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9095530A
Other languages
Japanese (ja)
Inventor
Hidetada Fukunaka
Shigeru Toyazaki
Tsutomu Yamazaki
勉 山▲崎▼
茂 戸矢崎
秀忠 福中
Original Assignee
Hitachi Inf Technol:Kk
Hitachi Ltd
株式会社日立インフォメーションテクノロジー
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Inf Technol:Kk, Hitachi Ltd, 株式会社日立インフォメーションテクノロジー, 株式会社日立製作所 filed Critical Hitachi Inf Technol:Kk
Priority to JP9095530A priority Critical patent/JPH10289120A/en
Publication of JPH10289120A publication Critical patent/JPH10289120A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To effectively utilize an existing memory bus and to reduce the cost in the case of adding a co-processor to an information processor. SOLUTION: A CPU 1 senses that arithmetic processing requests are increased by a memory access frequency judgement counter 11, writes program data or the like to be executed by the co-processor 3 to a memory 2 and opens an address/data bus 50. The co-processor 3 controls the opened address/data bus 50, reads the program data from the memory 2 and executes an arithmetic processing. After an arithmetic operation is ended, an arithmetic result is written to the memory 2, arithmetic operation completion reporting signals 55 are outputted, a bus control right is returned to the CPU and thus, achievement is made.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for sharing a bus of an information processing apparatus, and more particularly to a CPU having an external memory.
And an information processing apparatus having a configuration in which a coprocessor for arithmetic processing is added to the information processing apparatus.

[0002]

2. Description of the Related Art Generally, in the prior art, when a coprocessor is connected to a CPU, a dedicated interface must be separately provided between the CPU and the coprocessor.
LSIs and coprocessors require signal pins in the LSI. As a result, there were problems in terms of increasing the amount of hardware and the price. In addition, in an information processing apparatus that does not use a coprocessor, the frequency of access to a memory or an I / O device decreases when the processing load of the CPU increases, and the processing efficiency of the system is not balanced. was there.

[0003]

In the above prior art, when a coprocessor is added, it is necessary to provide a dedicated interface between the CPU and the coprocessor, and the cost increases due to an increase in the number of signal pins or an increase in the amount of hardware. In addition, there is a problem that the CPU has to be aware of the operation of the coprocessor when transmitting the operation processing data to the coprocessor and receiving the operation processing result. Further, when the arithmetic processing of the CPU increases, the frequency of access to the memory bus decreases, so that the memory bus is not effectively used, and there is room for performance improvement as a device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus sharing system in an information processing apparatus using a memory, which can be connected without increasing the number of pins of LSIs of a CPU and a coprocessor by effectively utilizing an existing memory bus. To provide. Another object of the present invention is to provide a small, low-cost bus that can improve the performance of a system by causing a coprocessor to partially perform processing without being conscious of the CPU when CPU arithmetic processing is concentrated. Another object of the present invention is to provide a sharing method.

[0005]

The present invention employs the following bus control system to achieve the above object.

In a configuration in which an arithmetic coprocessor is added to an information processing device having a memory, an address / data bus is constructed between the CPU, the memory, and the coprocessor. CP
A coprocessor interface control unit is provided in U
When transmitting and receiving data between the U and the coprocessor, the control signal to the memory is suppressed and used as a dedicated bus, and by performing an arithmetic processing request to the coprocessor, control can be performed without increasing the number of LSI pins of the CPU. . Further, a counter for sensing the frequency of accessing the memory and a bus release flag are provided in the CPU. When the memory access frequency of the CPU is low, the memory access frequency determination counter
It is determined that the processing load of U has increased, and the release signal 5
9 is output. CPU that senses increase in arithmetic processing load
Writes program data for causing the coprocessor to perform arithmetic processing in the memory, and sets the bus release flag 12 to O
By setting N, the memory bus is released to the coprocessor. Upon receiving the bus release signal, the coprocessor directly fetches program data and the like from a preset memory address area without passing through the CPU, executes the arithmetic processing, and stores the data after the arithmetic processing, and sends the arithmetic processing to the CPU. By reporting the end of the operation and the return of the control right of the memory bus, the CPU can perform the operation without being aware of the arithmetic processing of the coprocessor.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments.

FIG. 1 is a block diagram schematically showing a system to which the present invention is applied.

In FIG. 1, a CPU 1 has an I / O interface control unit 13, a memory interface control unit 10, and the like, and executes arithmetic processing in response to a request from an I / O device. The memory 2 having a direct interface with the CPU 1 stores program data and the like necessary for arithmetic processing. 3 assists the arithmetic processing of the CPU,
An arithmetic processing coprocessor including the memory control unit 30. In the prior art, separate interfaces were required between the CPU 1 and the memory 2 and between the CPU 1 and the coprocessor 3, respectively.
The coprocessor 3
By connecting one address / data signal and constructing one address / data bus 50,
CPU 1-coprocessor 3 without adding SI pin
Data can be transmitted and received between them. The procedure will be described below. First, the CPU 1 controls its own memory control unit 10.
Check whether the memory access is currently being performed
If not, the subsequent memory access is suppressed. Next, a coprocessor-dedicated access signal 54 is transmitted to report that the access is to the coprocessor 3. Subsequently, program data for causing the coprocessor 3 to execute an operation is transmitted in the same manner as in a normal memory write. When the coprocessor 3 receives the coprocessor-specific access signal 54, the coprocessor 3 suppresses the memory control signal 56 so that data is not erroneously written to the memory 2,
And receives the program data sent out onto the address / data bus 50, thereby executing the arithmetic processing.
After the completion of the operation, the coprocessor 3 outputs the operation completion report signal 55
Is output. When the CPU 1 receives the operation completion report signal 55 from the coprocessor 3, the CPU 1 accesses the coprocessor 3 in the same manner as a normal memory read and reads the operation result. As described above, by using the address / data bus 50 shared with the memory 2 and by the memory control signal 10, the CPU 1 -coprocessor 3 is operated in the same manner as the normal memory access.
It is possible to send and receive data between them. Further, in the present invention, C
The memory 2 is used for relaying data transmission and reception between the CPU 1 and the coprocessor 3 for the purpose of parallel operation between the CPU 1 and the coprocessor 3 when the operation processing of the PU 1 is concentrated. The processing procedure will be described below with reference to FIG.

First, with regard to the determination when the CPU 1 concentrates on the arithmetic processing, the number of memory accesses within a certain time is monitored by a memory access frequency determination counter 11 in the CPU 1. When the value of the counter 11 becomes equal to or less than the reference value, it is determined that the number of times of memory access has decreased, that is, the processing load in the CPU 1 has increased (10).
0), a memory control signal 52 is output to write program data for causing the coprocessor 3 to perform arithmetic processing in a specific address area of the memory 2 (101), and at the same time, the CP
U1 specifies an operation result storage address area in the memory 2. Next, the data transmission means between the CPU 1 and the coprocessor 3 reports the memory address area of the program data written to the coprocessor (102).
U1 turns on the flag 12 to turn on the bus release signal 53.
To release the control right of the address / data bus 50 to the coprocessor 3 (103). The CPU 1 does not execute subsequent memory access until the bus control right is returned.
Upon receiving the bus release signal 53, the memory control unit 30 of the coprocessor 3 outputs the memory control signal 57, reads out the program data from the program data storage area (104), and executes an arithmetic process using this data (1).
05). After the completion of the arithmetic processing, the arithmetic result is written in the arithmetic result storage address area of the memory 2, the arithmetic completion report signal 55 is output to the CPU 1 (106), and the control right of the address / data bus 50 is returned to the CPU 1. By following the above procedure, the coprocessor 3 can access the memory 2, and by storing the program data and the operation result in the memory 2, the CPU 1 can perform its own operation without being aware of the operation of the coprocessor 3. Enables continuation of arithmetic processing.

[0011]

According to the present invention, in a configuration in which an arithmetic coprocessor is added to a CPU having a memory, connection of the coprocessor can be performed easily and at low cost without increasing the number of pins used by the CPU. Also, by storing the contents of the arithmetic processing of the coprocessor in the memory, the coprocessor can effectively use the address / data bus to perform arithmetic processing when the frequency of the memory bus is low without the CPU being aware of the processing of the coprocessor. Can be performed, and the performance of the entire apparatus can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a comparison of relative performance and a transition of an operation in a configuration in which an arithmetic coprocessor is not added and in a configuration in which a coprocessor is added according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Memory, 3 ... Operation coprocessor, 4
... I / O device, 10 ... Memory control unit in CPU1, 1
DESCRIPTION OF SYMBOLS 1 ... Memory access frequency determination counter, 12 ... Bus release flag, 30 ... Memory control unit in coprocessor 3, 31 ...
Selector / arbiter, 32 ... operation unit in coprocessor 3,
50 ... address / data bus, 52 ... memory control signal,
53 ... bus release signal, 54 ... coprocessor dedicated access signal, 55 ... operation completion report signal, 56 ... memory control signal, 57 ... memory control signal, 59 ... bus release signal

Continued on the front page (72) Inventor Yama ▲ Saki ▼ Tsutomu Horiyamashita, Hadano-shi, Kanagawa Prefecture Within Hitachi Information Technology Co., Ltd. (72) Inventor Hidetada Fukunaka 810 Shimo-Imaizumi, Ebina-shi, Kanagawa Hitachi, Ltd. Office Systems Division

Claims (3)

[Claims]
1. An information processing apparatus comprising a memory and a CPU, wherein a coprocessor for arithmetic processing (hereinafter referred to as a coprocessor) is connected to an address / data bus between the CPU and the memory. An information processing apparatus characterized by the above-mentioned.
2. An information processing apparatus according to claim 1, wherein said CPU determines, based on a frequency of memory access, a determination to instruct a coprocessor to execute an arithmetic processing request due to an increase in arithmetic processing load. apparatus.
3. The information processing device according to claim 1, wherein a memory on a shared bus is used for data transmission and reception between the CPU and the coprocessor for relaying data transmission and reception. An information processing apparatus characterized by being able to perform processing without being aware of the information and to improve the performance of the apparatus.
JP9095530A 1997-04-14 1997-04-14 Information processor Pending JPH10289120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9095530A JPH10289120A (en) 1997-04-14 1997-04-14 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9095530A JPH10289120A (en) 1997-04-14 1997-04-14 Information processor

Publications (1)

Publication Number Publication Date
JPH10289120A true JPH10289120A (en) 1998-10-27

Family

ID=14140119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9095530A Pending JPH10289120A (en) 1997-04-14 1997-04-14 Information processor

Country Status (1)

Country Link
JP (1) JPH10289120A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002312163A (en) * 2001-04-17 2002-10-25 Denso Corp Information processor and information processing method
JP2008191949A (en) * 2007-02-05 2008-08-21 Nec Corp Multi-core system, and method for distributing load of the same
JP2010050970A (en) * 2008-08-22 2010-03-04 Arm Ltd Device and method of communicating between central processing unit and graphics processing unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002312163A (en) * 2001-04-17 2002-10-25 Denso Corp Information processor and information processing method
JP2008191949A (en) * 2007-02-05 2008-08-21 Nec Corp Multi-core system, and method for distributing load of the same
JP2010050970A (en) * 2008-08-22 2010-03-04 Arm Ltd Device and method of communicating between central processing unit and graphics processing unit
US8675006B2 (en) 2008-08-22 2014-03-18 Arm Limited Apparatus and method for communicating between a central processing unit and a graphics processing unit

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