JPH1011368A - Serial data receiving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To write only data inside a frame without writing error data in FIFO by providing a control part, etc., for controlling a serial data receiving part, a writing control signal generating part and a buffer memory. SOLUTION: When an error occurs by a certain reason and a write signal L including error data is generated, the serial data receiving part 2 outputs a coding error signal n. The writing control signal generating part 4 inputs the write signal L and the coding error signal n and generates a writing control signal L1 obtained by removing an error signal from the write signal L. FIFO 5 inputs parallel data m from the serial data receiving part 2 based on the writing control signal L1 so as to store it. That is, the writing control signal L1 does not include the error signal so that FIFO 5 stores only data within a frame period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a serial data receiving apparatus, and more particularly to a serial data receiving apparatus that does not write error data to a buffer memory.

[0002]

2. Description of the Related Art Conventionally, a serial interface is used for communication between a microcomputer and its peripheral devices or between a microcomputer and another microcomputer. In this serial interface, the serial transmission device converts parallel data representing one data or a data group composed of a plurality of codes in parallel and into serial data arranged in time series, and converts this serial data. The data is transmitted to the serial data receiving device through one transmission path. The serial data receiving device converts the serial data into parallel signals, that is, parallel data. As shown in FIG. 15, transmission and reception of serial data are performed by connecting a serial data transmitting device and a serial data receiving device via a data transfer path such as a wire cable or an optical fiber cable.

FIGS. 12 and 13 show a conventional serial data transmitting device 51 and a serial data receiving device 21.
Are respectively shown. The serial data transmitting device 51 has the configuration shown in FIG.
2, the control unit 52, the FIFO 54, the oscillator 5
3. It is composed of a transmitter 55. The serial data transmission device 51 receives parallel data a output from an input device 56 such as a host or a scanner. The control unit 52 generates control signals b, c, and d for writing the parallel data a input from the input device 56 into the FIFO 54, respectively. The FIFO 54 stores the parallel data a from the input device 56 according to the control signals c and d output from the control unit 52. Subsequently, the transmitter 55 outputs a read signal f for inputting the parallel data h from the FIFO 54 to the FIFO 54,
While inputting the parallel data h from the FIFO 54,
The input parallel data h is converted into serial data i. The transmitter 55 also performs data conversion such as 8B / 10B conversion. The oscillator 53 outputs the transfer timing reference clock g to the FIFO 54 and the transmitter 55. Here, assuming that the parallel data a input from the input device 56 has n bits, the transmitter 55 needs to transfer the converted serial data i at a frequency n times the frequency of reading the parallel data h from the FIFO 54. is there. Therefore, the clock of this transfer timing is generated by the PLL using the reference clock g input from the oscillator 53.

As shown in FIG. 13, in a conventional serial data receiving device 21, a receiver 22 converts an input serial code i into n-bit parallel data m. The FIFO 24 temporarily stores the parallel data m output from the receiver 22. Oscillator 23
Outputs the reference clock j to the receiver 22. The control unit 26 reads out the parallel data q stored in the FIFO 24 and outputs the parallel data q to the output device 27.
Outputs p and r. The output device 27 is a host or a printer. In the serial data receiving device 21, the parallel data m converted by the receiver 22 is
In addition to generating a write clock k for writing to the FO 24 and generating a write signal L, conversion of received serial data into parallel data, data conversion such as code conversion, and an error signal n indicating detection of coding violation Is generated. Further, the serial data receiving device 21 needs to generate a timing clock synchronized with the transferred serial data. This timing clock is a reference clock j input to the receiver 22.
And the input serial data to generate a PLL. In the serial data receiving device 21 or the serial data transmitting device 51 configured to generate a timing clock by such a PLL, the serial data receiving device 21
It is necessary to generate a timing clock using the data input on the side. This is because when there is no data to be transmitted on the serial data transmitting device 51 side, the serial data receiving device 21 cannot always generate a timing clock in a state where the serial data transmitting device 51 always outputs a signal of a constant level. You have to keep sending some code. Therefore, such a serial data transmitting device 51 is normally configured to transfer an idling code, which is a special code for indicating an idling state, when there is no data to be transferred.

[0005] In such a serial interface, it is necessary to be able to specify where and how the code sequentially input to the serial data receiving device 21 represents one data or data group. Therefore, in the serial data transmission device 51, data transfer is performed using frames. A frame is sandwiched between a special code representing the beginning of the frame (hereinafter, referred to as “start code S”) and a special code representing the end of the frame (hereinafter, referred to as “stop code E”). A set of codes that have been created. As described above, in the serial data transmission device 51, as shown in FIG. 14, a frame which is a set of data D sandwiched between a start code S indicating the start of a frame and a stop code E indicating the end of the frame is used. To transfer data. Therefore, in the transmission / reception of serial data, the idling code I indicating idling described above is transferred during a period in which it is not necessary to transmit data between frames.

Normally, the receiver 2 of the serial receiving device 21
When the idling code I indicating idling is transmitted, data corresponding to the idling code I is not written in the FIFO 24, and only when other codes are transmitted, the data corresponding to the code is transmitted. The data is stored in the FIFO 24. Therefore, receiver 2
2 sets the write signal L to HI and outputs it to the FIFO 24 only when data other than the idling code is transferred, as shown in FIG.

[0007]

However, when an error occurs for some reason during the transfer of serial data, a code other than the idle code is transferred during the idle period, and the serial data receiving device 21 receives this error data. , Serial data receiving device 21
As shown in FIG. 11, the receiver 22 outputs the write signal L corresponding to the error data to the FIFO 24, decodes the error data, and stores the error data in the FIFO 24. For this reason, even if no error occurs during data transfer during the frame transfer period, erroneous data is additionally written in the FIFO 24 when an error occurs during the previous idle code transfer. Will be. When using the data in the FIFO 24 storing the error data, it is necessary to perform some sort of error data removal processing after reading the data from the FIFO 24.

The present invention has been made in view of the above points, and has as its object to provide a serial data receiving apparatus capable of writing only data in a frame without writing error data to a FIFO. Aim.

[0009]

In order to achieve the above-mentioned object, the invention according to claim 1 converts input serial data into parallel data and stores the parallel data in a buffer memory at a transfer timing based on a reference clock. A serial data receiving unit that generates and outputs a write clock, a write signal, and a coding error signal; an oscillation unit that outputs the reference clock to the serial data receiving unit; A write control signal generating unit that removes a coding error from the write signal based on the coding error signal and generates a write control signal; and a buffer that inputs parallel data from the serial data receiving unit based on the write control signal. A memory and the serial data receiving unit And a serial data receiving apparatus and a control unit for controlling said buffer memory and the write control signal generating unit.

According to a second aspect of the present invention, in the serial data receiving apparatus according to the first aspect, the serial data receiving apparatus includes the write control signal generation unit including an inverting circuit and an AND circuit.

According to a third aspect of the present invention, the input serial data is converted into parallel data, the parallel data is output to a buffer memory at a transfer timing based on a reference clock, and a write clock and a write signal are generated. A serial data receiving unit for outputting, an oscillating unit for outputting the reference clock to the serial data receiving unit, and a write for removing a coding error from the write signal generated by the serial data receiving unit and generating a write control signal A control signal generator, a buffer memory that inputs parallel data from a serial data receiver based on the write control signal, and a controller that controls the serial data receiver, the write control signal generator, and the buffer memory. Serial data receiving device with

According to a fourth aspect of the present invention, in the serial data receiving apparatus according to the third aspect, a combination circuit for inputting parallel data output from a serial data receiving section and a negative feedback signal from a D flip-flop; A D flip-flop that inputs a signal output from the combinational circuit and a write clock; an OR circuit that inputs an output signal of the D flip-flop and an output signal of the combinational circuit; an output signal of the OR circuit and a write signal And a AND circuit that generates a write control signal by inputting a write control signal.

According to a fifth aspect of the present invention, in the serial data receiving apparatus of the fourth aspect, a start code detecting comparator for inputting parallel data output from the serial data receiving section and detecting a start code of a frame, A comparator for detecting a stop code of a frame by inputting parallel data output from a serial data receiving unit, a negative feedback signal from a D flip-flop and the comparator for detecting the start code or the comparator for detecting the stop code. An AND circuit that outputs a logical product of the signal and an output signal from
A serial data receiving device including a write control signal generation unit including an OR circuit that outputs a logical sum of an output signal from the start code detection comparator or the stop code detection comparator and an output signal of the AND circuit; And

According to a sixth aspect of the present invention, in the serial data receiving apparatus according to the fourth aspect, a start code detecting comparator for inputting parallel data output from the serial data receiving section and detecting a start code of a frame, A stop code detection comparator that detects the stop code of the frame by inputting the parallel data output from the serial data receiving unit, and an idling code detection that detects the idling code by inputting the parallel data output from the serial data receiving unit AND of the negative feedback signal from the D flip-flop, the output signal from the idling code detection comparator, and the output signal from the start code detection comparator or the stop code detection comparator And a write control signal generation unit configured to include an AND circuit that outputs a logical sum of an output signal from the start code detection comparator or the stop code detection comparator and an output signal of the AND circuit. Serial data receiving device.

[0015]

Embodiments of the present invention will be described below. The invention described in claim 1 will be described based on the embodiment of FIGS. 1, 2 and 3. First, the serial data receiving device 1 will be described. The serial data receiving device 1
It comprises a serial data receiving section 2, an oscillator 3, a write control signal generating section 4, a FIFO 5, and a control section 6.

Next, each component will be described. The oscillator 3 outputs a reference clock j to the serial data receiving unit 2. The serial data receiving unit 2 receives the serial data i transmitted from the serial data transmitting device,
It is converted into bit parallel data m. Further, in addition to converting the serial data i into parallel data m, the serial data receiving unit 2 generates a write clock k and a write signal L for writing the converted parallel data m into the FIFO 5, and performs code conversion. Coding error signal n indicating data conversion and detection of coding violation
Is generated. The write control signal generator 4 receives the coding error signal n and the write signal L from the serial data receiver 2 and stores parallel data m from the serial data receiver 2 only when no coding error has occurred. The write signal L1 is generated, and the write signal L1 is output to the FIFO5. The details of the write control signal generator 4 will be described later. FIFO5
Receives parallel data m from the serial data receiving unit 2 based on a write clock k output from the serial data receiving unit 2 and a write control signal L1 output from the write control signal generating unit 4, Data m is temporarily stored. The control unit 6 outputs a control signal o, a control signal p, and a control signal r for reading out the parallel data q not including the error data stored in the FIFO 5 to the output device 7. The output device 7 is controlled by the control signal r output from the control unit 6 to control the FIFO.
5 to read and output the parallel data q. The output device 7 includes a host or a printer.

Next, the operation of the serial data receiving apparatus 1 according to the present invention will be described. The serial data i transmitted from the serial data transmitting device is input to the serial data receiving unit 2 of the serial data receiving device 1 and is converted into parallel data m. As mentioned above,
The serial data receiving device 1 needs to generate a timing clock k synchronized with the transferred serial data i. Therefore, the serial data receiving unit 2 uses the reference clock j oscillated from the oscillator 3 and the input serial data i to execute the serial data i by the PLL.
Is generated in synchronization with the timing clock k. Further, the serial data receiving unit 2 detects the serial data i based on the timing clock k, and outputs the start code S
Is detected, until the stop code E indicating the end of the frame is detected as one frame.
Here, the serial data receiving unit 2 outputs the start code S
To HI during the period of the stop code E and LOW during the other periods. As shown in FIG. 3, an error may occur for some reason, and the write signal L may become HI during a period other than the frame.
That is, the write signal L including the error data is generated. At this time, the serial data receiving section 2 outputs a coding error signal n. Write control signal generator 4
Receives the write signal L including the error and the coding error signal n, and generates a write control signal L1 obtained by removing the error signal from the write signal L. FIF
O5 inputs and stores parallel data m from the serial data receiving unit 2 based on the write control signal L1 generated by the write control signal generating unit 4. That is, since the write control signal L1 does not include an error signal,
The IFO 5 stores only data within a frame period.
The parallel data q stored in the FIFO 5 is output to the output device 7 by the control signal o and the control signal p output from the control unit 6. The output device 7 is controlled by a control signal r from the control unit 6.

Next, the second aspect of the present invention will be described with reference to FIG. In the serial data receiving device according to the second aspect, the components other than the write control signal generating unit 4 are the same as those of the embodiment of the first aspect of the present invention, and therefore the description thereof is omitted. The write control signal generator 4 of the serial data receiving device according to claim 2 includes: an inverting circuit 8;
And an AND circuit 9. The inversion circuit 8 receives the coding error signal n output from the serial data receiving unit 2 and outputs an inverted signal of the coding error signal n. The AND circuit 9 receives the write signal L output from the serial data receiving unit 2 and the inverted signal of the coding error signal n output from the inverting circuit 8, and writes the logical sum of these two inputs into the write control signal L1.
And outputs it to FIFO5. With such a configuration,
The timing of each signal when a coding error is detected during the idling period is as shown in FIG. 3, and the write control signal L1, which is valid only during the frame period, is FI
Output to FO5. Therefore, even if a coding error is detected during the idling period, the error data is not written to the FIF05.

Next, the third aspect of the present invention will be described with reference to FIG. In the serial data receiving device 11 according to the third aspect, the components other than the write control signal generating unit 14 are the same as those of the embodiment of the first aspect of the present invention, and thus the description thereof is omitted. As shown in FIG. 4, the write control signal generation unit 14 receives the write clock k, the write signal L, and the parallel data m from the serial data reception unit 12, generates a write control signal L2, and
Output to

Next, the operation of the serial data receiving device 11 will be described. The write control signal generator 14 receives the parallel data m output from the serial data receiver 12, detects a start code S and a stop code E from the parallel data m,
A write control signal L2 that is valid only during the period between the start code S and the stop code E is generated and output to the FIFO 15.

Next, the fourth and fifth aspects of the invention will be described with reference to the embodiments of FIGS. As shown in FIG. 5, the write control signal generator 14 includes a combinational circuit 30, a 1-bit D flip-flop 31, a two-input OR circuit 32, and a two-input AND circuit 33. One embodiment of the combinational circuit 30 is shown in FIG. The combination circuit 30 includes a start code detection comparator 34 and a stop code detection comparator 3.
5, 2-input AND circuit 36, 2-input OR circuit 3
And 7. The start code detection comparator 34 receives the parallel data m from the serial data receiving unit 12 and outputs a high level when it matches the start code S representing the start of a frame, and outputs a low level during other periods. It is a comparator. The stop code detection comparator 35 receives the parallel data m from the serial data receiving unit 12, outputs a high level when the stop data E matches the stop code E indicating the end of the frame, and outputs a low level during other periods. It is a comparator. Here, Table 1 shows the combinational circuit 3
The relationship between the parallel data m input to 0 and the negative feedback signal SIG1 of the D flip-flop 31 and SIG0 output by the combinational circuit 30 is shown.

[0022]

[Table 1]

Here, A is the parallel data m input to the start code detection comparator 34, B is the parallel data m input to the stop code detection comparator 35, SOF is the start code, EOF is the stop code, X Represents an arbitrary value. As is clear from Table 1, when the combinational circuit 30 having the configuration shown in FIG. 6 is used, the relationship between the data is as shown in FIG. That is, the write clock k, the parallel data m, and the write signal L are input by setting the logical sum of SIG1 and SIG0 and the logical product of the logical sum and the write signal L only during the frame period as the write control signal L2. When the FIF015
Is corrected so that the write control signal L2 for writing data to the memory is output only during the frame period.
15 stores only the data in the frame. Further, when generating the write control signal L2,
Since the coding error signal n is not used, it is also effective when an error other than a coding error occurs.

Next, FIG. 4 and FIG.
Will be described based on the embodiment of FIG. FIG. 8 shows another embodiment of the combinational circuit according to the fourth and fifth aspects of the present invention. The combination circuit 40 includes a start code detection comparator 44, a stop code detection comparator 45, an idling code detection comparator 48, a three-input AND circuit 46, and a two-input OR circuit 47. The idling code detection comparator 48 is connected to the serial data receiving unit 12.
Is a comparator that inputs the parallel data m output from the controller, outputs a high level when the data is other than the idling code, and outputs a low level when the data matches the idling code. Further, the start code detection comparator 34 receives the parallel data m from the serial data receiving unit 12 and outputs a high level when the parallel data m matches the start code S indicating the beginning of the frame.
In other periods, the comparator outputs a low level. The stop code detection comparator 45 receives the parallel data m from the serial data receiving unit 12, outputs a high level when the stop data E matches the stop code E indicating the end of the frame, and outputs a low level during other periods. It is a comparator. Here, in Table 2,
The relationship between the parallel data m input to the combination circuit 40 and the output signal SIG2 of the D flip-flop 31 and the SIG3 output from the combination circuit 40 are shown.

[0025]

[Table 2]

Here, A is the parallel data m input to the start code detection comparator 44, B is the parallel data m input to the stop code detection comparator 45, SOF is the start code, EOF is the stop code, X Represents an arbitrary value. As shown in FIG. 9, when the write clock k, the parallel data m, and the write signal L are input, the combination control circuit L3 having the configuration shown in FIG. 8 outputs the write control signal L3 for writing to the FIF015 only during the frame period. Therefore, even when an error occurs during the idling period, only the parallel data m within the frame period is stored in the FIF015. Since the coding error signal n is not used for generating the write control signal L3 in this case, it is effective even when an error other than a coding error occurs.

As shown in FIG. 10, even when an error occurs in the stop code E indicating the end of the frame, the data is written following the detection of the idling code, so that the stop code indicating the end of the next frame is obtained. Does not continue to write the idling code to the FIFO until the detection of is detected, and the overflow of the FIF015 does not occur.

[0028]

As described above, according to the first aspect of the present invention, even when an error occurs during idle code transfer, only parallel data within a frame period can be stored in the FIFO. .

According to the second aspect of the present invention, only data during a frame period can be written in the FIFO even when a coding error occurs during the idle code transfer.

According to the third aspect of the present invention, even when a coding error occurs during the idle code transfer, only the parallel data within the frame period is transmitted to the FI.
The serial data receiving device that can be written in the FO can have a simple configuration and can be realized at low cost.

According to the fourth aspect of the present invention, when an error occurs, not only a coding error during idle code transfer, but only parallel data within a frame period can be written in the FIFO.

According to the fifth aspect of the present invention, when an error occurs, not only a coding error during the idle code transfer, but only parallel data within a frame period can be written into the FIFO, and serial data reception can be performed. The apparatus can have a simple configuration and can be realized at low cost.

According to the sixth aspect of the present invention, when an error occurs during transmission of an idling code or a stop code, not only a coding error but also serial data which can write only data within a frame period into a FIFO. The receiving device can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a diagram showing a serial data receiving apparatus according to the first embodiment.

FIG. 2 is a diagram illustrating a write control signal generation unit of the serial data receiving device according to the first embodiment;

FIG. 3 is a timing chart showing the timing of each signal according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a serial data receiving apparatus according to the third aspect of the present invention.

FIG. 5 is a diagram showing a write control signal generation unit of the serial data receiving device according to the third aspect of the present invention.

FIG. 6 is a diagram showing a combinational circuit of a write control signal generation unit of the serial data receiving device according to the fourth aspect of the present invention.

FIG. 7 is a timing chart showing the timing of each signal according to the third aspect of the present invention.

FIG. 8 is a diagram showing a write control signal generation unit of the serial data receiving device according to the invention of claim 6;

FIG. 9 is a timing chart showing the timing of each signal of the invention according to claim 6;

FIG. 10 is a timing chart showing the timing of each signal of the invention according to claim 6;

FIG. 11 is a timing chart showing the timing of each signal when an error occurs.

FIG. 12 is a diagram illustrating a conventional serial data transmission device.

FIG. 13 is a diagram illustrating a conventional serial data receiving device.

FIG. 14 is a timing chart illustrating a relationship among a write clock, a write signal, and a frame.

FIG. 15 is a diagram illustrating a configuration of a conventional serial communication.

[Explanation of symbols]

 1, 11, 21 Serial data receiving device 2, 12, 22 Serial data receiving unit 3, 13, 23, 53 Oscillator 4, 14 Write control signal generating unit 5, 15, 24 Buffer memory 6, 16, 26, 52 Control unit 7, 17, 27 output device 8 inversion circuit 9, 33, 36, 46 AND circuit 30, 40 combination circuit 31 D flip-flop 32, 37, 47 OR circuit 34, 44 start code detection comparator 35, 45 stop code detection Comparator 48 Idling code detection comparator 51 Serial data transmitting device 54 FIFO 55 Transmitter 56 Input device.

Claims (6)

[Claims] 1. A method for converting input serial data into parallel data, outputting the parallel data to a buffer memory at a transfer timing based on a reference clock, and generating and outputting a write clock, a write signal, and a coding error signal. A serial data receiving unit, an oscillating unit that outputs the reference clock to the serial data receiving unit, and a coding control that removes a coding error from the write signal based on the coding error signal generated by the serial data receiving unit, and performs write control. A write control signal generator that generates a signal, a buffer memory that inputs parallel data from the serial data receiver based on the write control signal, the serial data receiver, the write control signal generator, and the buffer memory. Control to control The serial data receiving apparatus characterized by comprising and. 2. The serial data receiving apparatus according to claim 1, further comprising: the write control signal generating section including an inverting circuit and an AND circuit. 3. A serial data receiver for converting input serial data into parallel data, outputting the parallel data to a buffer memory at a transfer timing based on a reference clock, and generating and outputting a write clock and a write signal. An oscillation unit that outputs the reference clock to the serial data reception unit, a write control signal generation unit that removes a coding error from the write signal generated by the serial data reception unit, and generates a write control signal; A buffer memory that inputs parallel data from a serial data receiving unit based on the write control signal, and a control unit that controls the serial data receiving unit, the write control signal generation unit, and the buffer memory. Serial data receiving device. 4. The serial data receiving device according to claim 3, wherein a combinational circuit for inputting parallel data output from the serial data receiving unit and a negative feedback signal from a D flip-flop, and an output from the combinational circuit. A D flip-flop for inputting a signal and a write clock, an OR circuit for inputting an output signal of the D flip-flop and an output signal of the combination circuit, and a write control for inputting an output signal of the OR circuit and a write signal A serial data receiving device, comprising: a write control signal generation unit including an AND circuit that generates a signal. 5. A serial data receiving device according to claim 4, wherein a start code detecting comparator for detecting a start code of a frame by inputting parallel data output from the serial data receiving unit, and outputting the parallel data from the serial data receiving unit. And a negative code signal from a D flip-flop and an output signal from the start code detection comparator or the stop code detection comparator. A write control signal including an AND circuit that outputs a logical product, and an OR circuit that outputs a logical sum of an output signal from the start code detection comparator or the stop code detection comparator and an output signal of the AND circuit Include generator The serial data receiving apparatus, characterized by. 6. A serial data receiving device according to claim 4, wherein a start code detecting comparator for detecting a start code of a frame by inputting parallel data output from the serial data receiving unit, and outputting the data from the serial data receiving unit. A stop code detection comparator for detecting a stop code of a frame by inputting parallel data to be input, an idling code detection comparator for inputting parallel data output from a serial data receiving unit and detecting an idling code, and a D flip-flop An AND circuit that outputs a logical product of a negative feedback signal from the amplifier, an output signal from the idling code detection comparator, and an output signal from the start code detection comparator or the stop code detection comparator, A write control signal generator configured to include an OR circuit that outputs a logical sum of an output signal from the start code detection comparator or the stop code detection comparator and an output signal of the AND circuit. Serial data receiving device.