JPH1013393A - Transmission method for digital signal, encoder and decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To send data without error without transmission of a clock through other line by encoding data into a code consisting of a data part and a synchronization part in the case of serial transmission of data between electronic devices. SOLUTION: An electronic device 1 is provided with an encoder 4, and electronic device 2 is provided with an encoder 5. Then data of the electronic device 1 is encoded into a code consisting of a data part and a synchronization part. An output of the encoder 4 is received by a decoder 2 of the electronic device 2 via a data line 3. The decoder 5 decodes the data from the code consisting of the data part and the synchronization part. Thus, in the case of sending data between the electronic device 1 and the electronic device 2, the data are encoded into a code consisting of the data part and the synchronization part. Thus, it is not sent to send a clock signal through other signal line by sending data encoded into the code and it is not required to recover the clock signal by using a PLL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission method suitable for performing data communication between a remote controller and an electronic device when, for example, the electronic device is controlled by a remote controller, and And an encoder and a decoder that can be used when data is communicated by such a transmission method.

[0002]

2. Description of the Related Art For example, when controlling an electronic device using a wired remote commander, data is serially transmitted between the remote commander and the electronic device. As described above, when data is transmitted serially between electronic devices, conventionally, data and a clock are transmitted, and data is taken in while being synchronized with the clock.

That is, in FIG. 17, when data is transmitted from the electronic device 101 to the electronic device 102, a data line 103 for transmitting data and a clock are transmitted between the electronic device 101 and the electronic device 102. And a clock line 104 for performing the operation. Data is sent from the electronic device 101 to the electronic device 102 via the data line 103, and data is sent from the electronic device 101 to the electronic device 10 via the clock line 104.
2 is sent a clock.

[0006] The electronic device 102 is provided with a register 105. Data sent from the electronic device 101 via the data line 103 is stored in the register 105 of the electronic device 102.
The clock supplied from the electronic device 101 via the clock line 104 and supplied from the electronic device 101 is supplied to the clock input terminal of the register 105 of the electronic device 102. In the register 105 of the electronic device 102, the clock line 1
The data transmitted via the data line 103 is taken in at a timing based on the clock transmitted via the data line 04.

For example, from the electronic device 101 to the electronic device 10
18A, data is sent via the data line 103 as shown in FIG. 18A, and
The clock is being sent as shown in. In the register 105 of the electronic device 102 that receives this data,
8B is received, and at the rising edge of the clock, the data shown in FIG. 18A is captured.

As described above, conventionally, when data is serially transmitted between electronic devices, a data line and a clock line are provided, and data and a clock are transmitted. this is,
This is because, when data is transmitted, simply transferring the data serially makes it impossible to take in data at the correct timing when data of “1” or data of “0” continues for a long time. As described above, the electronic device 101 and the electronic device 1
02, a data line 103 and a clock line 104 are provided to transmit data and clock.
Even if the data of "1" or "0" continues for a long time,
Data can be transferred accurately.

However, when the data and the clock are transmitted in this manner, the electronic device 101 and the electronic device 1 are not transmitted.
02 must be connected by at least two lines of the data line 103 and the clock line 104. Therefore, as shown in FIG.
And the electronic device 112 are connected only by the data line 113, and the clock is reproduced by the PLL.

That is, in FIG. 19, a data line 113 is provided between an electronic device 111 and an electronic device 112. The electronic device 112 includes a register 114 and a PLL 1
15 are provided. From the electronic device 111 to the electronic device 11
2, data is transmitted via the data line 113.
This data is supplied to the data input terminal of the register 114 and to the PLL 115. PLL11
At 5, the clock is recovered from the data sent via the data line 113. This clock is the register 1
14 clock input terminals. Electronic equipment 112
The register 114 receives the data transmitted via the data line 113 at a timing based on the clock reproduced by the PLL 115.

[0009]

As described above, when the PLL 115 is provided in the electronic device 112 on the receiving side and the clock is reproduced by the PLL 115, it is not necessary to provide a clock line. However, like this, the PLL
If the clock is reproduced by using a PLL, it is necessary to provide a PLL on the receiving side, which increases the hardware. Also, even if the clock is reproduced by the PLL as described above,
If the data of “1” or the data of “0” continues for a very long time, the clock of the PLL may deviate from the original clock, and erroneous data may be captured.

Further, even when data of "1" or data of "0" continues for a very long time, a synchronization pattern is inserted into the data at regular intervals so that the PLL clock does not deviate from the original clock. It is possible to do. However,
When such a synchronization pattern is inserted into data and transmitted, the communication speed is reduced because a signal pattern is inserted. Also, if you insert a pattern for synchronization,
A pattern for synchronization is also sent during a period in which no data exists.

Accordingly, an object of the present invention is to provide a digital signal transmission method that does not require a clock line when transmitting data serially between electronic devices, does not increase hardware, and does not cause data transmission errors. A transmission method and an encoder and a decoder are provided.

[0012]

According to the present invention, one code comprises a data portion having a first polarity and a synchronization portion, and the other code comprises a data portion having a second polarity and a synchronization portion. This is a data transmission method of a digitized digital signal.

According to the present invention, there is provided an encoder for encoding a code including a data portion having a first polarity and a synchronization portion and a code including a data portion having a second polarity and a synchronization portion. A first signal generating means for generating a signal of one polarity, a second signal generating means for generating a signal of a second polarity, and a data part according to a length of the data part and a length of the synchronizing part. And the output of the first signal generating means,
A switching means for switching and outputting the output of the second signal generation means.

According to the present invention, in a decoder for decoding a code composed of a data part of a first polarity and a synchronization part, and one code composed of a data part and a synchronization part of a second polarity, A measuring means for measuring the length of one or the other polarity of the transmitted code based on the timing of the synchronization part of the transmitted code, and a measuring means for measuring the length of one or the other polarity of the transmitted code. And a judging means for judging the transmitted code.

According to the present invention, in a decoder for decoding a code composed of a data part of a first polarity and a synchronization part, and one code comprising a data part of a second polarity and a synchronization part, The decoder is provided with integrating means for integrating the obtained code, and data taking means for taking in the output of the integrating means at the timing of the synchronization section of the transmitted code.

When data is serially transmitted between electronic devices, the data is encoded into a code consisting of a data portion and a synchronization portion.
Data can be transmitted without errors. In addition, encoding can be performed only by adding a synchronization section to the data section, and decoding can be performed only by measuring, for example, a low-level period immediately before rising of data, so that the encoder and decoder are not complicated and hardware does not increase. .

[0017]

Embodiments of the present invention will be described below with reference to the drawings. According to the present invention, as in the case of controlling an MD player with a wired remote commander,
Used for serial transmission of data between two electronic devices.

In FIG. 1, an electronic device 1 and an electronic device 2 are connected via a data line 3. The electronic device 1 is, for example, a remote commander, and the electronic device 2 is, for example, an MD player controlled by the remote commander.

The electronic device 1 is provided with an encoder 4, and the electronic device 2 is provided with a decoder 5.
The data of the electronic device 1 is encoded by the encoder 4 into a code including a data section and a synchronization section. Encoder 4
Is received by the decoder 5 of the electronic device 2 via the data line 3. The decoder 5 decodes the data from the code including the data part and the synchronization part.

As described above, according to the present invention, when data is transmitted between the electronic device 1 and the electronic device 2, the data is encoded into a code including the data portion and the synchronization portion. If the data is transmitted after being encoded into a code composed of the data section and the synchronization section, there is no need to send a clock through another signal line, and it is not necessary to reproduce the clock using a PLL. The code composed of the data part and the synchronization part will be described in more detail.

FIGS. 2A and 2B show a code "0" and a code "1" used at the time of transmission in the present invention. As shown in FIG. 2A, reference numeral "0", after being held at a low level for a predetermined time T _1, a high level for a predetermined time T _2. As shown in FIG. 2B, reference numeral “1”
After being held at the high level for a predetermined time T _3, it becomes a predetermined time T ₄ by the low level and the predetermined time T ₅
Only high level.

Here, the low-level period T ₁ in the first half of the code “0” is a period obtained by combining the high-level period T ₃ of the code “1” and the low-level period T _{4 of the} code “1”. equal to the period T ₂ of the second half of the high level code "0", a period T ₅ of the second half of the high level of the code "1" are equal. The low-level period T ₁ of the code “0” is the code “1”.
Sufficiently longer than the period T ₄ of the low level. That is, the relation of _{T 1 = T 3 + T 4} T 2 = T 5 T 1> T 4.

As shown in FIG. 2A, the minimum communication unit time T _Unit0 code "0" is a _{T unit0 = T 1 + T 2} , as shown in Figure 2B, a minimum communication unit time T of the code "1" _unit1 is a _{T unit1 = T 3 + T 4} + T 5. Then, the minimum communication unit time T of the code “0”
_Unit0 is equal to the minimum communication unit time _{Tunit1 of} code "1", and has a relationship of _Tunit0 = _Tunit1 .

Such a code is formed based on the idea that a data section is transmitted with a synchronization section added.

That is, in the data part, "0" is at a low level,
“1” is a high-level signal. And the synchronization unit,
As shown in FIG. 3, and the low level period of the period t _11, a signal consisting of a high-level period of time t _12.

The code "0" is obtained by adding a synchronization section SY as shown in FIG. 3 to the low-level data section. That is, as shown in FIG. 4A, in the case of the code "0", the data unit DA0 is a low level for a predetermined time T _21. As shown in FIG. 4B, a predetermined time T ₁₁
When the synchronization unit SY which of consisting of low level period and the high-level period of the predetermined time T ₁₂ is added, as shown in FIG. 4C, the code of the code "0" is formed. Here, assuming that T ₂₁ + T ₁₁ = T ₁ T ₁₂ = T ₂ , the format is the same as the format of the code “0” shown in FIG. 2A.

The code “1” indicates a high-level data part.
A synchronization unit SY as shown in FIG. 3 is added.
That is, as shown in FIG. 5A, in the case of the code "1", the data unit DA1 is a high level for a predetermined time T _31. As shown in FIG. 5B, a predetermined time T
When the synchronization unit SY consisting of ₁₁ low-level period and the high-level period of the predetermined time T ₁₂ of is added, as shown in FIG. 5C, code of the code "1" is formed. Here, assuming that T ₃₁ = T ₃ T ₁₁ = T ₄ T ₁₂ = T ₅ , the format is the same as the format of the code “1” shown in FIG. 2B.

As described above, the data portions DA0 and DA1 in which the code “0” is at the low level and the code “1” is at the high level
2A and 2B by adding a synchronization unit SY composed of a low level for a predetermined time and a high level for a predetermined time.
Are formed as shown in FIG.

FIG. 6 shows the configuration of an encoder that generates such codes. In FIG. 6, reference numeral 31 denotes a shift register. The shift register 31 is supplied with data for transmission from an input terminal 32. The shift register 31 is shifted by a shift clock from the timer control circuit 40. The output of the shift register 31 is supplied to a terminal 34A of the switch circuit 34.

A low-level signal from a low-level signal generation circuit 35 is supplied to a terminal 34 B of the switch circuit 34. A high-level signal from a high-level signal generation circuit 36 is supplied to a terminal 34C of the switch circuit 34. The switch circuit 34 is controlled by the timer control circuit 40. An output terminal 41 is derived from the switch circuit 34.

For the timer control circuit 40, a data section timer 37, a low level period timer 38, and a high level period timer 39 are provided. Data unit timer 37, the period of the data portion (the period T ₂₁ and T ₃₁ in FIG. 4 and FIG. 5)
Is measured. Low-level period timer 38 measures the period of the low level of the synchronization unit (period T ₁₁ in FIG. 4 and FIG. 5). The high-level period timer 39 measures a high-level period (period T ₁₂ in FIGS. 4 and 5) of the synchronization unit.

The timer control circuit 40 performs a process as shown in the flowchart of FIG. As a result, the signal encoded as described above is output from the output terminal 41.

That is, as shown in FIG. 7, first, the switch circuit 34 is set to the terminal 34A side (step ST).
1). Then, the data section timer 37 is set (step ST2).

When the switch circuit 34 is set to the terminal 34A, the data from the shift register 31 is output to the output terminal 4A.
1 is output.

It is determined from the output of the data section timer 37 whether or not the output period of the data section has elapsed (step ST3). When the output period of the data section has elapsed, the data section timer 37 is cleared (step ST4), and the switch circuit 34 is set to the terminal 34B side (step ST4).
5). Then, the low level period timer 38 is set (step ST6).

When the switch circuit 34 is set to the terminal 34B side, a low level signal from the low level signal generation circuit 35 is output from the output terminal 41.

It is determined from the output of the low level period timer 38 whether or not the output period of the low level of the synchronization section has elapsed (step ST7). After the elapse of the low-level output period of the synchronization unit, the low-level period timer 38 is cleared (step ST8), and the switch circuit 34 sets the terminal 34C.
(Step ST9). Then, the high level period timer 39 is set (step ST1).
0).

When the switch circuit 34 is set to the terminal 34 C side, a high-level signal from the high-level signal generation circuit 36 is output from the output terminal 41.

It is determined from the output of the high-level period timer 39 whether or not the output period of the high level of the synchronizing section has elapsed (step ST11). When the high-level output period of the synchronization section has elapsed, the high-level period timer 39 is cleared (step ST12). Then, after one shift clock is sent (step ST13), step S13 is executed.
Returned to T1.

According to the above control, a low-level or high-level data portion is added with a low-level and high-level synchronizing section for a predetermined period of time. An encoded signal will be output.

Next, the decoding process of such a code will be described. Such a code is, for example, a low-level period immediately before a low-to-high transition point.
It can be decoded depending on whether it is longer than the low-level period of the latter half of the code “1”.

That is, as shown in FIG. 8, it is assumed that a code encoded as described above is input. This code is
“0”, “1”, “1”, “0”...

When such a code is input, at the time of decoding, the transition points t ₁₁ , t ₁₂ from low level to high level,
t _13, t ₁₄ ... is detected. Then, the length of the low level immediately before the high level change points t ₁₁ , t ₁₂ , t ₁₃ , t _14, ... From this low level is determined, whereby the data is decoded to “0” or “1”. .

[0044] At time t _11, the length L ₁₁ of the immediately preceding low level is longer than the period of the latter half portion of the low level by the symbol "1", is decoded to "0". At time t _12, since the immediately preceding low level length L ₁₂ is shorter than the period of the latter half portion of the low level by the symbol "1", is decoded to "1". At time t _13, the length L ₁₃ of the immediately preceding low level is shorter than the period of the latter half portion of the low level by the symbol "1",
Decoded to "1". At time t _14, the length L ₁₄ of the immediately preceding low level is longer than the period of the latter half portion of the low level by the symbol "1", it is decoded to "0".

FIG. 9 shows a decoder that performs decoding depending on whether the low-level period immediately before the transition point from the low level to the high level is longer than the low-level period of the latter half of the code “1”. This is an example.

In FIG. 9, received data is supplied to an input terminal 51. The received data is supplied to the falling edge detection circuit 53 while being supplied to the falling edge detection circuit 52. Rising edge detection circuit 52
And the output of the falling edge detection circuit 53 are supplied to the low level period measurement timer 54. The low-level period measurement timer 54 starts measurement at the output of the falling edge detection circuit 52 and ends measurement at the output of the rising edge measurement circuit 53.

The output of the low level period measurement timer 54 is supplied to comparators 55 and 56. Comparator 5
5 is supplied with the output of the code “1” measurement time generation circuit 57. The output of the code “0” measurement time generation circuit 58 is supplied to the comparator 56.

The reference time "1" measurement time generation circuit 57 sets the time (period T ₄ in FIG. 2B) corresponding to the low-level period immediately before the transition point from the low level to the high level in the case of the reference “1”. Is done. The time corresponding to the low-level period immediately before the low-level to high-level change point in the case of the code “0” is set in the code “0” measurement time generation circuit 58 (the period T ₁ in FIG. 2A). .

The outputs of the comparators 55 and 56 are supplied to a decision circuit 59. The determination circuit 59 determines the sign of the received data from the outputs of the comparators 55 and 56.

That is, the low-level period timer 54 measures the low-level period immediately before the transition point from the low level to the high level. The comparator 55 determines whether or not the low-level period immediately before the low-level to high-level transition point coincides with the low-level period immediately before the low-level to high-level transition point for the code “1”. Is detected. The comparator 56 determines whether or not the low-level period immediately before the low-level to high-level transition point matches the low-level period immediately before the low-level to high-level transition point in the case of code “0”. Is determined. The detection outputs of the comparators 55 and 56 are supplied to a judgment circuit 59.

From the output of the comparator 55, the judgment circuit 59 determines the low level immediately before the low-level to high-level transition point when the low-level period immediately before the low-level to high-level transition point is "1". If it is determined that the period matches the level period, it is decoded to “1”. Also, from the output of the comparator 56, if the low-level period immediately before the low-level to high-level transition point coincides with the low-level period immediately before the low-level to high-level transition point when the code is “0”. If it is determined, it is decoded to “0”.

FIG. 10 shows another example of the decoder. In the above-described example, decoding is performed depending on whether the low-level period immediately before the transition point from the low level to the high level is longer than the low-level period in the latter half of the code “1”. The decoding is performed by storing whether the low-level signal time of the received data is short or long in an integrating circuit including a resistor and a capacitor.

That is, in FIG. 10, the received data from the input terminal 61 is supplied to the clock input terminal of the D flip-flop 62, and the resistor 63 and the capacitor 64
Is supplied to an integrating circuit 65 composed of The output of the integration circuit 65 is supplied to the data input terminal of the D flip-flop 62.

At the rising edge of the received data, the D flip-flop 62 fetches the received data via the integration circuit 65. The integration circuit 65 stores the length of the low level period of the received data.

That is, as shown in FIG. 11, when a signal having a long low-level period (FIG. 11A) is input, the output of the integrating circuit 65 falls to a low level as shown in FIG. 11B. Therefore, as shown in FIG. 11C, when the output of the integrating circuit 65 is captured at the rising edge of the data, the captured data becomes low level. In contrast, FIG.
As shown in FIG. 2, a signal having a short low-level period (FIG. 12)
When A) is input, the output of the integration circuit 65 does not fall to a low level as shown in FIG. 12B. Therefore, as shown in FIG. 12C, when the output of the integration circuit 65 is captured at the rising edge of the data, the captured data becomes a high level.

As described above, in the integrating circuit 65, the low level period immediately before the data rises from the low level to the high level is stored, and the low level period immediately before the data rises from the low level to the high level is stored. If the period is long, the D flip-flop 62 takes in the low level. If the period of the low level immediately before the data rises from the low level to the high level is short, the high level is taken into the D flip-flop 62.

In the above example, only the binary data of the code "0" and the code "1" is transmitted.
Further, as shown in FIG. 13, a synchronization pattern may be sent. In FIG. 13, a period indicated by SYNC is a pattern for synchronization. The pattern for synchronization is set to be at the low level for a longer period of time than the low level period at code “0”. This pattern for synchronization can be used to notify the start of data transmission.

FIG. 14 shows an example in which data can be exchanged between the master electronic device and the slave electronic device. In FIG. 14, reference numeral 71 denotes a master electronic device, and reference numeral 72 denotes a slave electronic device. An encoder 73 is provided in the electronic device 71 on the master side. As the encoder 73, one having a configuration as shown in FIG. 6 is used. Further, the electronic device 71 on the master side is provided with a tri-state buffer 74 and a D flip-flop 75 for receiving data. The electronic device 72 on the slave side is provided with a decoder 77. Decoder 77
The one having the configuration as shown in FIG. 9 or FIG. 10 is used. Further, the electronic device 72 on the slave side is provided with a shift register 78 for data transmission and a resistor 79. The electronic device 71 on the master side and the electronic device 72 on the slave side are connected via a transmission line 80.

In such a configuration, not only data is transmitted from the master electronic device 71 to the slave electronic device 72, but also data is transmitted from the slave electronic device 72 to the master electronic device 71. Can be.

That is, when data is transmitted from the electronic device 71 on the master side to the electronic device 72 on the slave side, the data is encoded by the encoder 73 of the electronic device 71 on the master side.
The data is sent to the slave-side electronic device 72 via the transmission line 80. This data is decoded by the decoder 77 of the electronic device 72 on the slave side.

When data is transmitted from the electronic device 72 on the slave side to the electronic device 71 on the master side, data is output from the shift register 78 of the electronic device 72 on the slave side. The data from the shift register 78 is transmitted via a resistor 79 and a transmission line 80 to the electronic device 7 on the master side.
Sent to 1. Then, this data is taken in by the D flip-flop 75 of the electronic device 71 on the master side.

As described above, when data is transmitted from the slave-side electronic device 72 to the master-side electronic device 71, the tristate buffer 74 is set to the high impedance state for a period corresponding to the period of the data portion. As described above, when the tri-state buffer 74 is set to the high impedance state for the period corresponding to the period of the data portion, the D flip-flop 75 of the master electronic device 71 does not need to provide an encoder in the slave electronic device 72. ,
Can take encoded data.

That is, it is assumed that a high-level signal is output from the shift register 78 of the electronic device 72 on the slave side as shown in FIG. 15A. As shown in FIG. 15B, in the period T ₅₁ in the data unit, the tri-state buffer 74 is set to the high impedance state. Therefore, in the period T ₅₁ in the data unit, as shown in FIG. 15C, the signal from the shift register 78 (high level) is directly input to the D flip-flop 75 on the master side of the electronic device 71. In the period T ₅₂ in the synchronization section, the tri-state buffer 7
4 is driven. For this reason, the signal of the synchronizing unit which is at the low level for a predetermined period and at the high level for a predetermined period from the encoder 73 is input to the D flip-flop 75. Accordingly, as shown in FIG. 15C, the encoded code “1” is input to the D flip-flop 75.

As shown in FIG. 16A, assume that a low-level signal is output from the shift register 78 of the electronic device 72 on the slave side. As shown in FIG. 16B, in the data section period _T51 , the tristate buffer 74 is set to the high impedance state. Therefore, in the period T ₅₁ in the data unit, as shown in FIG. 16C, the shift register 7
The signal (low level) from 8 is directly input to the D flip-flop 75 of the electronic device 71 on the master side. In the period T ₅₂ in the synchronization section, the tri-state buffer 74 is driven. For this reason, the signal of the synchronizing unit, which is at the low level for a predetermined period and the high level for a predetermined period,
It is input to the D flip-flop 75. Therefore, FIG.
As shown in C, the encoded code “0” has been input to the D flip-flop 75.

[0065]

According to the present invention, when data is serially transmitted between electronic devices, the data is encoded into a code composed of a data portion and a synchronization portion, so that a clock need not be transmitted on another line. Data can be transmitted without error. Further, according to the present invention, encoding can be performed only by adding a synchronization section to the data section, and decoding can be performed only by measuring, for example, a low-level period immediately before data rises, so that the encoder and decoder are not complicated. , The hardware does not increase.

[Brief description of the drawings]

FIG. 1 is a block diagram used to describe an example of data transmission between electronic devices to which the present invention has been applied.

FIG. 2 is a schematic diagram used for explaining reference numerals to which the present invention is applied;

FIG. 3 is a schematic diagram used for explaining reference numerals to which the present invention is applied;

FIG. 4 is a schematic diagram used for explaining reference numerals to which the present invention is applied;

FIG. 5 is a schematic diagram used for describing symbols to which the present invention is applied.

FIG. 6 is a block diagram illustrating an example of an encoder to which the present invention is applied;

FIG. 7 is a flowchart used to explain an encoder to which the present invention is applied;

FIG. 8 is a schematic diagram used for describing reference numerals to which the present invention is applied.

FIG. 9 is a block diagram showing an example of a decoder to which the present invention is applied;

FIG. 10 is a block diagram of another example of a decoder to which the present invention is applied.

FIG. 11 is a waveform diagram used for describing a decoder to which the present invention is applied.

FIG. 12 is a waveform diagram used for describing a decoder to which the present invention is applied.

FIG. 13 is a schematic diagram used for describing reference numerals to which the present invention is applied.

FIG. 14 is a block diagram used for describing another example of data transmission between electronic devices to which the present invention has been applied.

FIG. 15 is a timing chart used for describing another example of data transmission between electronic devices to which the present invention is applied.

FIG. 16 is a timing chart used for describing another example of data transmission between electronic devices to which the present invention has been applied.

FIG. 17 is a block diagram of an example of data transmission between conventional electronic devices.

FIG. 18 is a timing chart used to describe an example of data transmission between conventional electronic devices.

FIG. 19 is a block diagram of another example of data transmission between conventional electronic devices.

[Explanation of symbols]

1,2 ... electronic equipment, 4 ... encoder, 5 ...
decoder

Claims (5)

[Claims] 1. One of the codes comprises a data section having a first polarity and a synchronization section, and the other code comprises a data section having a second polarity and a synchronization section, for transmitting a binary digital signal. Method. 2. The digital signal transmission method according to claim 1, wherein said synchronization section comprises said first polarity and said second polarity. 3. An encoder for encoding a code comprising a data portion of a first polarity and a synchronization portion, and the other code comprising a code portion comprising a data portion of a second polarity and a synchronization portion. First signal generating means for generating a signal of a polarity; second signal generating means for generating a signal of a second polarity; and the data according to the length of the data section and the length of the synchronization section. An encoder including switching means for switching and outputting a signal of a unit, an output of the first signal generating means, and an output of the second signal generating means. 4. One of the codes is transmitted by a decoder for decoding a code composed of a data part of a first polarity and a synchronization part, and the other code is composed of a data part of a second polarity and a synchronization part. Based on the timing of the synchronization part of the code
Measuring means for measuring the length of one or the other polarity of the transmitted code; and determining the transmitted code in accordance with the length of the one or the other polarity of the transmitted code. A decoder including a determination unit. 5. One of the codes is transmitted by a decoder for decoding a code composed of a data part of a first polarity and a synchronization part, and the other code is composed of a data part of a second polarity and a synchronization part. And a data capturing means for capturing the output of the integrating means at the timing of the synchronization section of the transmitted code.