JP4026657B2 - Communication device - Google Patents

Description

  The present invention relates to a communication device suitable for use in data communication between a remote controller and an electronic device, for example, when the electronic device is controlled by a remote controller.

  For example, when an electronic device is controlled using a wired remote commander, data is serially transmitted between the remote commander and the electronic device. As described above, when data is transmitted serially between electronic devices, the data and the clock are conventionally transmitted, and the data is captured while being synchronized with the clock.

  That is, in FIG. 17, when data is transmitted from the electronic device 101 to the electronic device 102, the data line 103 for transmitting data and the clock for transmitting the clock are transmitted between the electronic device 101 and the electronic device 102. A clock line 104 is provided. Data is sent from the electronic device 101 to the electronic device 102 via the data line 103, and a clock is sent from the electronic device 101 to the electronic device 102 via the clock line 104.

  The electronic device 102 is provided with a register 105. Data sent from the electronic device 101 via the data line 103 is supplied to a data input terminal of the register 105 of the electronic device 102, and a clock sent from the electronic device 101 via the clock line 104 is sent to the register 105 of the electronic device 102. To the clock input terminal. Data sent via the data line 103 is captured by the register 105 of the electronic device 102 at a timing based on the clock sent via the clock line 104.

  For example, data is sent from the electronic device 101 to the electronic device 102 via the data line 103 as shown in FIG. 18A, and a clock is sent via the clock line 104 as shown in FIG. 18B. The register 105 of the electronic device 102 that receives this data receives the clock shown in FIG. 18B, and the data shown in FIG. 18A is taken in at the rising edge of this clock.

  As described above, conventionally, when data is serially transmitted between electronic devices, a data line and a clock line are provided, and data and a clock are transmitted. This is because, when data is transmitted, if the data is simply transferred serially, data “1” or “0” will continue to be captured at a correct timing if data “1” or “0” continues for a long time. As described above, if the data line 103 and the clock line 104 are provided between the electronic device 101 and the electronic device 102 to transmit the data and the clock, the data “1” or “0” is transmitted. Even when data continues for a long time, data can be accurately transferred.

  However, when data and a clock are transmitted in this way, there is a problem that the electronic device 101 and the electronic device 102 must be connected by at least two lines of the data line 103 and the clock line 104. . Therefore, as shown in FIG. 19, the electronic device 111 and the electronic device 112 are connected only by the data line 113, and the clock is reproduced by the PLL.

  That is, in FIG. 19, the data line 113 is provided between the electronic device 111 and the electronic device 112. The electronic device 112 is provided with a register 114 and a PLL 115. Data is transmitted from the electronic device 111 to the electronic device 112 via the data line 113. This data is supplied to the data input terminal of the register 114 and also supplied to the PLL 115. The PLL 115 regenerates the clock from the data sent through the data line 113. This clock is supplied to the clock input terminal of the register 114. Data sent via the data line 113 is captured by the register 114 of the electronic device 112 at a timing based on the clock reproduced by the PLL 115.

  As described above, when the PLL 115 is provided in the electronic device 112 on the receiving side and the clock is reproduced by the PLL 115, it is not necessary to provide a clock line. However, when the clock is reproduced by the PLL in this way, it is necessary to provide the PLL on the receiving side, which increases hardware. Even if the clock is reproduced by the PLL in this way, if the data “1” or “0” continues for a very long time, the PLL clock deviates from the original clock, which is incorrect. Data may be captured.

  Also, even when “1” data or “0” data continues for a very long time, a synchronization pattern may be inserted into the data at regular intervals so that the PLL clock does not deviate from the original clock. Conceivable. However, when such a synchronization pattern is inserted into data and transmitted, the signal speed is reduced, so the communication speed is reduced. If a synchronization pattern is inserted, the synchronization pattern is sent even during a period in which no data exists.

  Therefore, an object of the present invention is to provide a communication device that does not require a clock line when serially transmitting data between electronic devices, does not increase hardware, and does not cause data transmission errors. It is in.

In order to solve the above-described problems, the present invention includes a data period and a synchronization period in one code between a first transmission apparatus and a second transmission apparatus coupled by a single line. In the communication device that performs communication via a single line by the code, the first transmission device includes synchronization signal generation means for generating a synchronization signal output in the synchronization period, a binary output enabled state, and a high impedance state A buffer means capable of taking the data, a data fetch means for fetching data in a data period for each code from a code transmitted on a single line, and a code comprising a synchronization period and a data period in one code and a code generating means for generating a second transmission apparatus, a data output means for outputting data for each synchronization signal from the synchronization signal generating means and the output of a single line and data output means connected and connection means for, And a decoding means for retrieving the data of the data period by decoding the composed includes a code on the data period and a synchronization period code, when transmitting data from the second transmission device to the first transmission device In the data period, the buffer means is set in a high impedance state, the data output from the data output means via the connection means to the single line is taken in by the data taking means, and the first transmission apparatus When data is transmitted to two transmission devices, the buffer means is set to a binary output enabled state, the code generated by the code generation means is output on a single line via the buffer means, A communication apparatus is characterized in that a code outputted on a line is decoded by a decoding means to extract data in a data period .

  As described above, according to the present invention, the first transmission device includes a synchronization signal generation unit that generates a synchronization signal output in the synchronization period, a buffer unit that can take a binary output enabled state and a high impedance state, And a data fetching unit that fetches data in a data period for each code from a code transmitted on a single line, and the second transmission device outputs data for each synchronization signal from the synchronization signal generation unit Data output means, connecting means for connecting a single line and the output of the data output means, and when transmitting data from the second transmission device to the first transmission device, Since the buffer means is set to a high impedance state during the period and the data output from the data output means via the connection means to the single line is taken in by the data taking means, the first transmission The device can transmit a synchronization signal to the second transmission device connected on a single line during the synchronization period, and capture the output of the second transmission device by the buffer means during the data period. Can do.

  According to the present invention, the first transmission device includes a synchronization signal generation unit that generates a synchronization signal output in a synchronization period, a buffer unit that can take a binary output enabled state and a high impedance state, and a single transmission device. A data fetching unit that fetches data in a data period from a code transmitted on the line for each code, and the second transmission device outputs data for each synchronization signal from the synchronization signal generation unit And a connection means for connecting the single line and the output of the data output means, and when data is transmitted from the second transmission device to the first transmission device, a buffer is provided in the data period. The means is in a high impedance state, and the data output on the single line from the data output means via the connection means is captured by the data capture means.

  Therefore, the first transmission device can transmit a synchronization signal in the synchronization period to the second transmission device connected on a single line, and the output of the second transmission device in the data period. Can be captured by the buffer means, and the encoded data can be captured on the first transmission device side without providing the second transmission device with an encoder that encodes the code composed of the data portion and the synchronization portion. There is an effect that can be done.

  In addition, according to the present invention, when data is serially transmitted between electronic devices, the data is encoded into a code composed of a data portion and a synchronization portion, so that there is no error even if a clock is not transmitted on a separate line. Data can be transmitted. In addition, according to the present invention, encoding can be performed simply by adding a synchronization unit to the data unit, and for example, decoding can be performed simply by measuring a low-level period immediately before the rise of data, so that the encoder and decoder are not complicated. , Hardware does not increase.

  Embodiments of the present invention will be described below with reference to the drawings. The present invention is used to serially transmit data between two electronic devices, as in the case of controlling an MD player with a wired remote commander.

  In FIG. 1, an electronic device 1 and an electronic device 2 are connected via a data line 3. The electronic device 1 is, for example, a remote commander, and the electronic device 2 is, for example, an MD player controlled by this remote commander.

  The electronic device 1 is provided with an encoder 4, and the electronic device 2 is provided with a decoder 5. Data of the electronic device 1 is encoded by the encoder 4 into a code composed of a data portion and a synchronization portion. The output of the encoder 4 is received by the decoder 5 of the electronic device 2 via the data line 3. The decoder 5 decodes the data from the code composed of the data part and the synchronization part.

  Thus, in the present invention, when data is sent between the electronic device 1 and the electronic device 2, the data is encoded into a code composed of the data portion and the synchronization portion. When data is transmitted after being encoded into a code composed of a data portion and a synchronization portion in this way, it is not necessary to send a clock through a separate signal line, and it is not necessary to regenerate the clock using a PLL. The code composed of the data part and the synchronization part will be described in further detail.

2A and 2B show the code “0” and the code “1” used at the time of transmission in the present invention. As shown in FIG. 2A, the code “0” is held at a low level for a predetermined time T ₁ and then becomes a high level for a predetermined time T ₂ . As shown in FIG. 2B, the code “1” is held at the high level for the predetermined time T ₃ , then becomes the low level for the predetermined time T ₄ , and then becomes the high level for the predetermined time T ₅ .

Here, the first low-level period T ₁ with the code “0” is equal to the period obtained by combining the high-level period T ₃ with the code “1” and the low-level period T ₄ with the code “1”. A high-level period T ₂ in the latter half at “0” is equal to a high-level period T _{5 in} the latter half of the code “1”. Also, the low level period T ₁ of the code “0” is sufficiently longer than the low level period T ₄ of the code “1”. That is,
T ₁ = T ₃ + T ₄
T ₂ = T ₅
T ₁ > T ₄
Are in a relationship.

As shown in FIG. 2A, the minimum communication unit time T _unit0 of the code “0” is
T _unit0 = T ₁ + T ₂
As shown in FIG. 2B, the minimum communication unit time T _unit1 of the code “1” is
T _unit1 = T ₃ + T ₄ + T ₅
It is. Then, the minimum communication unit time T _Unit0 code "0", equal to the minimum communication unit time T _unit1 code "1",
T _unit0 = T _unit1
Are in a relationship.

  Such a code is formed based on the idea that a synchronization part is added to the data part for transmission.

That is, in the data portion, “0” is a low level signal and “1” is a high level signal. As shown in FIG. 3, the synchronization unit is a signal including a low level period of a period t ₁₁ and a high level period of a period t ₁₂ .

The code “0” is obtained by adding a synchronization unit SY as shown in FIG. 3 to the low-level data unit. That is, as shown in FIG. 4A, in the case of the code "0", the data unit DA0 is a low level for a predetermined time T _21. This data unit DA0, as shown in FIG. 4B, when the synchronizer SY consisting of high-level period of the low-level period and the predetermined time T ₁₂ of the predetermined time T ₁₁ is added, as shown in FIG. 4C , A code “0” is formed. here,
T ₂₁ + T ₁₁ = T ₁
T ₁₂ = T ₂
Then, it becomes equal to the format of the code “0” shown in FIG. 2A.

The code “1” is obtained by adding a synchronization unit SY as shown in FIG. 3 to the high-level data unit. That is, as shown in FIG. 5A, in the case of the code "1", the data unit DA1 is a high level for a predetermined time T _31. This data section DA1, as shown in FIG 5B, when the synchronizer SY consisting of high-level period of the low-level period and the predetermined time T ₁₂ of the predetermined time T ₁₁ is added, as shown in FIG. 5C , The code “1” is formed. here,
T ₃₁ = T ₃
T ₁₁ = T ₄
T ₁₂ = T ₅
Then, it becomes equal to the format of the code “1” shown in FIG. 2B.

  In this way, by adding the synchronization unit SY having a low level for a predetermined time and a high level for a predetermined time to the data portions DA0 and DA1 in which the code “0” is a low level and the code “1” is a high level. 2A and 2B are formed.

  FIG. 6 shows a configuration of an encoder that generates such a code. In FIG. 6, reference numeral 31 denotes a shift register. Data for transmission is supplied from the input terminal 32 to the shift register 31. The shift register 31 is shifted by a shift clock from the timer control circuit 40. The output of the shift register 31 is supplied to the terminal 34A of the switch circuit 34.

  A low level signal from the low level signal generation circuit 35 is supplied to the terminal 34B of the switch circuit 34. A high level signal from the high level signal generation circuit 36 is supplied to the terminal 34C of the switch circuit 34. The switch circuit 34 is controlled by the timer control circuit 40. An output terminal 41 is derived from the switch circuit 34.

For the timer control circuit 40, a data section timer 37, a low level period timer 38, and a high level period timer 39 are provided. The data part timer 37 measures the period of the data part (periods T ₂₁ and T ₃₁ in FIGS. 4 and 5). The low level period timer 38 measures the low level period (period T ₁₁ in FIGS. 4 and 5) of the synchronization unit. The high level period timer 39 measures a high level period (period T ₁₂ in FIGS. 4 and 5) of the synchronization unit.

  The timer control circuit 40 performs a process as shown in the flowchart of FIG. As a result, the signal encoded as described above is output from the output terminal 41.

  That is, as shown in FIG. 7, first, the switch circuit 34 is set to the terminal 34A side (step ST1). Then, the data part timer 37 is set (step ST2).

  When the switch circuit 34 is set to the terminal 34A side, the data from the shift register 31 is output from the output terminal 41.

  It is determined from the output of the data part timer 37 whether or not the output period of the data part has elapsed (step ST3). When the output period of the data part has elapsed, the data part timer 37 is cleared (step ST4), and the switch circuit 34 is set to the terminal 34B side (step ST5). Then, the low level period timer 38 is set (step ST6).

  When the switch circuit 34 is set to the terminal 34B side, a low level signal from the low level signal generation circuit 35 is output from the output terminal 41.

  It is determined from the output of the low level period timer 38 whether or not the low level output period of the synchronization unit has elapsed (step ST7). When the low level output period of the synchronization unit has elapsed, the low level period timer 38 is cleared (step ST8), and the switch circuit 34 is set to the terminal 34C side (step ST9). Then, the high level period timer 39 is set (step ST10).

  When the switch circuit 34 is set to the terminal 34C side, a high level signal from the high level signal generation circuit 36 is output from the output terminal 41.

  From the output of the high level period timer 39, it is determined whether or not the high bell output period of the synchronization unit has elapsed (step ST11). When the high level output period of the synchronization unit has elapsed, the high level period timer 39 is cleared (step ST12). Then, after one shift clock is sent (step ST13), the process returns to step ST1.

  Through the control as described above, a low-level or high-level data portion is added with a low-level synchronization portion for a predetermined time and low level for a predetermined time, and is encoded from the output terminal 41 as described above. A signal will be output.

  Next, the decoding process of such a code will be described. Such a code can be decoded, for example, depending on whether the low level period immediately before the low-level to high-level change point is longer than the low-level period of the latter half of the code “1”.

  That is, as shown in FIG. 8, it is assumed that the code encoded as described above is input. This code is “0”, “1”, “1”, “0”.

When such a code is input, transition points t ₁₁ , t ₁₂ , t ₁₃ , t ₁₄ ... From low level to high level are detected at the time of decoding. Then, the length of the low level immediately before the change points t ₁₁ , t ₁₂ , t ₁₃ , t ₁₄ ... From the low level to the high level is determined, and is decoded to “0” or “1”. .

At the time point t ₁₁ , the low level length L ₁₁ immediately before that is longer than the low level period of the latter half of the code “1”, so that it is decoded to “0”. At the time point t ₁₂ , the low level length L ₁₂ immediately before is shorter than the low level period of the latter half of the code “1”, so that it is decoded to “1”. At time point t ₁₃ , the length L ₁₃ of the previous low level is shorter than the low level period of the latter half of the code “1”, so that it is decoded to “1”. At the time point t ₁₄ , the low level length L ₁₄ immediately before is longer than the low level period of the latter half of the code “1”, and thus is decoded to “0”.

  FIG. 9 shows an example of a decoder that performs decoding based on whether or not the low level period immediately before the transition point from the low level to the high level is longer than the low level period of the latter half of the code “1”. is there.

  In FIG. 9, received data is supplied to the input terminal 51. This received data is supplied to the falling edge detection circuit 52 and also to the rising edge detection circuit 53. The output of the rising edge detection circuit 52 and the output of the falling edge detection circuit 53 are supplied to the low level period measurement timer 54. The low level period measurement timer 54 starts measurement at the output of the falling edge detection circuit 52 and ends the measurement at the output of the rising edge measurement circuit 53.

  The output of the low level period measurement timer 54 is supplied to the comparators 55 and 56. The output of the code “1” measurement time generation circuit 57 is supplied to the comparator 55. The output of the code “0” measurement time generation circuit 58 is supplied to the comparator 56.

The code “1” measurement time generation circuit 57 is set to a time (period T ₄ in FIG. 2B) corresponding to the low level period immediately before the change point from the low level to the high level in the case of the code “1”. In the code “0” measurement time generation circuit 58, the time corresponding to the low level period immediately before the change point from the low level to the high level in the case of the code “0” (period T ₁ in FIG. 2A) is set. .

  Outputs of the comparators 55 and 56 are supplied to the determination circuit 59. The determination circuit 59 determines the sign of the received data from the outputs of the comparators 55 and 56.

  In other words, the low level period measurement timer 54 measures the low level period immediately before the change point from the low level to the high level. The comparator 55 determines whether or not the low level period immediately before the low-level to high-level change point coincides with the low-level period immediately before the low-level to high-level change point in the case of “1”. Detected. The comparator 56 determines whether the low level period immediately before the low-level to high-level change point coincides with the low-level period immediately before the low-level to high-level change point in the case of the code “0”. To be judged. The detection outputs of the comparators 55 and 56 are supplied to the determination circuit 59.

  The determination circuit 59 determines, based on the output of the comparator 55, the low level period immediately before the high level change point when the low level period immediately before the low level to high level change point is “1”. When it is determined that they match, it is decoded to “1”. Further, from the output of the comparator 56, when the low-level period immediately before the low-level to high-level change point coincides with the low-level period immediately before the low-level to high-level change point when the code is “0”. If it is determined, it is decoded to “0”.

  FIG. 10 shows another example of the decoder. In the above example, decoding is performed depending on whether the low level period immediately before the transition point from the low level to the high level is longer than the low level period of the latter half of the code “1”. The decoding is performed by storing in the integrating circuit comprising a resistor and a capacitor whether the low level signal time of the received data is short or long.

  In other words, in FIG. 10, the received data from the input terminal 61 is supplied to the clock input terminal of the D flip-flop 62 and also supplied to the integrating circuit 65 including the resistor 63 and the capacitor 64. The output of the integrating circuit 65 is supplied to the data input terminal of the D flip-flop 62.

  The D flip-flop 62 takes in the received data via the integrating circuit 65 at the rising edge of the received data. In the integrating circuit 65, the length of the low level period of the received data is stored.

  That is, as shown in FIG. 11, when a signal having a long low level period (FIG. 11A) is input, the output of the integrating circuit 65 drops to a low level as shown in FIG. 11B. For this reason, as shown in FIG. 11C, when the output of the integration circuit 65 is captured at the rising edge of the data, the captured data becomes a low level. On the other hand, as shown in FIG. 12, when a signal with a short low level period (FIG. 12A) is input, the output of the integrating circuit 65 does not drop to the low level as shown in FIG. 12B. . For this reason, as shown in FIG. 12C, when the output of the integration circuit 65 is captured at the rising edge of the data, the captured data becomes a high level.

  Thus, the integration circuit 65 stores the low level period immediately before the data rises from the low level to the high level, and the low level period immediately before the data rises from the low level to the high level is long. If the low level period immediately before the data rises from the low level to the high level is short, the high level is taken into the D flip-flop 62.

  In the above example, only binary data of code “0” and code “1” is transmitted, but a synchronization pattern may be sent as shown in FIG. In FIG. 13, a period indicated by SYNC is a pattern for synchronization. This synchronization pattern is set to be at a low level for a period longer than the low level period at code “0”. This synchronization pattern can be used to notify the start of data transmission.

  FIG. 14 shows an example in which data can be exchanged between the electronic device on the master side and the electronic device on the slave side. In FIG. 14, 71 is an electronic device on the master side, and 72 is an electronic device on the slave side. The master electronic device 71 is provided with an encoder 73. As the encoder 73, an encoder having the structure shown in FIG. 6 is used. The electronic device 71 on the master side is provided with a tristate buffer 74 and a D flip-flop 75 for receiving data. The slave-side electronic device 72 is provided with a decoder 77. As the decoder 77, the one shown in FIG. 9 or FIG. 10 is used. Furthermore, the slave-side electronic device 72 is provided with a data transmission shift register 78 and a resistor 79. The master-side electronic device 71 and the slave-side electronic device 72 are connected via a transmission line 80.

  In such a configuration, not only data can be transmitted from the electronic device 71 on the master side to the electronic device 72 on the slave side, but also data can be transmitted from the electronic device 72 on the slave side to the electronic device 71 on the master side.

  That is, when data is transmitted from the master-side electronic device 71 to the slave-side electronic device 72, the data is encoded by the encoder 73 of the master-side electronic device 71, and this data is stored in the tristate buffer 74, the transmission line 80. And sent to the electronic device 72 on the slave side. Then, this data is decoded by the decoder 77 of the electronic device 72 on the slave side.

  When data is transmitted from the slave-side electronic device 72 to the master-side electronic device 71, the data is output from the shift register 78 of the slave-side electronic device 72. Data from the shift register 78 is sent to the electronic device 71 on the master side via the resistor 79 and the transmission line 80. Then, this data is captured by the D flip-flop 75 of the electronic device 71 on the master side.

  As described above, when data is transmitted from the slave-side electronic device 72 to the master-side electronic device 71, the tri-state buffer 74 is set to the high impedance state for a period corresponding to the period of the data portion. As described above, when the period tri-state buffer 74 corresponding to the period of the data portion is set to the high impedance state, the D flip-flop 75 of the master-side electronic device 71 does not have an encoder in the slave-side electronic device 72. Encoded data can be imported.

That is, as shown in FIG. 15A, it is assumed that a high level signal is output from the shift register 78 of the electronic device 72 on the slave side. As shown in FIG. 15B, the tri-state buffer 74 is set to the high impedance state in the period T ₅₁ of the data portion. For this reason, in the period T _{51 of the} data part, as shown in FIG. 15C, the signal (high level) from the shift register 78 is input to the D flip-flop 75 of the electronic device 71 on the master side as it is. In the period T ₅₂ in the synchronization section, the tri-state buffer 74 is driven. For this reason, a signal of the synchronization unit that is low level for a predetermined period and high level for a predetermined period is input to the D flip-flop 75 from the encoder 73. Therefore, as shown in FIG. 15C, the encoded code “1” is input to the D flip-flop 75.

As shown in FIG. 16A, it is assumed that a low-level signal is output from the shift register 78 of the electronic device 72 on the slave side. As shown in FIG. 16B, the tri-state buffer 74 is set to the high impedance state in the period T ₅₁ of the data portion. For this reason, in the period T _{51 of the} data portion, as shown in FIG. 16C, the signal (low level) from the shift register 78 is input to the D flip-flop 75 of the master-side electronic device 71 as it is. In the period T ₅₂ in the synchronization section, the tri-state buffer 74 is driven. For this reason, a signal of the synchronization unit that is low level for a predetermined period and high level for a predetermined period is input to the D flip-flop 75 from the encoder 73. Accordingly, as shown in FIG. 16C, the encoded code “0” is input to the D flip-flop 75.

It is a block diagram used for description of an example of the data transmission between the electronic devices to which this invention was applied. It is a basic diagram used for description of the code | symbol to which this invention was applied. It is a basic diagram used for description of the code | symbol to which this invention was applied. It is a basic diagram used for description of the code | symbol to which this invention was applied. It is a basic diagram used for description of the code | symbol to which this invention was applied. It is a block diagram of an example of the encoder to which this invention was applied. It is a flowchart used for description of the encoder to which this invention was applied. It is a basic diagram used for description of the code | symbol to which this invention was applied. It is a block diagram of an example of a decoder to which the present invention is applied. It is a block diagram of the other example of the decoder to which this invention was applied. It is a wave form diagram used for description of the decoder to which this invention was applied. It is a wave form diagram used for description of the decoder to which this invention was applied. It is a basic diagram used for description of the code | symbol to which this invention was applied. It is a block diagram used for description of the other example of the data transmission between the electronic devices with which this invention was applied. It is a timing diagram used for description of the other example of the data transmission between the electronic devices with which this invention was applied. It is a timing diagram used for description of the other example of the data transmission between the electronic devices with which this invention was applied. It is a block diagram of an example of the data transmission between the conventional electronic devices. It is a timing diagram used for description of an example of the data transmission between the conventional electronic devices. It is a block diagram of the other example of the data transmission between the conventional electronic devices.

Explanation of symbols

1, 2 Electronic equipment 4 Encoder 5 Decoder

Claims (1)

Communication between the first transmission device and the second transmission device coupled by a single line via the single line by a code comprising a data period and a synchronization period in one code. In the communication device to perform
The first transmission device includes:
Synchronization signal generating means for generating a synchronization signal output during the synchronization period;
Buffer means capable of taking a binary output enabled state and a high impedance state;
A data capturing means for capturing the data of the data period for each sign of the 1 from the transmitted the code on the single line,
Code generating means for generating a code comprising a synchronization period and a data period in one code ,
The second transmission device is
Data output means for outputting data for each synchronization signal from the synchronization signal generating means;
Connection means for connecting the single line and the output of the data output means ;
Decoding means for decoding a code comprising a data period and a synchronization period in one code and extracting data in the data period ;
When transmitting data from the second transmission device to the first transmission device,
In the data period, the buffer means is in the high impedance state, and the data output from the data output means via the connection means to the single line is captured by the data capturing means ,
When transmitting data from the first transmission device to the second transmission device,
The buffer means is set in the binary output enabled state, the code generated by the code generation means is output on the single line via the buffer means, and the code output on the single line is output. A communication apparatus characterized in that the data is decoded by the decoding means and the data in the data period is extracted .

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