JPH0234508B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a decoding circuit for decoding a variable length encoded signal sequence received at a constant speed.

(2) Background of the technology Differential encoding methods are used to compress bandwidth when encoding and transmitting image signals. The bit length is changed according to this time difference, and a pattern is also fixedly assigned to make encoding easier, creating a variable length code.When transmitting, a fixed length code is used to keep the transmission speed constant. A method to do so is being implemented. This will be explained using FIG. As shown in figure a, when the difference is “+10” it is “0001”, when it is “+5” it is “001”, when it is “+2” it is “01”, when it is “-2” it is “10”.
", "-10" is assigned a fixed pattern of "1001", and when transmitted, it is transmitted as a fixed length of, for example, 8 bits. Figure b shows how the data is converted to this fixed length. The differential data is " +10”, “+5”, “+2”,
If you send "-2" and "-10" in this order, the first "0001" representing "+10", "001" representing "+5", and the first "0" of "01" representing "+2" Set in the send buffer and send. Next, "1" of "01" representing "+2", "10" representing "-2", and "1001" representing "-10" are sequentially set in the transmission buffer.

Since the pattern and the difference correspond to each other, decoding of the data converted into a fixed length code and transmitted is carried out by detecting the pattern.

(3) Prior Art and Problems In the above system, the configurations shown in FIGS. 2a and 2b have been proposed as decoding circuits that have been conventionally used. First, to explain the case in Fig. 2a, 1 in the figure is an input terminal, 2 is a buffer memory,
3 is a phase expansion circuit, 4 is a multiplexer, 5 is a variable length decoder, 6 is an output terminal, and 7 is a decoding code length management circuit.

The buffer memory 2 sequentially writes the constant speed fixed code input from the input terminal 1 at a constant speed.
The bits (for example, 8 bits) are output in parallel. The phase expansion circuit 3 is composed of a flip-flop, and alternately stores the signals sent from the buffer memory 2, and outputs 2K bits in parallel. The multiplexer 4 receives instructions from the decoding code length management circuit 7 and receives instructions from the phase expansion circuit 3.
A signal sequence starting from the code to be decoded next from among the 2K bit signals is output in parallel in the form of K bits. When the multiplexer 4 receives an instruction (shift amount) 1 from the decoding code length management circuit 7, it shifts the 2K bit signal downward by 1 bit, for example, by wired logic, and parallelizes the K bit signal. will be output to . The variable length encoder 5 inputs the signal sequence output from the multiplexer 4, detects a predetermined variable length code pattern, outputs the decoded code to the output terminal 6, and outputs the decoded code to the output terminal 6. code length in binary n
It is expressed in bits and sent to the decoding code length management circuit 7. For example, if the output code has a code length of 5 bits, it is sent to the management circuit 7 in the form of "0101". The decoding code length management circuit 7 is composed of an (n+1) bit adder that adds its own output value and the signal sent from the variable length decoder 5, and the output value, that is, the addition result is sent to the phase expansion circuit 3. It represents the number of bits that have been decoded up to this point in the signal stored in the memory. this. The addition result is (n+1)
It is sent in the form of a binary number of bits to the multiplexer 4, where it is used as a control signal. Furthermore, among the outputs of the decoding code management circuit 7, n
The bit-th signal is used as a read clock from the buffer memory 2, and the (n+1)th bit, NBS, is used as a clock for the phase expansion circuit 3. Note that in the above, K bits can be considered to be 2 ⁿ bits.

In order to make the explanation easier to understand, an example will be given. Suppose that variable length codes such as code lengths ``2'', ``3'', ``5'', ``4'', etc. are sequentially stored in the buffer memory 2 and sent out from the output terminal 6 in a first-in, first-out format. n = 4, K = 2 ⁴ = 16.

(1) In this case, the above code lengths are “2”, “3”, “5”,
The 16 bits (4 and the first 2 bits of 6) are set in the flip-flop at the top of the figure, and the remaining 4 bits of the code length 6, 1,
The 16 bits of "4" and "7" are set in the flip-flop at the top of the diagram, and multiplexer 4 is set.
supplied to

(2) In this case, (n-1) of the decoding code length management circuit 7
The added value of the bit adder is "00000", so the multiplexer 4 shifts the input signal by 0, that is, without shifting the input signal, converts the 16 bits starting from the variable length code of the first code length "2" into a variable length code. The signal is supplied to the decoder 5.

(3) In this state, the variable length decoder 5 first decodes the code with code length “2” and outputs it to the output terminal 6.
At the same time, the variable length decoder 5 supplies the binary number "0010" to the (n+1) bit adder.

(4) As a result, the addition result by the (n+1) bit adder becomes "00010", and the multiplexer 4 is notified of this fact. As a result, the multiplexer 4 shifts the input signal by 2 bits, removes the decoded code length "2", and transfers the 16 bits starting with the variable length code of code length "3" to the variable length decoder 5. supply to.

(5) The variable length decoder 5 now has a code length of “3”.
The code is decoded and output to the output terminal 6, and at the same time, the binary number "0010" is sent to the (n+1) bit adder.
supply.

(6) As a result, the addition result by the (n+1) bit adder is "2" + "3", that is, "00101",
The multiplexer 4 is notified of this fact. As a result, the multiplexer 4 shifts the input signal by 5 bits and removes the code lengths "2" and "3" which have already been encoded, and generates the code length "5" in the same manner as described above.
The 16 bits starting with the variable length code are supplied to the variable length decoder 5.

(7) The variable length decoder 5 now has a code length of “5”.
The code is decoded and output to the output terminal 6, and at the same time, the binary number "0101" is sent to the (n+1) bit adder.
supply.

(8) As a result, the addition result by the (n+1) bit adder is "5" + "5", that is, "01010",
The multiplexer 4 is notified of this fact.

(9) At this time, in the addition result of the (n+1) bit adder, the n-th bit, that is, the fourth bit in this case, changes to logic "1", so a clock is supplied to the buffer memory 2 under this condition and reading is performed. At this time, in the addition result of the (n+1) bit adder, the (n+1)th bit, that is,
Since the MSB corresponds to logic ``0'', 16 bits starting from the assumed code length ``3'' are set in the flip-flop at the bottom of the diagram.

(10) In the process of (8) above, the multiplexer 4 is notified of the addition result "01010", and the multiplexer 4 converts the 16 bits starting from the code with the code length "4" to the variable length decoder in the same way as above. Supply to 5.

(11) The variable length decoder 5 now has a code length of “4”.
The code is decoded and output to the output terminal 6, and at the same time, the binary number "0100" is sent to the (n+1) bit adder.
supply.

Decryption is performed as described above.

However, in this circuit, if a bit error occurs in the transmission path, for example, a variable length code of code length "2" becomes code length "3", which cannot be decoded with code length "2", or
It happened that it was decoded as a variable length code of "4". However, even if it happens to be decrypted once,
Since the patterns do not match from the next code onwards, there is a drawback that the code cannot be decoded.

For this purpose, a decoding circuit as shown in FIG. 2b has also been proposed.

The operation in this case will be explained.

The received signal is temporarily stored in a buffer memory (BM) 20, and when a header (unique word) of a frame is detected by a header (HD) detection section 21, the number of transmitted words is stored in a transmitted word number counter 23. On the other hand, the code decoder 22 starts decoding the variable length code in the received signal (data), and sends an update signal to the received word number counter 24 in units of received words to start counting. The received word number counter 24 continues to be updated until the number of transmitted words A and the number of received words B match. At this time, the received data is also sent to a variable length decoder. Then, when one frame is completely received, that is, when the header of the next frame is detected, the value A of the transmission word counter 23 is
When the count value B of the received word number counter 24 does not match, the next process is performed depending on the magnitude relationship between A and B. When B is smaller than A, the pseudo information sending circuit 28 outputs an instruction signal to the code decoder 22, and sends pseudo signals corresponding to the number of unprocessed words to the variable length decoder. When B is larger than A, the fast reading circuit 29 sends an instruction signal to the code decoder 22 to read the next frame quickly. The former of these signals corresponds to a reset signal, and the latter is performed by changing the data reading clock cycle, etc.

That is, by temporarily storing the received data in the buffer memory (BM) 20 shown in FIG. 2 and detecting the header part HD of the received frame, frame synchronization with the transmitting side is achieved using a known frame synchronization method. is taken. Then, the variable length data part within the frame is decoded based on the information in the fixed data part. In this case, on the receiving side,
If the number of words increases or decreases due to a data error, the number of words on the transmitting side specified by the number of transmitted words WD will no longer match the number of received words, and the relative position of the header HD in the transmitter and receiver will change. As a result, the sending and receiving sides become out of synchronization.

In order to absorb such discontinuity, as in the previous procedure, by looking at the magnitude relationship between the count value A of the transmission word number counter 23 and the count value B of the transmission word number counter 24, pseudo information for the number of unprocessed words is generated. By inserting or quickly reading the excess number of words in the next frame, the discontinuity is resolved and synchronization with the transmitting side is reestablished in the next header HD. This will cause resynchronization.

Figure c is a diagram for explaining the operation of the resynchronization circuit in figure b. In the figure, A indicates transmission information,
B and C show the operations on the receiving side. In each of these figures, the ↑ mark indicates the header portion of each frame.

In Figure C, A ₁ , A ₂ , A ₃ , . . . indicate the number of words in each transmitted frame. B shows the case where a code error occurs and the number of words processed on the receiving side is small and A ₁ >B ₁ . In this case, in the next frame, (A ₁ − B ₁ ) words of pseudo information are first processed, and then the number of words on the transmitter side is
Processing of the number of words B ₂ equal to A ₂ is performed on the receiving side, and after the end of the frame, the transmitting side and the receiving side are synchronized.

C shows a case where the number of words processed on the receiving side due to code errors is large, and A ₁ <B ₁ .
In this case, when the processing of B ₁ words on the receiving side is completed, (B ₁ <A ₁ ) is read into the unprocessed word number signal source 25, and then the information for the transmitted A ₂ words is quickly read. In C, B ₂ ′ indicates the number of words read quickly in this way. Afterwards
Send pseudo information by A ₂ − {(B ₁ − A ₁ ) + B ₂ ′},
By processing B ₃ equal to A ₃ of the next transmitted sender, after the end of that frame,
The sender and receiver can be synchronized.

However, with this circuit, it is necessary to send out a special code and pick up the code.
There was a problem that the control became complicated.

(4) Purpose of the invention The present invention has been made in view of the above points.
It is an object of the present invention to provide a decoding circuit which can minimize the influence of bit errors even if they occur, and which simplifies control when detecting special codes.

(5) Structure of the Invention The above object is to receive a variable-length coded signal sequence in which a special code is inserted at a constant period into a variable-length code sequence at a constant speed, and to receive a predetermined bit length unit from the reception buffer. The bit position indicated by the adder circuit output is read out as the first bit, and the decoder decodes it according to the bit pattern, and the number of bits corresponding to each bit pattern is input to the adder circuit. , and when the special code is detected, the adder circuit output is compared with the position of the first bit of the special code within the predetermined bit length, and the adder circuit output bit is added to the previous read position. When the position < special code output bit position, the code decoding using the adder circuit output as the output continues as before, and when the adder circuit output bit position ≧ the special code output bit position, the control circuit is reset and the code added to the special code is decoded. Control is performed to decode each bit information and the number of transmitted codes, etc., and then the number n' of actually transmitted codes is compared with the number n of codes to be included between special codes, and n' is When it is smaller than n, reading from the holding circuit is stopped until n and n' become equal; when n' is larger, reading is continued in units of the predetermined bit length until the next special code is detected. and at this point, the reading is stopped for the number of codes that is the difference between n and the sum of the number of codes n'' read in the predetermined bit length unit and the value of n'-n. This is achieved by a decoding circuit.

(6) Embodiments of the invention In the present invention, a special code and a code indicating the number of codes between the special codes are inserted at fixed intervals on the transmitting side,
Every time this special code is detected, the reading position from the holding circuit is corrected.

This will be explained below with reference to FIG.

In the figure, 8 is a control circuit, 9 is a special code detection circuit, and 7
a, 7b, and 10 are flip-flops, 7c is an adder, SEL is a selector, CMP is a comparator, OR is an OR gate, AND1 and AND2 are AND gates, and the same reference numerals are given to the same components as the second one.

To explain the operation, a variable-length code string from input terminal 1 is stored in buffer memory 2, output to flip-flop 3, and special code detection circuit 9
Enter. The special code is composed of, for example, 12 bits, and its pattern is "100000000001". If no special code is detected, selector
SEL connects the output of the adder 7c to the flip-flop 7a.
, and feeds it back to the adder 7c and inputs it to the multiplexer 4.

On the other hand, when the special code detection circuit 9 detects a special code, a bit indicating the detection and the position of the first bit of the special code within the K bits are set in the flip-flop 10. Then, the comparator CMP compares the adder output with the first bit position of the special code set in the flip-flop. When the adder output is small, the selector SEL selects the adder output using the comparator CMP output, and flip-flop 7
Set to a. On the other hand, when they are equal or when the adder output becomes large, the output of the flip-flop 10 is selected by the output of the comparator CMP, set in the flip-flop 7a, and the special code is read out from the multiplexer 4 and set in the variable length decoder 5. . Furthermore, the comparator output is sent to flip-flop 7b.
is set to . The output of the flip-flop 7b is connected to the control circuit 8, an OR gate, and an AND gate.
It is input to flip-flops 3 and 10 via AND1. When the control circuit 8 receives the output of the flip-flop 7b, it performs processing as shown in FIG.

In other words, a special code uw for every n ₁ code in the figure a.
Assume that you insert and send. Then, when the special code uw is read from the multiplexer 4 as in the previous procedure, the number of codes from the previously read special code is tested, and if n ₁ , the code length detection circuit in the variable length decoder 5 Forcibly output the number of bits of the special code.

This causes the adder output to indicate the address of the first bit of the code following the special code.

On the other hand, if the number of received codes is less than the number of codes sent as shown in figure b, the AND gate AND2 is closed by the difference in the number of codes (n ₁ - n ₁ '), the clock is disabled, and the update of the adder is prohibited. do. Then, when n ₁ -n ₁ ' codes are generated by the control signal to the variable length decoder 5, a special code is forcibly output from the code length detection circuit. Furthermore, as shown in figure c, the number of received codes
If n ₁ '' is larger than n ₁ , the variable length decoder continuously outputs the maximum fixed code length, in the example shown in the figure, the number of bits K, until the next special code is detected, and fast reading is performed. When the next special code is detected,
Only n ₁ − (n ₁ ″− n ₁ + n _x ) codes are prohibited from being read.

After that, the number of bits of the special code is output.

(7) Effects of the Invention As described above, according to the present invention, when a mismatch occurs between the number of transmitted codes and the number of received codes due to a transmission path error, etc., the bit position of the special code is input to the circuit that indicates the decoding start bit position. This makes it easier to recover from mistakes.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the process of converting a variable length code into a fixed length code, Fig. 2 a, b, and c are diagrams showing a conventional decoding circuit and its operation, and Fig. 3 is a diagram showing a decoding circuit according to the present invention. FIG. 4 is a diagram showing the operation of the decoding circuit according to the present invention. In the figure, 2 is buffer memory, 3, 7a, 7b, 1
0 is a flip-flop, 4 is a multiplexer, 5
7 is a variable length decoder, 7 is a decoding code length management circuit, 8 is a control circuit, and 9 is a special code detection circuit.

Claims (1)

[Claims] 1. Inputting a variable-length encoded signal string in which a special code is inserted at a constant period into a variable-length code string into a receiving buffer, and extracting a predetermined bit length k from the receiving buffer.
The data is read out in units of the predetermined bit length, and the holding circuit holds the predetermined bit length k continuously for 2k, and the multiplexer reads the data in units of the predetermined bit length with the bit position indicated by the output of the adder circuit as the first bit. The variable length encoded signal string is decoded by a decoder according to the pattern, and the number of bits corresponding to each bit pattern is input to the adder circuit and added to the position read from the previous multiplexer, thereby sequentially decoding the variable length encoded signal string. Detects the special code and holds the position of the first bit of the special code within the predetermined bit length, and uses the comparator to compare the output of the adder circuit with the predetermined bit length of the first bit of the special code. When they match or when the output of the adder becomes large, set the position of the first bit of the special code in the predetermined bit length in the adder, and set the special code before the special code. Number of codes decoded after detecting the code
Compare n' with the number n of codes that should be included between special codes, and when n' is smaller than n, read from the buffer memory and change the read position from the multiplexer until n and n' become equal. and when n' is larger than n, the variable length decoder reads the decoded signal sequence in a predetermined bit length unit until a special code is detected, and then reads the decoded signal string in the predetermined bit length unit. The reading of codes from the buffer memory and the change of the reading position from the multiplexer are stopped by the number of codes represented by 2n - (n′+n ^x ), where n ^x is the number of codes read in decoding circuit.