JPS58175366A - Decoding circuit - Google Patents

Abstract

PURPOSE:To eliminate an effect of a bit error for a decoding circuit which decodes the variable length code of a picture signal, by inserting a special code with each fixed period at the transmitting side and setting the reading address at a fixed value every time the special code is detected. CONSTITUTION:A variable length code train supplied from an input terminal 1 is stored in a buffer memory 2 and delivered to an FF3 as well as fed to a special code detecting circuit 9. When no special code is detected, a selector SEL sets the output of an adder to an FF7a to feed it back to the adder as well as to supply it to a multiplexer 4. As a result, a differentially coded variable length code is decoded. When a special code is detected by the circuit 9, a comparator CMP compares the output of the adder with the position of the head bit of the special code set to an FF10. Based on the result of this comparison, the output of the adder or the output of the FF10 is set to the FF7a. At the same time, the result of comparison is set to an FF7b and the number of bits of the special code read out previously is inspected. The output of the adder shows the head bit of the next code.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Summary of the Invention The present invention relates to a decoding circuit for decoding a variable length encoded signal sequence received at a constant speed.

(2) Background of the Technology A differential encoding method is applied for band compression when encoding and transmitting a 1JJE signal. At this time, the bit length is changed according to the difference, and a pattern is fixedly assigned in order to make decoding easier. When transmitting, the transmission sequence is kept constant. This will be explained with reference to FIG. 1. (1) As shown in the figure, when the nutrients are 1+10" 000
1", +5 "001", +2 (1) @01'-2
A fixed pattern is assigned such as "IO" at 0 o'clock and @1001 at -10 o'clock, and when it is transmitted, it is transmitted as a fixed length of, for example, 8 bits.The conversion to this fixed length is shown in Figure t(b). Difference data t@+lo”.

"+5", "+2", -2", "-10' nol
[If you send K, first ``0'' representing #i''+10''
o01", "001'" representing 1+5@, and "01" representing 1+2", the first ``Om'' is set in the transmission buffer and transmitted.

Next, 11 of 101'' representing +2, 110'' representing 1-2''t-, and 1001'' representing -10'' are sequentially set in the transmission buffer.

Since the * symbol of the data changed to a fixed length code and transmitted in this way corresponds to the pattern and the difference, it is performed by detecting the pattern + h (3) Conventional branch technique and ij1 problem In the above system, the configuration shown in Figure 1 has been proposed as a conventional decoding circuit. In the figure, 1 is an input terminal, 2 is a buffer memory, 3 is a phase expansion circuit, and 4 is a multiplexer. , 5 is a variable length decoder, 6
is an output terminal and a 7-digit decoding code length management circuit.

Packer memory bits (for example, 8
(bits) appear in parallel. The phase expansion circuit 3 consists of 7 lip-flops, and
The incoming signals are stored alternately and the two bits are output in parallel. The multiplexer 4 receives instructions from the decoding code length management circuit 7 and selects the @code sequence starting with the code to be decoded next from among the 2-bit signals sent from the phase expansion circuit 3. Output in parallel in the form of bits.

When the multiplexer 4Fi is given an instruction (shift amount) 1 from the decoding code length management circuit 7, it shifts the bit signal to the 2 bit, for example, by 1 bit to the left by wired logic. g are output in parallel. variable length decoding tisti,
The signal system data output from the multiplexer 4 manually detects a predetermined variable length code pattern,
The decoded code is outputted to the output terminal 6, and the code length of the sold-out code is expressed in 2Mn bits and sent to the decoded code length management circuit 7. For example, if the output code has a code length of 5 bits, it is sent to the management circuit 7 in the form of "0101".

The subsequent code length f# embedding circuit 7 is composed of an (n+1) bit exciter that adds its own output value and the signal sent from the variable length decoder 5, and its output value, that is, the addition result is mutually exclusive. It represents the number of bits of the signal stored in the expansion circuit 3 up to the point in time. This adder G
et(n+1) bit binary number multiplexer 4
The signal is sent to the multiplexer 4 and used as a control signal.

Furthermore, the n-th bit i=s of the output of the decoding code length management circuit 7 is used as a clock for starting from the buffer memory 2, and is used as a clock for the (n+1)-th bit MSBF'i phase expansion circuit 3. used. Note that in the above, the bits may be considered to be 2(n+1) bits.

In order to make the explanation easier to understand, an example will be given.

Now, suppose code length is “2” and “8” for buffer memory 2.
”, “5”, “4”, ・Variable length codes such as liK
It is assumed that the data is stored and sent out from the output terminal 6 in a first-in, first-out format, n = 3, K = 2
=16.

(1) In this case, the code lengths “2”, “3”, “5”,
The first 2 bits of "4" and "6", 16 bits, are set in the free lag flop shown in the lower part of the figure, and the code length is "4".
The remaining 4 bits of ``6'' and 16 bits of ``1'', ``4'', and ``7'' are set in the 7-lip e-flop in the upper row of the diagram.
It is supplied to multiplexer 4.

(2) In this case, the added value of the (n+1) bit adder of the decoding code length management circuit 7 is [0OOOJ, and therefore the multiplexer 4 outputs 07 feet, that is, the first code length "2" without shifting the input signal. The 16 bits starting with the variable length code are supplied to the decoder 5.

(3) In this state, the variable length encoder 5 first has a code length of 1'2J.
The code is decoded and output to the output terminal 6. At the same time, the OI squarer 5 sends 7t to the (n+1) bit adder and 2
Supply the base number [0010J.

(4) As a result of kneading, the addition result Fi[0001O] is obtained by the (n+1) bit adder, and the multiplexer 4 is notified of this fact. As a result, the multiplexer 4 shifts the input signal by 2 bits, completely removes the decoded code length "2", and transfers the 16 bits to the decoder 5 as a variable code association with a code length "3". supply

(5) The variable length decoder 5 thereby post-codes the code 'fr of code length "3" and outputs it to the output terminal 6, and at the same time (n+1
) Supply the 2-overnumber "0OIIJ" to the bit adder jI.

(6) As a result, the addition result by the (n+1) bit adder becomes Fir2J +r3J, that is, "00101", and the multiplexer 4K is notified of this fact.

This includes the multi-graxer 4Fi above and 1Wlf! II
The above O! has been decoded with the K input flaw 49' shifted by 5 bits. Remove code lengths “2” and “3” to obtain code length “5”
16 bits starting with the inverted length code of - are supplied to decoding-5 (0 Supply the binary number [0101J to the n-+1) bit adder.

(8) The result of addition by the K+C(n+1) bit adder is r5J +r5J, that is, "01010 J," and the multiplexer 4 is notified of this fact.

(9) At this time, in the addition result of the (n+1) bit adder, the n-th bit, that is, the 4th bit in this case, changes to logic "1", so according to this condition, a clock is supplied to the buffer memory 2 and reading is performed. . At this time (n+
1), and in the addition result of the adder, there are (n+1) bits 0 and MSBFi logic "0" K, so 7 in the lower part of the diagram
The 16 bits corresponding to the assumed code length "3" are set in the lip 70.

(1@ In the process of (8) above, multiplexer 4
is notified of the addition result "01010 J", and the multi-grec f4 supplies 16 bits of code having the code length "4" as a priori to the decoder 5Vc in the same way as above.

(1) Variable length decoder 5Fi, which allows the code length to be 4
” is decoded and output to output terminal 6, and at the same time (n+
1) Supply the binary number "01oO" to the bit adder.

Decryption is performed as described above.

However, in this circuit, if a bit error occurs in the transmission Ayu, for example, a f-length code with code length r2J becomes code length "2".
Although it cannot be decoded, the code length is "3".

The code may be coded as t1 as a blue length code of "4".

However, even if it happens to be decoded once, the patterns do not match from the next phase sign onward, so there is a drawback that the decoding is no longer possible.

(4) One aspect of the invention The present invention has been made in view of the above points, and is therefore a bit-
It is our aim to provide a decoding circuit that can minimize the effects of interference even if it occurs.

(5) For the purpose of false creation of the invention (iiC), a modulation coded signal sequence (1) in which a special code r is inserted into a five-length code sequence at one cycle is received by a reception buffer at a constant speed, and Read in units of a predetermined bit length and hold it in a holding circuit, read out the bit position indicated by the output of the adder circuit as the first bit, decode it by t14ge according to the bit pattern, and calculate the number of bits corresponding to each bit pattern. It is input to the adder circuit and added to the previous read position, and when all the Mukuro special codes are detected, the output of the class 1 arithmetic circuit and the position of the a priori bit of the special code within the predetermined bit length are calculated. When they match or when the output of the When it is small, reading from the holding circuit is stopped until n and n' become strong, and when n/ is large, the data is read in units of the predetermined bit length until the next special code? There is no bamboo until it is detected, and at this point, the number of bits is equal to the difference between n and n, which is the sum of n, the number of bits stored in the predetermined bit length unit, n'', and the value of n' - n. This is done by a decoding circuit that imitates the fact that the transfer is completely stopped.

(6) Embodiment of the Invention In the present invention, on the transmitting side, one special code is carried by % at every fixed period.
A code t7 indicating the number of bits between special codes is entered, and each time this waiting stock code is output, the read position is corrected from the 1-way.

This will be explained below according to FIG.

8Fi control circuit in 1, 9#'i% stock sign detection circuit, 7
a.

7b, IOHOH free lag flop ELFi selector,
CM Ph ratio ms, 0RFi#7 gate, ANDI.

AND2 is an AND gate, and the same members as in Figure w71.2 are given the same symbols.

When the operation is confirmed, the variable length code string from the input terminal 1 is stored in the buffer memory 2, outputted to the flip-flop 3, and also inputted to the Va code detection circuit 9. For example, the % swimming dip number is extracted using 12 bits, and its pattern is as follows.
r 100000000001 J. When no special sign is detected, selector 5ELe- sets the output of adder xi to 7 lip-flop 7a, and inputs it to multiplexer 4 along with feedback to the adder.

On the other hand, when the detection circuit 9 detects a special code, the bit indicating the detection and the position tk of the first bit of the special code in the bits are loaded into the 7-lip-flop 1o. Then, a comparator CMP compares the output of the adder with the earlier application bit position of the special code set in the 7 lip-flop. When the output of the 0 adder is small, the comparator CMP output selector SE
At L, select the adder output and select the 7 logic flop 7.
Set aK. - When it becomes necessary to castrate or when the adder output becomes small, select the cutting edge of 7 lip flop 10 by comparison CMP output,
set, and from multiplex t4 the special code 'lkwk,
Set to variable length code string 6.

Historically, the f/f ratio output is set in flip-flop 7b. The output of the flip-flop 7b is manually inputted to the flip-flop 3.10 via the control circuit 8, the OR gate, and the AND gate ANDI'i.

When the output of the control circuit 8iJ flip-flop p-tube 8 is inputted, the process shown in FIG. 4 is performed.

In other words, (a) As shown in the figure, every n1 bits! ＃Special sign u
Assume wt-insert and send. Then, as mentioned above, when the special code UW is read from the multiplexer 4, the number of bits from the previously read special code is checked,
If it is n1 bits, Kti, 1'L & bit length fllJ of the special code is determined from the code length detection circuit in the long postcoder 5.
Make it output as follows.

As a result, the adder output becomes w, which indicates the address of the first bit of the code following the special code.

On the other hand, if the number of received bits is less than the number of transmitted bits (as shown in the bJ figure), close the AND gate AND2 'i by the difference in the number of bits (n + i), disable the clock, and disable Jl!New of the adder. .And the number of received bits is nl
When the code length detecting circuit reaches , the number of bits of the % field code is forcibly output. (e) As shown in the figure, when the number of received bits nl is larger than nl, the code length detection circuit outputs the next special code with a delay of the maximum fixed code length, in the example shown in the figure, the number of bits Kt. Output until it is, then read quickly. Then, at the moment when the %jugyo sign of Ku is detected, n+
Prohibits reading 9 by (1Dr+nx) bits.

After that, the number of bits of the special code is output.

(7) Effects of the Invention As described above, according to the present invention, a special code is inserted at a constant period, and each time this special code is detected, one consecutive address is set to a constant value. The influence of bit-i can be reduced compared to the conventional method.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the process of converting a variable length code to a fixed length code, w! , 2 is a diagram showing a conventional coder circuit, FIG. 3 is a diagram showing a decoding circuit according to the present invention, and FIG. 4 is a diagram showing the operation of the decoding circuit according to the present invention. In the figure, 2Fi=Q) family memory, 3. 7m, 7b,
10 is Furiragu 191 Tsubu, 4 Fiw Multiplexer, 5
is a variable length decoder, 7 is a decoding code length management circuit, and 8 is a control (i)
Kl (b) path 9 is a special code detection circuit.

Claims (1)

[Claims] A variable-length encoded signal string in which a special code is inserted at a fixed period into a variable-length code string is received at a constant speed, read out in units of a predetermined bit length from the reception buffer, and held in a holding circuit. , the bit position indicated by the output of the adder circuit is set as the first bit, and is decoded by a decoder according to the pit no (turn), and the number of bits corresponding to each pit no (turn) is input to the adder circuit to calculate the previous bit. When adding to the extraction position and detecting the tf% special code, it is actually transmitted when the adder circuit output and the special code become the first pitch by comparison. When n' is smaller than n, which is less than the number of bits n that should be included in between, the output from the holding circuit is stopped until n and n' are equal. Read in predetermined bit length units until the next special code is detected, and at this point add n, the number of bits read in the predetermined bit length position n#, and the value of n' - n. The decoding circuit is designed to stop the ffa extraction when the number of bits is the difference between the given value and n.