KR100209881B1 - Memory controller in high speed variable length decoder - Google Patents

Abstract

The present invention relates to a fast variable length decoder that can be used in a high speed system such as an HD-TV system. In the fast variable length decoder of the present invention, when decoding the variable length codes inputted through the buffer, the buffer is implemented as a large-capacity memory such as a dual port memory, an asynchronous to synchronous FIFO memory, and the variable length codes stored in the memory from the interface unit. Each time a read signal is applied, a memory control device is included between the memory and the interface unit to supply data directly to the interface unit. Therefore, the data read from the memory are sequentially stored in a plurality of latches, which are internal storages of the memory control apparatus, and when a read signal is applied from the interface unit, the new valid data stored among the stored data of the plurality of latches is selected first and outputted. Therefore, it is possible to speed up the decoding of the input through the buffer and propose to apply it to the actual high speed system.

Description

Memory control device of high speed variable length decoder

1 is a block diagram schematically showing a conventional fast variable length decoder.

2 is an operation timing diagram for a FIFO memory.

3 is a block diagram showing a fast variable length decoder to which the memory controller of the present invention is applied.

4 is a table showing the input / output combined logic state of the combined logic unit in the FIG. 3 apparatus.

5 is a table showing an operating state of the memory control apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

10: FIFO memory 20: Memory controller

21: status determination means 211: combination logic unit

212: inverter 213214: latch

22, 23, 24: latch 25: multiplexer

30 interface unit 40 decoder unit

The present invention relates to a fast variable length decoder capable of providing fast decoding of a variable length code, and more particularly, to a memory (buffer) for speeding up a variable length decoder for decoding an input through a memory (buffer). A memory control apparatus of a high speed variable length decoder for controlling

Recently, technologies related to high-speed variable field decoders that can be used in high-speed systems such as high-definition television (HD-TV) systems in the development competition have been proposed. For example, US Patent No. 5,245,338, entitled "HIGH-SPEED VARIABLE-LENGTH DECODER", issued September 14, 1993, is briefly shown in FIG. Here, the fast variable length decoder is largely composed of the buffer unit 1, the interface unit 2, and the decoder unit 3, and the detailed configuration is omitted.

In order to decode the conventional fast variable length decoder shown in FIG. 1, variable length coders in the form of bit strings are input. The buffer unit 1 stores the variable length coders to be input, and the bit data corresponding to the fixed length codewords in the input order are stored in the variable length codes whenever the read signal READ is applied from the interface unit 2. Is output to the interface unit 2 at a fixed symbol clock rate. The interface unit 2 receives and accumulates the code length, which is the number of bits used for decoding, from the decoder unit 3, and accumulates the fixed-length bit data input from the buffer unit 1 and the previously input fixed-length bit data. The data in the window shifted by the accumulation result is output. The decoder unit 3 inputs a code string shifted by the decoding result code length every clock cycle, and is not yet decoded consecutively from the most significant bit MSB to the least significant bit LSB of the code immediately decoded. As bits, the whole is stored by two code lengths. The stored contents are shifted by the length of the code just decoded just before, resulting in consecutive intermediate undecoded bits as internal intermediate results. This intermediate result is fed back to form the upper code length information of the contents stored in the next clock cycle, and is compared in an internal code table to output the code length information and the decoded data when there is a corresponding code.

Here, when the buffer unit 1 is a large-capacity memory made of a synchronous FIFO, the operation is performed at the same timing as that in FIG. A valid read enable signal (FIFO_READ_ENABLE) is applied to the FIFO memory at a "low" level as shown in FIG. If a fixed length codeword for variable length decoding stored in the FIFO memory is immediately output to the interface unit 2. However, as shown in FIG. 2 (c), the output signal is not output immediately but is synchronized with the next read clock. In addition, it may be output after a predetermined clock depending on memory characteristics, which may be a detrimental factor in speeding up the variable length decoder.

Accordingly, an object of the present invention is a memory control for controlling a memory so that data can be output in response to a data request signal by independently performing data output and variable length decoding in a memory forming a buffer unit in the prior art. The present invention provides a high speed variable length decoder that can be applied to an actual high speed system.

In order to achieve the above object, a fast variable length decoder stores bit data by variable length encoding, and outputs data stored in a first-in first-out method as fixed-length bit data whenever a memory read signal is applied. A memory read signal is applied to the memory means and the memory means, and the fixed length bit data applied from the memory means is stored, and each time the read signal is applied, the next data of the currently output data is stored. And a variable length decoding means for applying a read signal to the memory control means, and variable length decoding the data applied from the memory control means.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 5 as follows.

3 is a block diagram showing a fast variable length decoder according to a preferred embodiment of the present invention. As shown, the high speed variable length decoder of the present invention is configured in the same manner as the conventional high speed variable length decoder of FIG. 1, whereas the buffer unit 1 is a large capacity memory such as a dual port memory, an asynchronous FIFO or a synchronous FIFO. In addition, the memory control apparatus 20 for controlling the memory corresponding to the present invention is further configured. The memory controller 20 has a specific circuit that varies depending on the memory used, but the overall function is the same. The configuration here is based on a synchronous FIFO. The memory controller 20 determines the status of whether or not to read data from the FIFO memory 10 and whether the read data is output or not, and the status determination means 21 and the FIFO memory 10 for controlling each configuration. Three latches 22, 23, and 24 for sequentially storing data applied from the circuit, and output terminals of the three latches 22, 23, and 24 are connected to the respective input terminals, and the data input to one of the input terminals is The multiplexer 25 outputs to the interface unit 30.

In the fast variable length decoder of the present invention configured as described above, the variable length codes in the form of bit strings are input to the FIFO memory 10. The FIFO memory 10 stores variable long term inputs, and stores fixed bit data that is input first among the stored data whenever the memory read signal MEM_READ is applied from the memory controller 20. 20) The state determining means 21 of the memory control device 20 reads data from the FIFO memory 10 through the combinational logic unit 211 having a table of input / output combinational logic states as shown in FIG. It is determined whether to store in the latches 22, 23, and 24 that perform the role, and whether to output to the interface unit 30 stored in the latches 22, 23, and 24. That is, the combinational logic unit 211 reads whether the read signal READ from the interface unit 30 is valid, whether or not the data stored in the latches 22, 23, and 24 is valid, and is read one clock before from the FIFO memory 10. It is determined whether to read the next data into the latch 22 from the validity of the data. The combinational logic unit 211 includes a read signal READ output from the interface unit 30, a flag signal indicating a data storage state for each of the three latches 22, 23, and 24, and a FIFO memory ( 10) A flag signal (flag), a memory read signal (MEM_READ), and a multiplexer that receive a load enable signal (LOAD_ENABLE) for storing data read from the input signal and correspond to the input combinational logic states shown in the table shown in FIG. And outputs a select signal MUX_SELECT to be applied to the signal 25). For example, the combinational logic unit 211 has three input signals when the input flag signal is “000”, the load enable signal LOAD_ENABLE is “1”, and the read signal READ is “0”. The current state is determined when there is no data stored in the two latches 22, 23, and 24, data input from the FIFO memory 10 is stored in the latch 22, and there is no data request from the interface unit 30. . Thus, the combinational logic unit 211 outputs the flag signal as "001", the memory read signal MEM_READ as "0", and the multiplexer selection signal MUX_SELECT as "000". Here, the flag signal is fed back to the combinational logic unit 211 through the latch 214. The memory read signal MEN_READ is input to the FIFO memory 10 and inverted through the inverter 212, and then output as a load enable LOAD_ENABLE through the latch 213. The load enable signal LOAD_ENABLE is inputted to the latches 22, 23, and 24 and fed back to the combinational logic unit 211. In the memory controller 20, the latch 22 is fixed-length bit data output from the FIFO memory 10, the latch 23 is data from the latch 22, and the latch 24 is latched ( The data supplied from 23 is individually latched in accordance with the load enable signal LOAD_ENABLE of the status determining means 21. Meanwhile, the multiplexer 25 receiving the fixed length bit data sequentially latched through the three latches 22, 23, and 24 is first inputted according to the selection signal MUX_SELECT applied from the combinational logic unit 211. Select and output the saved data in order. In more detail with reference to FIG. 5, the combinational logic unit 211 of the memory controller 20 is output from the FIFO memory 10 in the next operation cycle when the load enable signal LOAD_ENABLE is “1”. The latch 22 receives data, the latch 22 outputs the data output from the latch 22, and the latch 24 receives the data output from the latch 23 and latches the data output to the latches 22, 23, and 24. Save your data. The flag signal is updated according to the data storage state of the current latches 22, 23, and 24, and the latches 22, 23 are applied whenever the read signal READ “1” is applied from the interface unit 30. Among the data stored in, 24, the data is first read from the FIFO memory 10 and selected from the stored data through the multiplexer 25 to be output to the interface unit 30. As in the case of Cycle No. 7 of FIG. 5, the combinational logic unit 211 uses the flag signal "111", the load enable signal "LOAD_ENABLE" "0", and the read signal "READ" "1". Is input and the data "ABC" is stored in the latches 22, 23 and 24 which are internal storages. For example, the combinational logic unit 211 selects the multiplexer 25 according to a predefined combinational logic state. The signal "MUX_SELECT" is outputted so that the data "A" stored in the latch 24 is selected and output during the previous cycle so that the data "B" stored in the latch 23 can be selected and output. That is, data output through the memory control device 20 changes each time a read signal READ is applied. The combinational logic unit 211 updates the flag signal with "011" to indicate that the data stored in the latch 24 is invalid data. The degree of delay in the memory controller 20 may vary depending on the characteristics of the memory used, and thus the number of latches may vary. It consists of three latches here. Data output from the memory control device 20 is input to the interface unit 30. The interface unit 30 and the decoder unit 40 operate in the same manner as mentioned above. That is, the interface unit 30 applies a read signal READ to the memory controller 20 and then decodes the fixed length bit data from the memory controller 20 and the previously input fixed length bit data. The section 40 outputs the data contained in the shifted window to the decoder section 40 according to the accumulation of the code lengths used for decoding. Here, the time point at which the new fixed length bit data is input to the interface unit 30 is when the read signal READ is activated at the beginning of a new clock cycle. In other words, the memory is directly synchronized with the read signal READ output from the interface unit 30, and the data is supplied from the memory control device 20 to the interface unit 30. The decoder unit 40 decodes and outputs data applied from the interface unit 30, and outputs the code length used in decoding to the interface unit 30.

As described above, the present invention relates to a memory control apparatus of a high speed variable length decoder, which is stored in a buffer of a large capacity memory such as a dual port memory, an asynchronous to synchronous FIFO, and a buffer to decode the variable length coded data. The memory is controlled so that the data can be read out from the memory (buffer) and the variable-length decoding can be performed independently. Provides a fast variable length decoder that can be applied to the system.

Claims (6)

1. A high speed variable length decoder comprising: memory means for storing bit data by variable length encoding and outputting data stored in a first-in first-out method as fixed length bit data each time a memory read signal is applied; A memory read signal is applied to the memory means, and the fixed length bit data applied from the memory means is stored, and each time the read signal is applied, the memory read signal is changed into the next data of the currently output data among the stored data. Memory control means; And variable length decoding means for applying a read signal to the memory control means and for variable length decoding the data applied from the memory control means. 2. The memory control apparatus of claim 1, wherein the memory means is a large capacity memory such as a dual port memory, an asynchronous FIFO memory, a synchronous FIFO memory, or the like. 2. The apparatus of claim 1, wherein the memory control means comprises: a plurality of latches for sequentially latching and storing data applied from the memory means; A multiplexer which receives data output from the plurality of latches, selects the data output according to the input selection signal, and outputs the data to the variable length decoding means; And whether or not to output data to the variable length decoding means and whether to read data from the memory means according to whether a read signal is input from the variable length decoding means and whether data is stored in each of the plurality of latches. A memory control apparatus for a high speed variable length decoder, comprising status determination means. 4. The apparatus of claim 3, wherein the state determining means inputs a read signal of the variable length decoding means, a flag signal indicating a data storage state of each of the plurality of latches, and a load enable signal for latching the plurality of latches. A combinational logic section for outputting a memory read signal of the memory means, a selection signal of the multiplexer, and an updated flag signal in accordance with the combination; A latch which latches the updated flag signal and feeds it back to the combinational logic unit; An inverter for inverting the state of the memory read signal; And a latch configured to latch a memory read signal whose state is inverted in the inverter, output a load enable signal to each of the latches, and a feedback input feedback to the combinational logic unit. Device. 5. The apparatus of claim 4, wherein the flag signal indicates whether valid data to be used for decoding in the variable length decoding means is stored in each of the plurality of latches, and the first valid signal stored first by a read signal applied from the variable length decoding means. A memory control device of a high speed variable length decoder, wherein the state is updated accordingly whenever data is output. 4. The memory controller of claim 3, wherein the memory control means outputs new data in synchronization with the initial stage of the clock when a read signal output from the variable length decoding means is applied. .