JP2762528B2 - Transmission line encoding / decoding method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission line encoding / decoding method for preventing a predetermined number of “0” s from continuing in digital data transmitted to a transmission line. Things.

[Conventional technology]

In a communication device in which timing information is extracted from digital data received from a transmission line and an operation clock is set based on the timing information, if "0" continues in data from the transmission line, the timing information is received on the receiving side. Since the data cannot be extracted, it is necessary to limit the number of consecutive “0” on the transmission side. For example, US AT & T Publication 62411
Defines the situation of continuous "0" as follows.

(1) Do not transmit continuous "0" for 16 bits or more. (2) At any time, the width of 8 * (n + 1) bits must include "1" for n bits or more (n = 1 to 1).
23) Therefore, conventionally, for example, Bit-7 as shown in the application note of Rockwell's LSIR 8070 (Document No. 29300N23; Order No. 323 September 1986).
Using a technique called stuffing, continuous "0" was prevented. This means that the transmission data is slotted (1 slot =
When the data bits of the slot are all "0", the above condition is satisfied by forcibly transmitting the seventh bit of the slot as "1". is there. FIG. 14 is an explanatory diagram showing the encoding by the bit-7 stuffing. FIG. 14 (a) is the transmission data before processing, FIG. 14 (b) is the transmission clock, and FIG. 14 (c) is The transmission data sent to the transmission line after the Bit-7 stuffing process is shown. FIG. 14 (c) is transmitted at the rising timing of the transmission clock of (b). Here, one slot is composed of 8 bits,
One frame is composed of 24 slots, and a frame bit (F) is added at the beginning of each frame.
FIG. 14 shows from slot 23 to the beginning of slot 1 of the next frame. As is clear from FIG. 14, the transmission data before processing is monitored in units of slots, and if a bit constituting a slot such as slot 23 has "1", the data is transmitted as it is. If all the bits forming the slot are "0" as shown in FIG. 14, a bit stuffing process for forcibly replacing the seventh bit B7 of the slot with "1" is performed, and FIG. Obtaining the transmission data of c) satisfies the above-mentioned "0" continuous restriction condition.

[Problems to be solved by the invention]

As described above, in the conventional transmission line encoding / decoding method,
If all bits of an arbitrary slot are “0”, a predetermined one bit is forcibly replaced by “1” on the transmitting side, so that when the original data is all “0”, the predetermined one bit is replaced. One slot at the time of replacement is the same as one slot when the original data is originally "1" only in the predetermined bit. At the receiving side of this data, the original data is any one. There was a problem that it was not possible to judge whether there was, and as a result, a data error occurred. Therefore, in order to realize transparent data transmission, it is necessary to leave a predetermined bit for each bit slot for each slot, so that the data transmission speed is smaller than the transmission speed of the transmission line, for example, 1 bit. If the slot is composed of 8 bits, the speed is limited to 7/8 of the transmission line speed, and there is a problem that the line use efficiency is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a transmission line coding / decoding method capable of preventing a predetermined number of "0" continuations without lowering the line efficiency. I do.

[Means for solving the problem]

The transmission line coding / decoding method according to the present invention is characterized in that a plurality of slots constituting one block include a slot in which all bits are "0" bits (hereinafter referred to as all "0" slots). Is set in a predetermined slot of the block, and if all the "0" slots are present, each "0" bit is replaced with the "0" bit of each "0" slot. The encoding is performed by setting a slot information bit indicating the slot position of the 0 "slot, and the overhead bit set at a predetermined position in one block in the received data is used to perform the encoding before the encoding. It is determined whether or not all the “0” slots are present, and if it is determined that all the “0” slots are present, the slots of all the “0” slots set in the received block are determined. To remove the slot information bits indicating a location, in which to carry out the decoding so as to restore full "0" slot in every slot position indicated by the slot information bits.

[Action]

In the present invention, whether or not all "0" slots exist in each slot of one block is indicated by an overhead bit. If all "0" slots do not exist, the limit is exceeded by the data as it is. In addition, transparent data transmission is possible without the occurrence of continuous "0" bits, and when all "0" slots exist, all "0" bits are replaced with "0" bits of each "0" slot. The slot information bit indicating the position of the 0 "slot is set, thereby preventing the continuation of the" 0 "bit exceeding the restriction, and indicating the position of all" 0 "slots before encoding by the slot information bit. Based on this, all “0” before encoding
Since the slot is restored, if only one bit is left in the predetermined slot of one block, transparent data transmission becomes possible, and data transmission is performed with high line use efficiency.

(Example of the invention)

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a restriction condition of continuous "0" similar to the above-mentioned conventional example, that is, "0" is not continued for 16 bits or more, and within a width of 8 * (n + 1) bits at an arbitrary time. FIG. 2 is a flowchart showing a processing procedure for encoding data to a transmission line so as to satisfy a condition that "1" s of n bits or more are included, and FIG. 2 shows a case of performing decoding at that time. 5 is a flowchart showing a processing procedure of the first embodiment. FIG. 3 is an explanatory diagram showing a data structure at the time of data encoding / decoding according to these processing procedures. In this embodiment, as shown in FIGS. 3 (a) to 3 (d), one frame is composed of a frame bit F of one bit and a data bit of 192 bits, and this data bit portion is composed of four bits.
Each block is composed of six slots, and each slot is composed of eight slots.
It is a bit.

First, the encoding processing procedure will be described based on the flowchart of FIG. 1 and with reference to the data configuration of FIG. First, the first bit in each block, in which the data bit portion of one frame is divided every 48 bits, that is, bit 1 of slot 1 is set as an overhead bit (step (1)), and then from slot 2 to slot 6 It is determined whether or not there is any "0" slot in which all bits are "0" in each slot (step (2)). If it is determined in step (2) that there are no all "0" slots, in step (3) the overhead bit is set to "1" as shown in FIG. 3 (c), and the other bits remain unchanged. One block is formed in the state. As a result, even if all bits 2 to 8 of slot 1 are "0", bit 1 is set to "1", so that slot 1 does not become all bits "0", and slot 2 to slot 6 Since all "0" slots do not exist in this block, each block always has "1" bits in this block, so that the above-mentioned "0" continuation restriction condition is satisfied and most data bits are satisfied. Is transmitted as it is, so that the line use efficiency does not decrease.

If it is determined in step (2) that all "0" slots are present in the slots 2 to 6, first, in step (4), as shown in FIG. To “0”. In addition,
FIG. 3D shows a case where all the slots 3 and 5 are all "0" slots. Next, step (5)
The initial value of the parameter n representing the number of all “0” slots in the block being processed is “1”.
Set to. Next, in step (6), the slot number obtained by binarizing and encoding the slot number of all the "0" slots as the slot information bit indicating the position of the n-th all "0" slots in the block. Set n bits 2-4. According to the example of FIG. 3 (d), the slot number "3" of slot 3, which is the first all "0" slot in the block, is represented by a binary code using a binary number (0,1). ,
1) is set to bits 2 to 4 of slot 1. Next, in step (7), it is determined whether or not all the "0" slots being processed are the last all "0" slots in the block. If it is determined that it is the last, the process proceeds to step (8), and if it is determined that it is not the last, the process proceeds to step (11). Fig. 3 (d)
In the example, since there is a slot 5 which is all "0" slots after the slot 3, the process proceeds to step (11). In step (11), bit 1 of slot (n + 1) after encoding is set to "0". In the example shown in FIG. 3D, bit 1 of slot 2 is set to "0". As shown in FIG. 3 (d), the first 8 bits following the overhead bit are information set in place of "0" of the 8 bits in slot 3, and the first 3 bits are binarized. The code (0,1,1) indicates the slot number “3” of the slot 3, and the last one bit “0” indicates that there are all the “0” slots after the slot 3. That is, because bit 1 of slot 2 is "0", the next 8-bit signal is not transmission data but binary code information set in place of the next all "0" slots. You can see that. Bits 5 to 8 of slot 1 are "1" and "0".
May be set to either. Next, at step (12), the value of the parameter n representing the number of all "0" slots in the block in which all the "0" slots being processed is within the block is increased by 1, and the process returns to step (6). In the example of FIG. 3 (d), the processing of the slot 3 which is all "0" slots is completed, and the processing shifts to the processing of the next slot 5 which is all "0" slots. In step (6), the second all "0" in the block
(1,0,1) representing the slot number "5" of the slot 5, which is a slot, by a binary code is set in bits 2 to 4 of the slot 2. In the following step (7), the slot 5 being processed is determined to be the last all "0" slot in the block, so that the process proceeds to step (8). At step (8), bit 1 of slot (n + 1) is set to "1". According to the example of FIG. 3 (d), the eight bits from bit 2 of slot 2 to bit 1 of slot 3 after encoding are set in place of "0" of eight bits of slot 5 before encoding. Since the last bit, that is, bit 1 of slot 3, is "1", slot 5 is the last all "0" slot in this block, and the bits after bit 2 of slot 3 after encoding are obtained. It can be seen that the signal is transmission data on which no conversion operation has been performed. Next, in step (9), all "0" slots in the block are deleted. That is, since the information indicating the positions of all "0" slots in the block has been set up to the stage up to step (8), if this information is transmitted, the receiving side will receive all "0" before encoding.
The eight "0" bits of all "0" slots that can be restored to the correct position and no longer need to be transmitted are released here. Finally, in step (10), the data of the slot other than all the "0" slots is followed by the bit 2 of the slot (n + 1), that is, the overhead bit in which the information of all the "0" slots is set (8 × n) Set after bit.
FIG. 3 (d) shows a data block diagram of one block after encoding in which the slots 3 and 5, which are all "0" slots, are deleted and other data are sequentially set after bit 2 of slot 3. It is. Slots 1, 2, 4, and 6 before encoding are set to slots 3, 4, 5, and 6 of the block after encoding.

As shown in FIG. 3 (d), in the block after encoding, “1” in the binary code (0,1,1) indicating slot 3
As a result, all eight bits of slot 1 are not set to "0", and all eight bits of slot 2 are set to "1" in the binary code (1, 0, 1) indicating slot 5. It cannot be 0 ". Since the processing of all "0" slots is the slot between slot 2 and slot 6, the binarized code indicating the slot number does not become (0,0,0). Therefore, no "0" slot is generated.

Also, since slots 3 to 6 in FIG. 3 (d) set slots other than all "0" slots before encoding, they do not include all "0" slots.
Accordingly, the eight bits constituting each of the slots 1 to 6 after encoding shown in FIG. 3 (d) do not become "0". Therefore, one or more "1" s are included in any continuous 16 bits, and the above-described restriction condition of continuous "0" can be satisfied.

According to such encoding, the overhead in one frame required for this purpose can be kept small while satisfying the restriction condition regarding continuous "0". For example, the above-described embodiment and the conventional bit staff described above can be used. The overhead can be reduced to 1/6 when compared with the wing method.

Since this overhead bit is set in a predetermined slot in one block, the length of one block including this overhead bit is an integral multiple of the number of bits of eight bits for one slot. For example, when the number of data bits excluding the frame bit is an integral multiple of 8 bits in the frame configuration of the transmission path as shown in FIGS. 3A and 3B, the data bit is wasted. It is possible to perform efficient data transmission without using it. This has the same effect even when the number of data bits in one frame is an integral multiple of the predetermined number of bits, even if the frame configuration is not as shown in FIGS. 3 (a) and 3 (b).

Next, the decoding procedure will be described with reference to the flowchart of FIG. 2 taking the encoded data configuration as shown in FIG. 3 (d) as an example. First, in step (21), the first bit in the received one block (48 bits) is extracted as an overhead bit, and in step (22), it is determined whether the overhead bit is "1" or "0". judge. If this is "1", it indicates that all "0" slots were not present in the block before encoding, so that in step (23), one block is constituted by using the other bits as they are as data bits. If the overhead bit is determined to be "0" in step (22), it indicates that all "0" slots exist in the block before encoding, and the process proceeds to step (24). In step (24), the initial value of a parameter n representing the number of all "0" slots being processed in the block is set to "1".

Next, at step (25), the value indicated by the binary code set in bits 2 to 4 of slot n in the block, that is, the slot number of all n-th "0" slots in the block before encoding Is stored. According to the example of FIG. 3D, the slot number indicated by the binary code (0,1,1) set in bits 2 to 4 of slot 1 is "3". The first all "0" slots in the block before encoding are found to be slot 3, and this "3" is stored.

Next, in step (26), bit 1 of slot (n + 1)
Is "1" or "0" to determine if all "0"
It is determined whether the slot is the last all "0" slot in the block. If bit 1 of slot (n + 1) is determined to be "0" in step (26), all "0" slots still exist in the block, and the process proceeds to step (28). Bit 1 of slot (n + 1) at step (26)
Is determined to be "1", there is no other "0" slot in the block, and the process proceeds to step (27). Returning to the example of FIG. 3 (d), if n = 1, then in step (26), since bit 1 of slot 2 is "0", step (28)
Proceed to. In step (28), the value of parameter n indicating the number of all "0" slots being processed is incremented by 1 in all the "0" slots being processed, and the process returns to step (25). Proceed to (26). In the example of FIG. 3D, n = 2 in step (28), and step (2)
The value indicated by the binarized code (1, 0, 1) set in bits 2 to 4 of slot 2 in step 5), that is, slot 5 of the second all "0" slot in the block before encoding Is stored as the value "5".

Next, at step (26), since bit 1 of slot 3 is "1", it indicates that there is no "0" slot thereafter.
Go to step (27). In step (27), a portion in which a binary code indicating the position of all "0" slots is set, that is, the portion following the overhead bit (8 ×
n) Bits, that is, bits 2 of slot 1 to bits 1 of slot (n + 1) are deleted, and data subsequent to bit 2 of slot (n + 1) that follows is sequentially set following the overhead bit. Reconstruct one block. However, when this sequential data is set, of the blocks to be reconstructed, 8 are set at the slot position indicated by the value stored in step (25).
According to the example shown in FIG. 3, the bits of slot 1 of the received data shown in FIG. 3 (d) are inserted by inserting "0" bits and sequentially setting data at other slot positions. The 16 bits from 2 to 1 of slot 3 are deleted, and the subsequent data from bit 2 of slot 3 to bit 8 of slot 4 are set following the overhead bit. At this point, the data setting in the block being reconstructed has been performed up to immediately before the slot 3 indicated by the value stored in the step (25), and the next eight "0" bits are set. Thereafter, slot 5 of the received data is set, and eight "0" bits are set again at the position of slot 5 of the reconstructed block. Subsequently, the remaining received data is set to one block. And the decoding is completed.

FIG. 4 is a circuit diagram of an encoder showing an example of realizing the transmission line encoding method of the present invention by an electric circuit.
The figure is a circuit configuration diagram of the decoder. In FIG.
(41) is transmission data to be subjected to channel coding, (42) is a shift register circuit for shifting this transmission data (41) by one slot in 1-bit units, and (43) is an output of the shift register circuit (42). 8 in parallel for each slot
The bit register circuit (44) uses this register circuit (4
An all-zero slot determination circuit that determines whether all eight bits output from 3) are "0", and (45) sets the output of the register circuit (43) to a frame in the absence of all "0" slots. All "0" slotless frame configuration circuit assembled into a configuration
(46) is a frame configuration circuit with all "0" slots that assembles the output of the register circuit (43) into a frame configuration when there are all "0" slots, and (47) is an all-zero slot determination circuit (47). Based on the output of 44), a selector circuit that selects either the output of the frame configuration circuit with all “0” slots (45) or the frame configuration circuit with all “0” slots (46), and (48) A parallel load shift register circuit for loading the output signal of (47) in block units and sending it out as a serial signal, (49) an encoded transmission data output from the parallel load shift register circuit (48), and (50) Is a bit clock which is a clock in a bit unit, (51) is a slot clock which is a clock in a slot unit, and (52) is a unit of code conversion.
This is a block clock output every 48 bits. (Five
3) is an output signal of the all "0" determination circuit (44), and is a signal indicating whether or not there is a slot whose eight bits are all "0" in slots after slot 2 of each block. In FIG. 5, (61) is a coded received data received from the transmission line, (62) is a shift register circuit for shifting the received data (61) by one block, that is, 48 bits. (63) is a register circuit for taking in the output of the shift register circuit (62) in block units, and (64) is taking in the first bit of each block from the output of this register (63), and the blocks are all "0" slots. "65" is the output signal of the all- "0" slot presence / absence determination circuit (64), which indicates the presence / absence of all "0" slots, and (66) is the all-zero If there is a “0” slot, one slot of “0” is inserted into all the “0” slots based on the binarization code of the slot information bit set in that block, and this binarization is performed. By removing the code The “0” replacement circuit for restoring the data string before the conversion is performed. (66) A selector circuit for selecting one of the output signals, (68) a delay circuit for delaying the block clock (52) by several bits, and (69) a block clock (5) via this delay circuit (68).
According to (2), the output signal of the selector circuit (67) is loaded in block units, and the output signal is output at the timing of the bit clock (50).
0) is decoded reception data output from the parallel load shift register circuit (69).

FIG. 6 is a timing chart showing the timing of each signal in the encoder shown in FIG. 4. (41b) is an enlarged view of the transmission data (41a) by one block, and (54) is a timing chart. This is a frame pulse for indicating the boundary of 192 bits.

In the encoder and decoder having such a configuration, the encoding operation will be described first. In FIG. 4, the transmission data (41) is converted into a parallel signal in slot units by a shift register circuit (42) and a register circuit (43). Is converted to The outputs of the register circuit (43) are all 8 bits, including the frame configuration circuit (45) without all "0" slots, the frame configuration circuit (46) with all "0" slots, and the "0" slot determination circuit (44). It is taken in by each. The frame configuration circuit (45) without all “0” slots sets the first bit of slot 1 to “1” as shown in the block configuration without all “0” slots shown in FIG. The data bits are sequentially set in slot units to form a block.

On the other hand, the frame configuration circuit with all “0” slots (46)
Is 1 when there are all "0" slots shown in FIG. 3 (d).
First, as shown in the data structure of the block, the first bit of slot 1 is set to "0". Further, based on the output signal (53) of all "0" slot determination circuits (44) for each slot from slot 2 to slot 6, all 8 bits constituting the slot are "0", that is, all "0" slots. , The binary code indicating the slot number of the slot is sequentially set in the slot following the overhead bit as shown in FIG. 3 (d), and all the "0" slots are formed. The data, that is, the output of the register circuit (43) which is all "0" is not written into the block, and if the slot is not all the "0" slot, the data constituting the slot, that is, the register circuit (43) One block is constructed by sequentially packing the output as it is in step 43) into the slot following the slot in which the binary code is set.

The all "0" slot determination circuit (44) determines whether all of the 8-bit signals stored in the register circuit (43) are "0" for each slot after slot 2 of each block, and also determines whether the block is "0". If there is at least one slot of slot “0” with respect to slot 2 and subsequent slots, the output (53) notifies the frame construction circuit (46) and selector circuit (47) with all “0” slots. I do.

The selector circuit (47) judges whether or not all the "0" slots have been obtained after the slot 2 in the block based on the output signal (53) of the all "0" slot determination circuit (44). When there is no slot of “0”, the output of the frame configuration circuit (45) without all “0” slots is output. When there is all “0” slot, the frame configuration circuit with all “0” slots (45) is output. The output of (46) is selected and output to the parallel load shift register circuit (48).

The parallel load shift register circuit (48) takes in the output signal of the selector circuit (47) by the block clock (52) and outputs a coded transmission signal (49) at the timing of the bit clock (50). The block (52) resets the output of the all "0" slot determination circuit (44) and prepares for the next block.

In this way, in the encoder shown in FIG. 4, the input transmission data (41) is fetched in slot units, and all the "0" slot determination circuits (44) determine whether or not all the data are "0" in slot units. ), And the "0" -slot-free frame forming circuit (45) and the "0" -slot-containing frame forming circuit (46) form a block-by-block frame in each case. Then, the outputs of both frame constituent circuits (45) and (46) are selected by a selector circuit (47) controlled by the output (53) of all "0" slot determination circuits (44), and the outputs are parallelized in block units. The signal is transmitted to the load shift register circuit (48), converted into a serial form, and output as a signal encoded as transmission data (49).

Next, the decoding operation in the decoder shown in FIG. 5 will be described. The encoded received data (61) is shifted to the shift register circuit (62) in units of one bit, and is taken into the register circuit (63) in units of one block. The output of the register circuit (63) is sent to the selector circuit (67) and the “0” replacement circuit (66)
It is sent to the slot presence / absence determination circuit (64). The "0" replacement circuit (66) includes all "0" s as shown in FIG.
It decodes the coded data in the presence of a slot. First, the contents of bits 2 to 4 of block 1 in the received data are interpreted as the slot numbers of the first all "0" slots, and are indicated by these numbers. After inserting an 8-bit "0" at the position of the slot thus set, if the bit 1 of the slot 2 is "1", the operation of restoring all the "0" slots is terminated and the slot 2 is returned.
If bit 1 of this bit is "0", the next entire "0" slot is restored by referring to bits 2 to 4 of slot 2 following this bit. In this way, the restoring operation of all the "0" slots is repeated until the bit 1 of the slot (n + 1) is determined to be "0", and the restoration of all the "0" slots is determined by determining the bit 1 to be "0". When the processing is completed, each bit from the bit 2 of the slot 1 to the bit 1 of the slot (n + 1) in which all the "0" slot information is set is deleted, and the data after the bit 2 of the slot (n + 1) is overhead. Subsequent to the bit, block data before encoding is restored by sequentially setting all "0" slots to slots other than the restored slot, and this is output to the selector circuit (67). On the other hand, the all- "0" slot presence / absence determination circuit (64) takes in the first bit of each block, determines whether or not the block includes all "0" slots, and outputs the determination result to the output signal (65). To the selector circuit (67).

Based on the output signal (65), the selector circuit (67) outputs the output signal from the register circuit (63) if the block does not have all the "0" slots, and all the "0" slots in the block. If there is, the decoded signal from the "0" replacement circuit (66) is selected. The output of the selector circuit (67) is fetched by the parallel load shift register circuit (69) at a timing obtained by delaying the block clock (52) by several bits in the delay (68). This is output as decoded reception data (70) at the timing of the bit clock (50).

In this way, in the decoder shown in FIG. 5, the input received data (61) is fetched in units of blocks, and the fetched signal is decoded in the "0" replacement circuit (66) as if there are all "0" slots. Become Then, the overhead bit at the head of the block is converted to a "0" slot presence / absence determination circuit (6
4), all “0” slots in the block are present,
Judgment is made, and if not, the output of the register circuit (63) is
If there is, the output of the decoded "0" replacement circuit (66) is selected, and this is output to the parallel load shift register circuit (69).
And decrypts it by serially outputting it.

In the above embodiment, the overhead bit is located at the beginning of the 48-bit block as shown in FIGS. 3 (c) and 3 (d). However, as shown in FIGS. It may be arranged at other positions inside.

In the above embodiment, as shown in FIGS. 3 (c) and (d), the slot number of all n-th "0" slots in the block is converted into a binary code and the bit 2 of the slot n is used. However, as shown in FIGS. 8 (c) and 8 (d), other bits such as bits 4 to 6 of slot n may be set.

Further, in the above embodiment, as shown in FIG. 3 (d), when the slot numbers of all the "0" slots are converted into binary codes, the slot numbers represented by binary numbers are used as they are. The correspondence between the slot numbers and the binary numbers is not limited to this, as shown in FIG. 9 (a). For example, as shown in FIG. 9 (b), a binary code and a slot number are paired. You may make it correspond to one. At this time, if the binarized code (0,0,0) is used, all slots including the binarized code after encoding may become “0”, so (0,0,0) Must be avoided.

Further, in the above embodiment, as shown in FIG. 3, one frame of data consisting of 193 bits is divided into four parts and divided into four parts.
Bits, ie, 6 slots, were taken as one block, but
If the bits indicated by the crosses in FIG. 4D are effectively used, 128 slots, ie, 102 slots, as shown in FIG.
Up to four bits can be one block. This is a binary code indicating the slot number of all “0” slots instead of the 8-bit “0” of all “0” slots, and all the “0” s.
When setting the information indicating whether or not the slot is the last all "0" slot in the block, the binary code indicating the slot number of all "0" slots contains all "0" s out of 8 bits. 1 of information indicating whether the slot is the last in the block
Since 7 bits excluding the bit can be used, 2 bits can be used.
This is because up to 7 = 128 slots can be represented.
In this case, since it is sufficient to provide one bit per block, one bit per 128 slots is sufficient, and the overhead bit is smaller than that in the above-described embodiment when viewed from one frame as a whole. The above-described “0” continuous regulation condition is satisfied.

When applied to the actual frame configuration, for example,
As shown in the figure, a 193-bit frame used in the U.S. T1 line can be used as one block as it is, and also used in the U.S. T2 line as shown in FIG.
A frame having a 789-bit configuration can also be formed as one block, and in this case also, the above-mentioned "0" continuous restriction condition can be satisfied only with a 1-bit overhead bit.

Also, in the above embodiment, as shown in FIG. 3 (d), the slot 1 includes an overhead bit, and even if all other bits are "0" bits, the overhead bit is used. Since the "0" continuation is prevented, all the slots 1 are excluded from the determination target of whether or not all the slots are "0" as shown in step (2) of FIG. It may be included in the determination target of the “0” slot. FIG. 13 shows an example of the configuration of coded data in the case where slot 1 is the object of determination of all "0" slots and slot 1 is all "0" slots.

In the above embodiment, the binary code is used as the slot information bit indicating the position of all "0" slots. However, for example, a plurality of bits having the same number as the number of slots of one block are prepared, and each bit is prepared. Correspond to each slot, and check whether each slot is all "0" slots or "1" of each bit.
Alternatively, a slot information bit represented by "0" may be set as a slot information bit, and may be set in place of all the "0" slots. In this case, the same slot information bit as the number of all "0" slots is transmitted redundantly, and the "0" continuation is prevented by this slot information bit.

〔The invention's effect〕

As described above, according to the present invention, all "0" s
An overhead bit indicating whether or not a slot exists is set in a predetermined slot of each block. If all “0” slots exist, each “0” slot is replaced with each “0” slot. Since the encoding is performed by setting the slot information bit indicating the position of the slot, the position of all “0” slots is transmitted to the receiving side by using the slot information bit, and the restoration of all the “0” slots can be accurately performed. As a result, the slot information bit prevents the continuation of "0" bits, so that there is an effect that completely transparent data transmission can be performed with high transmission efficiency while preventing the continuation of "0" bits.

[Brief description of the drawings]

FIG. 1 is a flow chart showing an encoding processing procedure according to an embodiment of a transmission line encoding / decoding method of the present invention, and FIG. 2 is a flow chart showing a decoding processing procedure thereof.
FIG. 3 is an explanatory diagram showing a data structure when data is encoded / decoded according to these processing procedures, and FIG. 4 is a circuit configuration of an encoder showing an example when the present invention is implemented by an electric circuit. FIG. 5 is a circuit diagram of the decoder, FIG. 6 is a time chart of each signal in the encoder of FIG. 4, and FIGS. 7 to 13 are encodings according to another embodiment of the present invention. FIG. 14 is an explanatory diagram showing a data configuration at the time of decoding / decoding, and FIG. 14 is an explanatory diagram showing a data configuration in a conventional transmission line encoding / decoding system. In the figure, (41) is transmission data before encoding, (42) is a shift register circuit, (43) is a register circuit, (44) is all "0" slot determination circuits, and (45) is no "0" slot. Frame configuration circuit, (46) is a frame configuration circuit with all "0" slots, (47) is a selector circuit, (48) is a parallel load shift register circuit, (49) is encoded transmission data, and (61) is Received data before decoding, (62) is a shift register circuit, (63) is a register circuit, and (64) is all "0".
Slot presence / absence judgment circuit, (66) is "0" replacement circuit, (67)
Is a selector circuit, (68) is a delay circuit, (69) is a parallel load shift register circuit, and (70) is received data after decoding. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] An overhead bit indicating whether or not there are all "0" slots in which all bits are "0" bits among a plurality of slots constituting one block having a predetermined data length is set in a predetermined slot of the block. When all the “0” slots are present, the slot information bit indicating the position of each of the “0” slots and the last slot in the block are replaced with the “0” slots. A bit indicating whether or not all of the slots are “0” slots, sequentially following the overhead bits. 2. It is determined whether or not all “0” slots exist in a block before encoding based on overhead bits set at a predetermined position in one block of a received predetermined data length. "When it is determined that a slot exists, the slot information sequentially set following the overhead bit in the received block and whether or not the slot is the last all“ 0 ”slots in the block are determined. A transmission path decoding method characterized by restoring all "0" slots at the positions of all "0" slots specified by indicated bits.