WO2015155242A1 - 2-wire differential-end bus transceiver system based on 12c-bus, and associated method for communication of 2-wire differential-end bus - Google Patents

2-wire differential-end bus transceiver system based on 12c-bus, and associated method for communication of 2-wire differential-end bus Download PDF

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Publication number
WO2015155242A1
WO2015155242A1 PCT/EP2015/057622 EP2015057622W WO2015155242A1 WO 2015155242 A1 WO2015155242 A1 WO 2015155242A1 EP 2015057622 W EP2015057622 W EP 2015057622W WO 2015155242 A1 WO2015155242 A1 WO 2015155242A1
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WIPO (PCT)
Prior art keywords
master
slave
differential
signal
single wire
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PCT/EP2015/057622
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French (fr)
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Julia Zhang
Jian QING
Zhongmeng CHEN
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Nxp B.V.
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Publication of WO2015155242A1 publication Critical patent/WO2015155242A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation

Definitions

  • 2-wire differential-end bus transceiver system based on I2C-bus, and associated method for communication of 2-wire differential-end bus
  • This disclosure relates to 2-wire differential-end bus based on I2C-bus.
  • a 2-wire differential-end bus transceiver system comprising: an I2C master, a master transceiver, a differential system, a slave transceiver and an I2C slave, wherein the master transceiver is adapted to encode master data SDA and master clock SCL received from I2C master using Manchester code, generate master single wire signal and transfer it to the differential system, the master transceiver is also adapted to decode Manchester-encoded slave signal received from the differential system and transfer the decoded slave data to I2C master; the differential system is adapted to transform the master single wire signal to differential signal and transfer it, then transform it back to master single wire signal and send it to the slave transceiver, the differential system is also adapted to transform the slave single wire signal to differential signal and transfer it, then transform it back to the slave single wire signal and send it to the master transceiver; the slave transceiver is adapted to encode slave data received from I2C slave using Manchester code, generate slave single wire signal
  • the differential system comprises a first differential circuit, a second differential circuit and differential wire between them, the first differential circuit is adapted to transform the master single wire signal to the differential signal and transform it back to the slave single wire signal, the differential wire is adapted to transfer the differential signal, and the second differential circuit is adapted to transform the slave single wire signal to differential signal and transform it back to the slave single wire signal.
  • a 2-wire differential-end bus master transceiver comprising: a master encode clock generator adapted to receive system clock of master transceiver and master clock, generate master encoding clock by sampling the master clock by system clock of master transceiver; a master Manchester encoder adapted to encode the received master encoding clock and master data using Manchester code, generate master single wire signal and output it; a master clock recovery adapted to recover slave clock according to the system clock and slave single wire signal; and a master Manchester decoder adapted to decode the slave single wire signal and output the decoded slave data.
  • the master Manchester encoder is further adapted to generate I2C master clock prolong control.
  • a 2-wire differential-end bus slave transceiver comprising: a slave clock recovery adapted to generate slave encoding clock according to master single wire signal received from the I2C master, and generate the recovered master clock; a master Manchester encoder adapted to encode the received master encoding clock and master data using Manchester code, generate master single wire signal and output it; and a master Manchester decoder adapted to decode the master single wire signal and generate master data.
  • the master I2C timing sequence generator is adapted to ensure the recovered master clock and decoded master data satisfy with I2C standard timing sequence requirement.
  • a method for communication of 2-wire differential-end bus from I2C master to I2C slave comprising: transmitting master data and master clock; encoding the master data and master clock using Manchester code, and generating master single wire signal;
  • a method for communication of 2-wire differential-end bus from I2C slave to I2C master comprising: transmitting slave data; encoding the slave data using Manchester code, and generating slave single wire signal; transforming the slave single wire signal to differential signal and transferring it; transforming the differential signal back to slave single wire signal; decoding the slave single wire signal.
  • Manchester code is Manchester-II Bi-phase code.
  • FIG. 1 shows a 2-wire differential-end bus transceiver system according to one or more embodiments
  • FIG. 2 shows a master transceiver according to one or more embodiments
  • FIG. 3 shows a slave transceiver according to one or more embodiments
  • FIG. 4 shows a graph of Manchester encoding
  • FIG. 5 shows a graph of 12 C master START command encoding
  • FIG. 6 shows a graph of 12 C master STOP command encoding
  • FIG. 7 shows a graph of I2C slave ACK response encoding
  • FIG. 8 shows a graph of 12 C slave NACK response encoding
  • FIG. 9 shows a graph of I2C master ACK response encoding
  • FIG. 10 shows a graph of 12 C master NACK response encoding.
  • FIG. 1 shows a 2-wire differential-end bus transceiver system 100 according to one or more embodiments.
  • the 2-wire differential-end bus transceiver system comprises an I2C master 101, a master transceiver 102, a differential system 103, a slave transceiver 104 and an I2C slave 105.
  • the 12 C master 101 and the master transceiver 102 transfer data SDA and master clock SCL to each other.
  • Master clock SCL is bus clock
  • the master transceiver 102 can encode master data SDA and master clock SCL received from the I2C master 101 using Manchester encoding, generate master single wire signal (MD) and transfer it to the differential system 103; the master transceiver 102 can also decode Manchester-encoded slave single wire signal (MD) received from the differential system 103 and transfer the decoded slave data to the I2C master 101.
  • MD master single wire signal
  • the differential system 103 can transform the master single wire signal to differential signal and transfer it, then transform it back to master single wire signal and send it to the slave transceiver 104; the differential system 103 can also transform the slave single wire signal to differential system and transfer it, then transform it back to the slave single wire signal and send it to the master transceiver 102.
  • the differential system 103 can transfer differential signal into single wire signal for the Manchester decoder 204 to decode Manchester-coded the single wire signal from slave transceiver.
  • Manchester encoder 204 can encode I2C master data SDA and master clock SCL into a single wire signal, then the differential 103 can transfer the single wire signal into 2-wire differential signal for transaction to the Manchester decode 204.
  • the slave transceiver 104 can encode slave data received from I2C slave 105 using Manchester code, generate slave single wire signal and transfer it to the differential system 103, the slave transceiver 104 can also decode Manchester-encoded master signal received from the differential system 103, generate the recovered master clock and transfer the decoded master data and recovered master clock to I2C slave 105.
  • the differential system 103 comprises a first differential circuit 107, a second differential circuit 109 and differential wire 108 between them.
  • the first differential circuit 107 can transform the master single wire signal to the differential signal and transform it back to the slave single wire signal; the differential wire 108 can transfer the differential signal, and the second differential circuit 109 can transform the slave single wire signal to differential signal and transform it back to the slave single wire signal.
  • the structure of master transceiver 102 and slave transceiver 104 in 2-wire differential-end bus system according to one or more embodiments are showed in FIG. 2 and FIG. 3 as below.
  • FIG. 2 shows a master transceiver 102 according to one or more embodiments.
  • Master transceiver 102 comprises a master encode clock generator 201 , master clock recovery 202, and master Manchester encoder 203 and decoder 204.
  • the master encode clock generator 20 lean receive system clock of master transceiver and master clock, and generate master encoding clock by sampling the I2C master clock.
  • the frequency of the master encoding clock is twice that of the master clock.
  • the master Manchester encoder 203 can encode the received master encoding clock and master data using Manchester code, generate master single wire signal and output it, and generate I2C master clock stretching control. A clock stretching control is used to postpone the transmission of master data when the master data has been transferred and the Manchester coding has not been done.
  • the Manchester encoder 203 may generate EN signal which is used to control the transmission direction of the differential-end bus transceiver system 100.
  • the Manchester encoded master single wire signal is generated by the master encode clock generator 201 and the master Manchester encoder 203.
  • the master single wire signal is transformed to 2-wire differential signal by the second differential circuit 109 and is transferred to the first differential circuit 107. Then the 2-wire differential signal is transferred to the second differential circuit 109 by the differential wire 108.
  • the second differential circuit 109 can transform the 2-wire differential signal back to the master single wire signal, then transfer it to the slave transceiver 104, so that the I2C master 101 and slave 105 can communicate with each other.
  • the master clock recovery 202 can sample the slave single wire signal and recover slave clock according to the system clock and slave single wire signal, in order to synchronize the master transceiver and slave transceiver system clock.
  • the master Manchester decoder 204 can receive the Manchester encoded slave single wire signal, the recovered salve clock, master transceiver system clock, decode the slave single wire signal and output the decoded slave data.
  • the Manchester encoded slave single wire signal is transformed to differential signal by the second differential circuit 109.
  • the differential signal is transferred to the first differential circuit 107 by the differential wire 108.
  • the first differential circuit 107 can transform the differential signal back to the slave single wire signal, then transfer it to the master transceiver 102.
  • the master decoder 204 can decode the slave single wire signal, generates decoded I2C slave data and transfers it to I2C master 101.
  • FIG. 3 shows a slave transceiver 104 according to one or more embodiments.
  • the slave transceiver 104 comprises a master I2C timing sequence generator 301 , a slave clock recovery 302, a master Manchester encoder 303, and a master Manchester decoder 304.
  • the slave clock recovery 302 can generate slave encoding clock which has a frequency twice that of the master clock according to master single wire signal received from the I2C master, and generate the recovered master clock.
  • the master Manchester encoder 303 can receive slave transceiver system clock, I2C slave data SDA and slave coded clock, encode the received master encoding clock and master data using
  • the second differential circuit 109 can transform the single wire signal to differential signal. Then the differential signal is transferred to the first differential 107 circuit by the differential wire 108. The first differential circuit 107 can transform the differential signal back to the slave single wire signal, then transfer it to the master transceiver 102, so that the I2C master 101 and slave 105 can communicate with each other.
  • the master Manchester decoder 303 can receive slave transceiver system clock, recovered master clock and master single wire signal, decode the master single wire signal and generate master data.
  • the master I2C timing sequence generator 301 can receive slave transceiver system clock, recovered master clock and decoded master data, buffer the decoded master data to ensure the recovered master clock and decoded master data satisfy with I2C standard timing sequence requirement, i.e. the master data sent to the I2C slave and master clock satisfy the I2C standard timing requirement.
  • the Manchester encoded master single wire signal is generated.
  • the master single wire signal is transformed to differential signal by the first differential circuit 107. Then the differential signal is transferred to the second differential circuit 109 by the differential wire 108.
  • the second differential circuit 109 can transform the differential signal back to the master single wire signal, then transfer it to the slave transceiver 104.
  • the slave decoder 304 can decode the master single wire signal, generate decoded I2C master data and recovered master clock and transfer them to the I2C timing sequence generator 301.
  • the I2C timing sequence generator 301 can transfer the decoded I2C master data and recovered master clock to I2C slave 105.
  • FIG. 4 shows a graph of Manchester encoding.
  • Manchester encoding provides a self-clocking waveform that incorporates the data bit sequence. Therefore, it is not a separate clock signal because the clock has been embedded in the data.
  • a logical "1 " is a positive pulse followed by a negative pulse
  • logical "0" is a negative pulse followed by a positive pulse.
  • the graph is shown as FIG.4.
  • Manchester coded data "1" is a positive pulse followed by a negative pulse
  • Manchester coded data "0” is a negative pulse followed by a positive pulse.
  • FIG. 5-10 illustrate several examples of encoding.
  • FIG. 5 shows a graph of I2C master START command encoding.
  • the master encoding clock is generated by sampling the I2C master clock SCL.
  • the frequency of the master encoding clock is twice that of the master clock.
  • SCL is positive pulse and SDA changes from positive pules to negative pulse
  • the START command starts.
  • SDA can be transferred continually.
  • the code is a sync header and is followed in 1 SCL period low level.
  • FIG. 6 shows a graph of master STOP command encoding.
  • the master encoding clock is generated by sampling the I2C master clock SCL.
  • the frequency of the master encoding clock is twice that of the master clock.
  • SCL is positive pulse and SDA changed from negative pulse to positive pulse
  • the STOP command starts.
  • SDA can be transferred again.
  • the code is a sync header and is sequentially followed in 2 SCL periods low level and 1 SCL period high level.
  • FIG. 7 shows a graph of slave ACK response encoding.
  • the code is a sync header and is followed in 1 SCL period low level.
  • FIG. 8 shows a graph of slave NACK response encoding.
  • the code is a sync header and is followed in 1 SCL period high level.
  • FIG. 9 shows a graph of master ACK response encoding.
  • the code is a sync header and is followed in 1 Manchester data bit 0.
  • FIG. 10 shows a graph of master NACK response.
  • the code is a sync header and is followed in 1 Manchester data bit 1.
  • a method for communication of 2-wire differential-end bus from I2C master to I2C slave comprising: transmitting master data and master clock; encoding the master data and master clock using Manchester code, and generating master single wire signal;
  • a method for communication of 2-wire differential-end bus from I2C slave to I2C master comprising: transmitting slave data; encoding the slave data using Manchester code, and generating slave single wire signal; transforming the slave single wire signal to differential signal and transferring it; transforming the differential signal back to slave single wire signal; decoding the slave single wire signal.
  • Manchester code is Manchester-II Bi-phase code.

Abstract

There is disclosed a 2-wire differential-end bus transceiver system comprising: an I2C master, a master transceiver, a differential system, a slave transceiver and an I2C slave, wherein the master transceiver is adapted to encode master data SDA and master clock SCL received from I2C master using Manchester code, generate master single wire signal and transfer it to the differential system, the master transceiver is also adapted to decode Manchester-encoded slave signal received from the differential system and transfer the decoded slave data to I2C master;the differential system is adapted to transform the master single wire signal to differential signal and transfer it, then transform it back to master single wire signal and send it to the slave transceiver, the differential system is also adapted to transform the slave single wire signal to differential signal and transfer it, then transform it back to the slave single wire signal and send it to the master transceiver;the slave transceiver is adapted to encode slave data received from I2C slave using Manchester code, generate slave single wire signal and transfer it to the differential system, the slave transceiver is also adapted to decode Manchester-encoded master signal received from the differential system, generate the recovered master clock and transfer the decoded master data and recovered master clock to I2C slave. Associated methods are also disclosed.

Description

2-wire differential-end bus transceiver system based on I2C-bus, and associated method for communication of 2-wire differential-end bus
BACKGROUND
This disclosure relates to 2-wire differential-end bus based on I2C-bus.
Traditional I2C-bus communication needs two wires, which may not be suitable long-distance cable in industrial applications. This may result in noise and ground offsets in the popular I2C-bus electronic design.
SUMMARY
There are disclosed herein methods and apparatus as defined in the independent claims.
According to one aspect of the present disclosure, there is provided a 2-wire differential-end bus transceiver system comprising: an I2C master, a master transceiver, a differential system, a slave transceiver and an I2C slave, wherein the master transceiver is adapted to encode master data SDA and master clock SCL received from I2C master using Manchester code, generate master single wire signal and transfer it to the differential system, the master transceiver is also adapted to decode Manchester-encoded slave signal received from the differential system and transfer the decoded slave data to I2C master; the differential system is adapted to transform the master single wire signal to differential signal and transfer it, then transform it back to master single wire signal and send it to the slave transceiver, the differential system is also adapted to transform the slave single wire signal to differential signal and transfer it, then transform it back to the slave single wire signal and send it to the master transceiver; the slave transceiver is adapted to encode slave data received from I2C slave using Manchester code, generate slave single wire signal and transfer it to the differential system, the slave transceiver is also adapted to decode Manchester-encoded master signal received from the differential system, generate the recovered master clock and transfer the decoded master data and recovered master clock to I2C slave.
By providing a 2-wire differential-end bus transceiver which mixes clock into data line, it may be possible to reduce noise and ground offsets, and the transceiver may be fully compatible to I2C protocol.
In one or more embodiments, the differential system comprises a first differential circuit, a second differential circuit and differential wire between them, the first differential circuit is adapted to transform the master single wire signal to the differential signal and transform it back to the slave single wire signal, the differential wire is adapted to transfer the differential signal, and the second differential circuit is adapted to transform the slave single wire signal to differential signal and transform it back to the slave single wire signal.
According to another aspect of the present disclosure, there is provided a 2-wire differential-end bus master transceiver comprising: a master encode clock generator adapted to receive system clock of master transceiver and master clock, generate master encoding clock by sampling the master clock by system clock of master transceiver; a master Manchester encoder adapted to encode the received master encoding clock and master data using Manchester code, generate master single wire signal and output it; a master clock recovery adapted to recover slave clock according to the system clock and slave single wire signal; and a master Manchester decoder adapted to decode the slave single wire signal and output the decoded slave data.
In one or more embodiments, alternatively and without limitation, the master Manchester encoder is further adapted to generate I2C master clock prolong control.
According to another aspect of the present disclosure, there is provided a 2-wire differential-end bus slave transceiver comprising: a slave clock recovery adapted to generate slave encoding clock according to master single wire signal received from the I2C master, and generate the recovered master clock; a master Manchester encoder adapted to encode the received master encoding clock and master data using Manchester code, generate master single wire signal and output it; and a master Manchester decoder adapted to decode the master single wire signal and generate master data.
In one or more embodiments, alternatively and without limitation, the master I2C timing sequence generator is adapted to ensure the recovered master clock and decoded master data satisfy with I2C standard timing sequence requirement.
According to another aspect of the present disclosure, there is provided a method for communication of 2-wire differential-end bus from I2C master to I2C slave , comprising: transmitting master data and master clock; encoding the master data and master clock using Manchester code, and generating master single wire signal;
transforming the master single wire signal to differential signal and transferring it;
transforming the differential signal back to master single wire signal; decoding the master single wire signal.
According to another aspect of the present disclosure, there is provided a method for communication of 2-wire differential-end bus from I2C slave to I2C master, comprising: transmitting slave data; encoding the slave data using Manchester code, and generating slave single wire signal; transforming the slave single wire signal to differential signal and transferring it; transforming the differential signal back to slave single wire signal; decoding the slave single wire signal.
In one or more embodiments, alternatively and without limitation, the
Manchester code is Manchester-II Bi-phase code.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a 2-wire differential-end bus transceiver system according to one or more embodiments;
FIG. 2 shows a master transceiver according to one or more embodiments; FIG. 3 shows a slave transceiver according to one or more embodiments;
FIG. 4 shows a graph of Manchester encoding;
FIG. 5 shows a graph of 12 C master START command encoding;
FIG. 6 shows a graph of 12 C master STOP command encoding;
FIG. 7 shows a graph of I2C slave ACK response encoding; FIG. 8 shows a graph of 12 C slave NACK response encoding;
FIG. 9 shows a graph of I2C master ACK response encoding; and
FIG. 10 shows a graph of 12 C master NACK response encoding.
DETAILED DESCRIPTION It should be noted that the figures are diagrammatic and not drawn to scale.
Relative dimensions and proportions of parts of these figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments. FIG. 1 shows a 2-wire differential-end bus transceiver system 100 according to one or more embodiments. The 2-wire differential-end bus transceiver system comprises an I2C master 101, a master transceiver 102, a differential system 103, a slave transceiver 104 and an I2C slave 105. The 12 C master 101 and the master transceiver 102 transfer data SDA and master clock SCL to each other. Master clock SCL is bus clock, the master transceiver 102 can encode master data SDA and master clock SCL received from the I2C master 101 using Manchester encoding, generate master single wire signal (MD) and transfer it to the differential system 103; the master transceiver 102 can also decode Manchester-encoded slave single wire signal (MD) received from the differential system 103 and transfer the decoded slave data to the I2C master 101.
The differential system 103 can transform the master single wire signal to differential signal and transfer it, then transform it back to master single wire signal and send it to the slave transceiver 104; the differential system 103 can also transform the slave single wire signal to differential system and transfer it, then transform it back to the slave single wire signal and send it to the master transceiver 102. The differential system 103 can transfer differential signal into single wire signal for the Manchester decoder 204 to decode Manchester-coded the single wire signal from slave transceiver. Manchester encoder 204 can encode I2C master data SDA and master clock SCL into a single wire signal, then the differential 103 can transfer the single wire signal into 2-wire differential signal for transaction to the Manchester decode 204.
I2C slave 105 and the slave transceiver 104 transfer data to each other. The slave transceiver 104 can encode slave data received from I2C slave 105 using Manchester code, generate slave single wire signal and transfer it to the differential system 103, the slave transceiver 104 can also decode Manchester-encoded master signal received from the differential system 103, generate the recovered master clock and transfer the decoded master data and recovered master clock to I2C slave 105.
The differential system 103 comprises a first differential circuit 107, a second differential circuit 109 and differential wire 108 between them. The first differential circuit 107 can transform the master single wire signal to the differential signal and transform it back to the slave single wire signal; the differential wire 108 can transfer the differential signal, and the second differential circuit 109 can transform the slave single wire signal to differential signal and transform it back to the slave single wire signal. The structure of master transceiver 102 and slave transceiver 104 in 2-wire differential-end bus system according to one or more embodiments are showed in FIG. 2 and FIG. 3 as below.
FIG. 2 shows a master transceiver 102 according to one or more embodiments. Master transceiver 102 comprises a master encode clock generator 201 , master clock recovery 202, and master Manchester encoder 203 and decoder 204.
The master encode clock generator 20 lean receive system clock of master transceiver and master clock, and generate master encoding clock by sampling the I2C master clock. The frequency of the master encoding clock is twice that of the master clock. The master Manchester encoder 203 can encode the received master encoding clock and master data using Manchester code, generate master single wire signal and output it, and generate I2C master clock stretching control. A clock stretching control is used to postpone the transmission of master data when the master data has been transferred and the Manchester coding has not been done. The Manchester encoder 203 may generate EN signal which is used to control the transmission direction of the differential-end bus transceiver system 100. The Manchester encoded master single wire signal is generated by the master encode clock generator 201 and the master Manchester encoder 203. The master single wire signal is transformed to 2-wire differential signal by the second differential circuit 109 and is transferred to the first differential circuit 107. Then the 2-wire differential signal is transferred to the second differential circuit 109 by the differential wire 108. The second differential circuit 109 can transform the 2-wire differential signal back to the master single wire signal, then transfer it to the slave transceiver 104, so that the I2C master 101 and slave 105 can communicate with each other. The master clock recovery 202 can sample the slave single wire signal and recover slave clock according to the system clock and slave single wire signal, in order to synchronize the master transceiver and slave transceiver system clock. The master Manchester decoder 204 can receive the Manchester encoded slave single wire signal, the recovered salve clock, master transceiver system clock, decode the slave single wire signal and output the decoded slave data. The Manchester encoded slave single wire signal is transformed to differential signal by the second differential circuit 109. Then the differential signal is transferred to the first differential circuit 107 by the differential wire 108. The first differential circuit 107 can transform the differential signal back to the slave single wire signal, then transfer it to the master transceiver 102. The master decoder 204 can decode the slave single wire signal, generates decoded I2C slave data and transfers it to I2C master 101.
Alternatively, the system clock of both master transceiver 102 and slave transceiver 104 may have a frequency 13 times that of the maser clock. It can make the recovered clock more accurate and the bit error ration lower. FIG. 3 shows a slave transceiver 104 according to one or more embodiments. The slave transceiver 104 comprises a master I2C timing sequence generator 301 , a slave clock recovery 302, a master Manchester encoder 303, and a master Manchester decoder 304.
The slave clock recovery 302 can generate slave encoding clock which has a frequency twice that of the master clock according to master single wire signal received from the I2C master, and generate the recovered master clock. The master Manchester encoder 303 can receive slave transceiver system clock, I2C slave data SDA and slave coded clock, encode the received master encoding clock and master data using
Manchester code, generate master single wire signal and output it to the second differential circuit 109. The second differential circuit 109 can transform the single wire signal to differential signal. Then the differential signal is transferred to the first differential 107 circuit by the differential wire 108. The first differential circuit 107 can transform the differential signal back to the slave single wire signal, then transfer it to the master transceiver 102, so that the I2C master 101 and slave 105 can communicate with each other.
The master Manchester decoder 303 can receive slave transceiver system clock, recovered master clock and master single wire signal, decode the master single wire signal and generate master data. The master I2C timing sequence generator 301 can receive slave transceiver system clock, recovered master clock and decoded master data, buffer the decoded master data to ensure the recovered master clock and decoded master data satisfy with I2C standard timing sequence requirement, i.e. the master data sent to the I2C slave and master clock satisfy the I2C standard timing requirement. The Manchester encoded master single wire signal is generated. The master single wire signal is transformed to differential signal by the first differential circuit 107. Then the differential signal is transferred to the second differential circuit 109 by the differential wire 108. The second differential circuit 109 can transform the differential signal back to the master single wire signal, then transfer it to the slave transceiver 104. The slave decoder 304 can decode the master single wire signal, generate decoded I2C master data and recovered master clock and transfer them to the I2C timing sequence generator 301. The I2C timing sequence generator 301 can transfer the decoded I2C master data and recovered master clock to I2C slave 105.
FIG. 4 shows a graph of Manchester encoding. Alternatively and without limitation, one or more embodiments may use known Manchester II Bi-phase encoding (which may often also be referred to as just Manchester encoding). Manchester encoding provides a self-clocking waveform that incorporates the data bit sequence. Therefore, it is not a separate clock signal because the clock has been embedded in the data. A logical "1 " is a positive pulse followed by a negative pulse, logical "0" is a negative pulse followed by a positive pulse. Encoding the SCL and SDA, the graph is shown as FIG.4. Manchester coded data "1" is a positive pulse followed by a negative pulse, Manchester coded data "0" is a negative pulse followed by a positive pulse.
FIG. 5-10 illustrate several examples of encoding.
FIG. 5 shows a graph of I2C master START command encoding. The master encoding clock is generated by sampling the I2C master clock SCL. The frequency of the master encoding clock is twice that of the master clock. When SCL is positive pulse and SDA changes from positive pules to negative pulse, the START command starts. After the START command, SDA can be transferred continually. There is a sync header for slave transceiver 104 and master transceiver 102. Any data transaction between slave and master will start with a sync header which is 1 SCL period low level and 1 SCL period high level. For start command, the code is a sync header and is followed in 1 SCL period low level.
FIG. 6 shows a graph of master STOP command encoding. The master encoding clock is generated by sampling the I2C master clock SCL. The frequency of the master encoding clock is twice that of the master clock. When SCL is positive pulse and SDA changed from negative pulse to positive pulse, the STOP command starts. After the STOP command, SDA can be transferred again. There is a sync header for slave transceiver 104 and master transceiver 102. Any data transaction between salve and master will start with a sync header which is 1 SCL period low level and 1 SCL period high level. For I2C STOP command, the code is a sync header and is sequentially followed in 2 SCL periods low level and 1 SCL period high level.
FIG. 7 shows a graph of slave ACK response encoding. For I2C slave ACK response, the code is a sync header and is followed in 1 SCL period low level.
FIG. 8 shows a graph of slave NACK response encoding. For I2C slave NACK response, the code is a sync header and is followed in 1 SCL period high level.
FIG. 9 shows a graph of master ACK response encoding. For I2C master ACK response, the code is a sync header and is followed in 1 Manchester data bit 0.
FIG. 10 shows a graph of master NACK response. For I2C master NACK response, the code is a sync header and is followed in 1 Manchester data bit 1. According to another aspect of the present disclosure, there is provided a method for communication of 2-wire differential-end bus from I2C master to I2C slave , comprising: transmitting master data and master clock; encoding the master data and master clock using Manchester code, and generating master single wire signal;
transforming the master single wire signal to differential signal and transferring it;
transforming the differential signal back to master single wire signal; decoding the master single wire signal.
According to another aspect of the present disclosure, there is provided a method for communication of 2-wire differential-end bus from I2C slave to I2C master, comprising: transmitting slave data; encoding the slave data using Manchester code, and generating slave single wire signal; transforming the slave single wire signal to differential signal and transferring it; transforming the differential signal back to slave single wire signal; decoding the slave single wire signal.
In one or more embodiments, alternatively and without limitation, the
Manchester code is Manchester-II Bi-phase code.
Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination. The applicant hereby gives notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of I2C bus transceiver, and which may be used instead of, or in addition to, features already described herein.
Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.
For the sake of completeness it is also stated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, a single processor or other unit may fulfil the functions of several means recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims.

Claims

CLAIMS:
1. A 2-wire differential-end bus transceiver system comprising: an I2C master, a master transceiver, a differential system, a slave transceiver and an I2C slave, wherein:
the master transceiver is adapted to encode master data SDA and master clock SCL received from the I2C master using Manchester code, generate a master single wire signal and transfer it to the differential system; the master transceiver is also adapted to decode Manchester-encoded slave signal received from the differential system and transfer the decoded slave data to the I2C master;
the differential system is adapted to transform the master single wire signal to differential signal and transfer it, then transform it back to master single wire signal and transfer it to the slave transceiver; the differential system is also adapted to transform the slave single wire signal to differential signal and transfer it, then transform it back to the slave single wire signal and send it to the master transceiver;
the slave transceiver is adapted to encode slave data received from I2C slave using Manchester code, generate slave single wire signal and transfer it to the differential system, the slave transceiver is also adapted to decode
Manchester-encoded master signal received from the differential system, generate the recovered master clock and transfer the decoded master data and recovered master clock to I2C slave.
2. A system as claimed in claim 1 , wherein the differential system comprises a first differential circuit, a second differential circuit and differential wire between them, the first differential circuit is adapted to transform the master single wire signal to the differential signal and transform it back to the slave single wire signal, the differential wire is adapted to transfer the differential signal, and the second differential circuit is adapted to transform the slave single wire signal to differential signal and transform it back to the slave single wire signal.
3. A system as claimed in claim 1 , wherein the Manchester code is
Manchester-II Bi-phase code.
4. A 2-wire differential-end bus master transceiver comprising:
a master encode clock generator adapted to receive a system clock of master transceiver and a master clock, and to generate a master encoding clock by sampling the master clock by the system clock of master transceiver;
a master Manchester encoder adapted to encode the received master encoding clock and master data using Manchester code, and to generate a master single wire signal and to output it;
a master clock recovery adapted to recover a slave clock according to the system clock and a slave single wire signal; and
a master Manchester decoder adapted to decode the slave single wire signal and output decoded slave data.
5. A transceiver as claimed in claim 4, wherein the master Manchester encoder is further adapted to generate I2C master clock stretching control.
6. A 2-wire differential-end bus slave transceiver comprising:
a slave clock recovery adapted to generate a slave encoding clock according to a master single wire signal received from the I2C master, and generate the recovered master clock;
a master Manchester encoder adapted to encode the received master encoding clock and master data using Manchester code, to generate a master single wire signal and to output it;
a master Manchester decoder adapted to decode the master single wire signal and generate master data; and
a master I2C timing sequence generator adapted to ensure the recovered master clock and decoded master data satisfy with I2C standard timing sequence requirement.
7. A method for communication of 2-wire differential-end bus from I2C master to I2C slave, comprising:
transmitting master data and master clock;
encoding the master data and master clock using Manchester code, and generating a master single wire signal;
transforming the master single wire signal to a differential signal and transferring it;
transforming the differential signal back to a master single wire signal; and decoding the master single wire signal.
8. A method for communication of 2-wire differential-end bus from I2C slave to I2C master, comprising:
transmitting slave data;
encoding the slave data using Manchester code, and generating a slave single wire signal;
transforming the slave single wire signal to a differential signal and transferring it;
transforming the differential signal back to a slave single wire signal; and decoding the slave single wire signal.
9. A method as claimed in claim 7 or 8 , wherein the Manchester code is Manchester-II Bi-phase code.
PCT/EP2015/057622 2014-04-09 2015-04-08 2-wire differential-end bus transceiver system based on 12c-bus, and associated method for communication of 2-wire differential-end bus WO2015155242A1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108280041A (en) * 2017-12-29 2018-07-13 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） A kind of communication means and device of internal integrated circuit host
EP3839755A1 (en) * 2019-12-17 2021-06-23 Covidien LP Surgical instrument with single wire digital communication over differential bus
CN113572674A (en) * 2021-09-26 2021-10-29 北京芯格诺微电子有限公司 Chain connection communication method of single-wire bus
CN114402576A (en) * 2019-09-24 2022-04-26 开利公司 System and method for transmitting and receiving Ethernet signals
US11336123B2 (en) * 2019-08-14 2022-05-17 Samsung Electronics Co., Ltd. Display apparatus and control method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017200243A1 (en) * 2017-01-10 2018-07-12 Robert Bosch Gmbh Method and apparatus for digital data transmission between a host and a slave over a microsecond bus
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0977126A2 (en) * 1998-07-27 2000-02-02 Richard Wolf GmbH I2C bus interface
WO2013052886A2 (en) * 2011-10-05 2013-04-11 Analog Devices, Inc. Two-wire communication system for high-speed data and power distribution

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201839287U (en) * 2010-10-18 2011-05-18 天津光电通信技术有限公司 Remote transmission circuit for asynchronous serial data
CN102752065B (en) * 2012-06-29 2015-09-09 华为技术有限公司 A kind of method for synchronizing time and system
CN103402007A (en) * 2013-07-26 2013-11-20 广州史达泊雷网络科技有限公司 Audio interface-based data transmission method between intelligent terminal and operating handle

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0977126A2 (en) * 1998-07-27 2000-02-02 Richard Wolf GmbH I2C bus interface
WO2013052886A2 (en) * 2011-10-05 2013-04-11 Analog Devices, Inc. Two-wire communication system for high-speed data and power distribution

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108280041A (en) * 2017-12-29 2018-07-13 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） A kind of communication means and device of internal integrated circuit host
CN108280041B (en) * 2017-12-29 2020-03-10 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） Communication method and device for internal integrated circuit host
US11336123B2 (en) * 2019-08-14 2022-05-17 Samsung Electronics Co., Ltd. Display apparatus and control method thereof
CN114402576A (en) * 2019-09-24 2022-04-26 开利公司 System and method for transmitting and receiving Ethernet signals
EP3839755A1 (en) * 2019-12-17 2021-06-23 Covidien LP Surgical instrument with single wire digital communication over differential bus
US11489696B2 (en) 2019-12-17 2022-11-01 Covidien Lp Surgical instrument with single wire digital communication over differential bus
US11736317B2 (en) 2019-12-17 2023-08-22 Covidien Lp Surgical instrument with single wire digital communication over differential bus
CN113572674A (en) * 2021-09-26 2021-10-29 北京芯格诺微电子有限公司 Chain connection communication method of single-wire bus

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