JPH10105433A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technique capable of monitoring and tracing the operation state of a microcomputer even with an evaluation chip (for evaluation) which is used in a development supporting system and by which a user can optionally set to which external terminal a desired function is assigned by a program. SOLUTION: A semiconductor integrated circuit device is provided with an OR gate circuit 19 obtaining OR of respective signals outputted from plural external terminals 14A and 14B where one of the desired functions, for example, WAIT is assignment possible and a monitor terminal 20 which is provided at the output side of the OR gate 19. The signal for executing the above function is inputted from an outside to one of the external terminals 14A or 14B. Then, when the monitor terminal 20 is permitted to output the signal indicating that the state is for the function, the operation state of the microcomputer is monitored and traced only by monitoring the monitor terminal 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device used in a development support system used when a user develops a product applied to a microcomputer.

[0002]

2. Description of the Related Art With the advance of semiconductor manufacturing technology, the performance of microcomputers (hereinafter simply referred to as microcomputers) has been dramatically improved. Such a microcomputer is
A semiconductor chip on which necessary circuit elements are integrated is sealed in a desired package, and signal input or output is performed through a plurality of external terminals arranged around or around the package.

Here, signals affecting the operation of the microcomputer, such as an external interrupt (IRQ) and a bus release request (B
REQ) and bus cycle extension request (WAIT) can be externally input through external terminals. However, conventionally, those functions are fixedly assigned to specific external terminals. It has become. For example, among a plurality of external terminals, IRQ is No. 5
BREQ is No. 8 to the external terminal
IT is No. Twelve external terminals are assigned, and a signal for executing each function for each external terminal can be input from the outside.

[0004] Such a technique is disclosed, for example, in Hitachi, Ltd., "Hitachi Single Chip RISC Microcomputer SH7.
032, SH7034 Hardware Manual ", issued March 1993, 1.3.1 Pin Assignment (P7).

By the way, a development support system has been constructed in order to develop a product using such a microcomputer, but this development support system has an evaluation chip (Evaluation) having some functions different from those of a commercially available microcomputer.
chip; hereinafter, simply referred to as an evaluation chip). In this development support system, ICE (I
The emulator is connected to a specific external terminal of an evaluation chip using an n-Circuit Emulator (hereinafter simply referred to as an emulator), and a signal input from the outside to the external terminal is monitored through a display or the like, whereby a microcomputer is provided. It monitors and traces the operating state of the system.

On the other hand, in a microcomputer with higher performance, required functions are inevitably increased. Therefore, in the evaluation chip corresponding to such a microcomputer, if a plurality of functions are assigned to specific external terminals in a one-to-one correspondence as described above, more external terminals are inevitably required. However, increasing the number of external terminals not only increases the number of external terminals monitored by the emulator, but also causes disadvantages such as an increase in package dimensions and a complicated circuit configuration.
It cannot be unnecessarily provided.

Therefore, in order to effectively use the limited external terminals, a method is adopted in which a plurality of functions can be assigned to one external terminal. In other words, one desired function is configured to be assignable to a plurality of external terminals, and a signal for executing each function for each external terminal can be input from the outside. For example, as one desired function, WAI
If the user selects T, this WAIT is, for example, No. 8
And No. 12 can be assigned to a plurality of external terminals. 8 and No. A signal for executing the WAIT can be input from the outside to twelve external terminals. In this case, the user can arbitrarily set the function to be assigned to which external terminal (from which external terminal a signal for executing the function is input).

[0008] Such a technique is disclosed in, for example, Hitachi, Ltd., “Hitachi Single Chip RISC Microcomputer SH7.
mmmm (SH704X) Target Specification ”, version 0.1, issued in August 1995, 3 block diagrams.

In the evaluation chip configured so that one desired function (for example, the above-mentioned WAIT) can be assigned to a plurality of external terminals, when the function is monitored by the emulator as described above, a plurality of target functions are required. (For example, the external terminals No. 8 and No. 12 described above) are sequentially switched, that is, multiplexed and monitored.

[0010]

As described above, a desired function can be assigned to a plurality of external terminals used in a development support system as described above. In the case of an evaluation chip that can be set as desired by a program, when monitoring the operation state of a microcomputer by monitoring a specific external terminal and tracing, it is technically necessary to use hardware on the development support system. There is a problem that is difficult.

An object of the present invention is to provide an evaluation chip which is used in a development support system and which allows a user to arbitrarily set a desired function to be assigned to an external terminal by a program. It is an object of the present invention to provide a technology capable of monitoring and tracing the operation state of the device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

(1) The semiconductor integrated circuit device of the present invention is used in a development support system used when developing products applied to microcomputers, and one desired function can be assigned to a plurality of external terminals. A semiconductor integrated circuit device configured to multiplex and monitor the plurality of external terminals, and an OR gate circuit that performs a logical sum of signals output from the plurality of external terminals;
A monitor terminal provided on the output side of the OR gate circuit, wherein when a signal for executing the function is input to any of the plurality of external terminals from the outside, the monitor terminal is in the state of the function. Is output.

(2) The semiconductor integrated circuit device of the present invention is used in a development support system used when developing products applied to microcomputers, and one desired function can be assigned to a plurality of external terminals. A semiconductor integrated circuit device configured to multiplex and monitor the plurality of external terminals, wherein the selection signal generation circuit outputs a plurality of selection signals corresponding to the plurality of external terminals; A plurality of gate circuits each inputting each signal output from the external terminal and each selection signal output from the selection signal generation circuit, and an OR gate circuit for calculating the logical sum of each signal output from each gate circuit, A monitor terminal provided on the output side of the OR gate circuit, and when a signal for executing the function is input from outside to any of the plurality of external terminals. , And is adapted to output a signal indicating that the state of the function to the monitor terminal.

(3) The development support system of the present invention is constructed using the semiconductor integrated circuit devices of (1) and (2).

According to the above-mentioned means (1), the semiconductor integrated circuit device of the present invention takes the logical sum of each signal output from a plurality of external terminals to which one desired function can be assigned. An OR gate circuit, and a monitor terminal provided on the output side of the OR gate circuit, and when a signal for executing the function is input from one of the plurality of external terminals to the outside, the monitor terminal is set to the state of the function. Since a signal indicating the presence of the microcomputer is output, the operation state of the microcomputer can be monitored and traced only by monitoring the monitor terminal. Therefore, even in the case of an evaluation chip that is used in a development support system and allows the user to arbitrarily set the desired function to which external terminal by a program, the operation status of the microcomputer can be monitored and traced using hardware. It is possible to do.

According to the above-mentioned means (2), the semiconductor integrated circuit device of the present invention provides a selection circuit that outputs a plurality of selection signals corresponding to a plurality of external terminals to which one desired function can be assigned. A signal generation circuit, a plurality of gate circuits for inputting each signal output from a plurality of external terminals and each selection signal output from the selection signal generation circuit, and a logical sum of each signal output from each gate circuit An OR gate circuit, and a monitor terminal provided on the output side of the OR gate circuit, and when a signal for executing the function is input from one of the plurality of external terminals to the outside, the monitor terminal has the function of the function. Since a signal indicating the state is output, the operation state of the microcomputer can be monitored and traced only by monitoring the monitor terminal. Therefore, even in the case of an evaluation chip that is used in a development support system and allows the user to arbitrarily set the desired function to which external terminal by a program, the operation status of the microcomputer can be monitored and traced using hardware. It is possible to do.

According to the above-mentioned means (3), since the development support system of the present invention is constructed using the semiconductor integrated circuit devices of the above (1) and (2), it is output from its monitor terminal. The operating state of the microcomputer can be monitored and traced simply by using the signal. Therefore, even when using an evaluation chip that allows the user to arbitrarily set the desired function to which external terminal by using a program, the operation status of the microcomputer can be monitored and traced using hardware. Becomes

Hereinafter, the present invention will be described in detail with reference to the drawings and embodiments.

In all the drawings for explaining the embodiments, parts having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0022]

FIG. 1 is a block diagram showing an internal configuration of a semiconductor integrated circuit device (evaluation chip) according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a configuration of a main part of FIG. FIG. 3 is a block diagram showing an example of the development support system constructed using the semiconductor integrated circuit device according to the present embodiment.

The semiconductor integrated circuit device 1 of the present embodiment has a C
PU (Central Processing Unit) 2, control unit 3, timer 4, S
CI (serial communication interface) 5, RAM (random access memory) 6, R
It comprises an OM (Read Only Memory) 7, a port unit 8, and a gate unit 9.
Formed on one semiconductor substrate. Also, a dedicated address bus (ASEAB) 1 necessary for building a development support system
0, data bus (ASEDB) 11, control (A
(SECNT) signal 12 is also provided.

The user can access the semiconductor integrated circuit device 1 via a user interface. In addition, the semiconductor integrated circuit device 1 is provided with a trace memory 1 via a development support system interface.
3 is accessible, and as shown in FIG. 3, a development support system is constructed.

FIG. 2 shows the port section 8 and the gate section 9 of FIG.
FIG. 3 is a block diagram showing a specific configuration of the embodiment. The port unit 8
A plurality of external terminals 14A, 14B,... 14n are provided, and one desired function can be assigned to the plurality of external terminals. For simplicity, FIG.
An example is shown in which three external terminals 14A and 14B are provided, and a bus cycle extension request (WAIT) can be assigned to each external terminal as one desired function. Therefore, the WAI is connected to each of the external terminals 14A and 14B.
A signal for executing T can be input from the outside.

The signal output from the external terminal 14A is the first
Is input to one input terminal of the first AND gate circuit 16A via the buffer circuit 15A, and is input to one input terminal of the first modified AND gate circuit 17A. First selection signal generation circuit 18A
Outputs a selection signal i corresponding to the external terminal 14A. The selection signal i is input to the other input terminal of the first AND gate circuit 16A and the other input terminal of the first modified AND gate circuit 17A. Input to the terminal.

On the other hand, the signal output from the external terminal 14B is input to one input terminal of the second AND gate circuit 16B via the second buffer circuit 15B.
The signal is inputted to one input terminal of the second modified AND gate circuit 17B. The second selection signal generation circuit 18B outputs a selection signal j corresponding to the external terminal 14B, and this selection signal j is input to the other input terminal of the second AND gate circuit 16B, and the second modification is performed. The signal is input to the other input terminal of the AND gate circuit 17B.

Here, the desired function W
Whether the signal for executing the AIT is input to one of the external terminals 14A and 14B is set by a user program. When programmed in this manner, the selection signal for the set external terminal becomes active. For example, WAIT is connected to the external terminal 14A.
Is assigned, the selection signal i for the external terminal 14A is activated.

In FIG. 2, the gate section 9 is connected to the port section 8.
First and second modified AND gate circuits 17A, 17B
An OR gate circuit 19 is provided so as to input both signals output from. An output terminal of the OR gate circuit 19 is connected to a monitor terminal 20 via a buffer circuit 15C.
Is provided. In this example, the monitor terminal 20 monitors the WAIT state. The control unit 3 is connected to the OR gate circuit 19.

Next, the operation of this embodiment will be described with reference to the configuration of FIG. 2 as an example.

First, the user sends one of the external terminals 14A and 14B to the WAIT signal (W
Input terminal of the signal for executing the AIT, ie, W
Set as an input terminal to assign AIT.

As an example, if the external terminal 14A is set as the input terminal, an active signal is output from the external terminal 14A and the selection signal i for the external terminal 14A is activated. Thereby, the signal output from the external terminal 14A passes through the first modified AND circuit 17A and is output to the OR gate circuit 19. Therefore, since this signal is output to the control unit 3, the control unit 3 confirms that the operation state of the evaluation chip is in the "bus cycle extension request" state.

At the same time, the signal output from the OR gate circuit 19 is output to the monitor terminal 20 via the third buffer circuit 15C. As a result, the signal is output to the development support system side, so that the development support system side receives other signals (for example, dedicated address bus signal ASE
Together with AB), it is possible to monitor that the operation state at that time is a “bus cycle extension request” state due to the WAIT signal input. Then, data based on this signal can be stored in the trace memory 13.

Next, assuming that the external terminal 14B is set as its input terminal, an active signal is output from the external terminal 14B and the selection signal j for the external terminal 14B is activated. As a result, the signal output from the external terminal 14B passes through the second modified AND circuit 17B and is output to the OR gate circuit 19.
Accordingly, this signal is output to the control unit 3 and also to the monitor terminal 20 via the third buffer circuit 15C. As a result, as described above, the control unit 3 confirms that the operation state of the evaluation chip is "bus cycle expansion request" state, and the operation state is "bus cycle expansion request" by the WAIT signal input on the development support system side.
Monitor status.

Subsequently, if both the external terminals 14A and 14B are set as their input terminals,
A and 14B output an active signal,
The selection signals i and j for the external terminals 14A and 14B are activated. Thus, the signal output from the external terminal 14A passes through the first modified AND circuit 17A, and the signal output from the external terminal 14B passes through the second modified AND circuit 17B. 19 is output. Therefore, these signals are output to the control unit 3 and the third buffer circuit 15
It is output to the monitor terminal 20 via C. As a result, as described above, the control unit 3 confirms that the operation state of the evaluation chip is "bus cycle expansion request" state, and the operation state is "bus cycle expansion request" by the WAIT signal input on the development support system side. Monitor status.

As described above, the gate section 9 is combined with the port section 8 which constitutes the main part of the semiconductor integrated circuit device (evaluation chip) shown in FIG. 1, and outputs from the external terminals 14A and 14B to which WAIT can be assigned. The external terminals 14A, 14A
When a signal for executing the WAIT is input from outside B, the function state can be confirmed only by monitoring the dedicated monitor terminal 20. As a result, the operation state of the microcomputer can be monitored and traced without being affected by the external terminal from which the signal is input by the user, so that the development environment of the microcomputer application product can be improved.

According to the semiconductor integrated circuit device of the present embodiment as described above, the following effects can be obtained.

An OR gate circuit 19 for calculating the logical sum of signals output from a plurality of external terminals 14A and 14B to which one desired function, for example, WAIT can be assigned.
And a monitor terminal 20 provided on the output side of the OR gate circuit 19. When a signal for executing the function is input to one of the plurality of external terminals 14A and 14B from outside, the monitor terminal 20 is connected to the monitor terminal 20. Since the signal indicating the function state is output, the operation state of the microcomputer can be monitored and traced only by monitoring the monitor terminal 20. Therefore, even in the case of an evaluation chip that is used in a development support system and allows the user to arbitrarily set the desired function to which external terminal by a program, the operation status of the microcomputer can be monitored and traced using hardware. It is possible to do.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, in the above-described embodiment, an example has been described in which the "bus cycle extension request" function can be assigned to two external terminals, but other functions can be assigned to a plurality of external terminals. In that case, it is equally applicable.

Instead of providing a monitor terminal inside the evaluation chip as in the above embodiment, a function of generating a selection signal corresponding to each external terminal may be provided outside the evaluation chip. This makes it possible to reduce the number of external terminals.

In the above description, the case where the invention made by the present inventor is mainly applied to a semiconductor integrated circuit device which is the application field of the background has been described, but the invention is not limited to this. The present invention is intended for applications in which at least a signal for performing a certain function can be input to a plurality of terminals, and when the signal is input to any of the terminals, it is desired to accurately and easily confirm this state. Can be applied in the same way.

[0043]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

An OR gate circuit for calculating the logical sum of signals output from a plurality of external terminals to which a desired one of the functions can be assigned; and a monitor terminal provided on the output side of the OR gate circuit. When a signal for executing the function is input from one of the plurality of external terminals to the outside, a signal indicating that the function is in effect is output to the monitor terminal. The evaluation chip can be used to monitor and trace the operating state of the microcomputer, so even an evaluation chip that is used in a development support system and allows the user to arbitrarily set the desired function to which external terminal with a program can be set. The operation state of the microcomputer can be monitored and traced by hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an internal configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of a development support system using the semiconductor integrated circuit device according to the embodiment of the present invention.

[Explanation of symbols]

1. Semiconductor integrated circuit device (evaluation chip) 2. CPU
(Central processing unit), 3 ... control unit, 4 ... timer, 5 ...
SCI (Serial Communication Interface), 6 ... RAM (Random Access Memory), 7
... ROM (Read Only Memory), 8 ... Port, 9 ... Gate, 10 ... Dedicated address bus (ASEA)
B), 11: Data bus (ASEDB), 12: Control (ASECCNT) signal, 13: Trace memory, 14A, 14B: External terminal, 15A, 15B: Buffer circuit, 16A, 16B: AND gate circuit, 17
A, 17B ... modified AND gate circuit, 18A, 18B ...
Selection signal generation circuit, 19: OR gate circuit, 20: Monitor terminal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Nosei Abe 5-22-1, Kamizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer Co., Ltd. (72) Inventor Hideaki Koyama 5 Kamimihoncho, Kodaira-shi, Tokyo No. 22-1, Hitachi Microcomputer System Co., Ltd. (72) Inventor Hideya Fujita 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. 5-2-1, Josui-Honmachi, Hitachi, Ltd.Semiconductor Division, Hitachi, Ltd. Inventor Takanaga Yamazaki 5-2-1, Josuihoncho, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd.

Claims (5)

[Claims] The present invention is used in a development support system used when developing a product applied to a microcomputer, wherein a desired one function can be assigned to a plurality of external terminals, and the plurality of external terminals are multiplexed. A semiconductor integrated circuit device configured to monitor by performing an OR gate circuit that performs a logical sum of respective signals output from the plurality of external terminals; and a monitor terminal provided on an output side of the OR gate circuit. Wherein, when a signal for executing the function is input to any of the plurality of external terminals from the outside, the monitor terminal is caused to output a signal indicating that the state of the function is present. Semiconductor integrated circuit device. 2. A system according to claim 1, wherein said plurality of external terminals are assigned to a plurality of external terminals, wherein said plurality of external terminals are assigned to a plurality of external terminals. A semiconductor integrated circuit device configured to monitor and output a plurality of selection signals corresponding to the plurality of external terminals, a selection signal generation circuit, and each signal output from the plurality of external terminals. A plurality of gate circuits for inputting each of the selection signals output from the selection signal generation circuit, and an OR gate circuit for calculating a logical sum of the signals output from each of the gate circuits,
A monitor terminal provided on the output side of the OR gate circuit, wherein when a signal for executing the function is input to any of the plurality of external terminals from the outside, the monitor terminal is in the state of the function. A semiconductor integrated circuit device which outputs a signal indicating the following. 3. The semiconductor integrated circuit device according to claim 1, further comprising a control unit provided on an output side of said OR gate circuit. 4. The semiconductor integrated circuit device according to claim 2, wherein a selection signal corresponding to an external terminal to which said function is assigned among said plurality of external terminals is set to an active state. 5. A development support system constructed using the semiconductor integrated circuit device according to claim 1. Description: