JPH0981402A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To impart the high degree of freedom to the interruption destination control means made by a hardware by making it possible to vary the interruption destination processor from a data transfer processing using software. SOLUTION: In each processor 10, 11...12, an interruption destination designation register rewriting instruction issue means 101 is provided. In a data transfer processor 3, an interruption destination designation register 31 which is rewritten by the interruption destination designation register rewriting instruction that the instruction issue means 101 issues and a data transfer termination interruption request means 32 requesting each processor to perform a data transfer termination interruption in accordance with the designation of the register 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to interrupt control from a data transfer processing device in a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, in a multiprocessor system, when a data transfer processing device issues a data transfer end interrupt to a processor, the following methods are known as a method of selecting an interrupt destination processor.

(1) Method 1 As shown in FIG. 2, a processor 1 constituting a system
Of 0, 11, ... 12, only the specific processor 10 performs interrupt processing. In this case, the data transfer processing device 20 recognizes the fixed specific processor 10 as an interrupt target.

(2) Method 2 As shown in FIG. 3, an interrupt request is issued to all the processors 10, 11, ...
The processor that first accepts the interrupt processes the interrupt. In this case, the data transfer processing device 20 recognizes all the processors 10, 11 ... 12 as interrupt targets.

(3) Method 3 As shown in FIG. 4, the processor 11 requesting the data transfer process performs the interrupt process. In this case, the data transfer processing device 20 determines that the processor 11 that issued the data transfer instruction
Is stored and the processor 11 is recognized as an interrupt target.

(4) Method 4 The processor that performs interrupt processing is dynamically changed based on a specific algorithm. That is, as shown in FIG. 5, an interrupt control unit 30 is provided, and the processors 10, 1
12 are provided between the interrupt control means 30 and the data transfer processing device 20 to monitor the status of the processors 10, 11 ... 12, and the interrupt control device 30 checks the status of each processor 10, 11 ... 12. Dynamically determine the interrupt target.

[0007]

The problems of each of the above-mentioned conventional methods will be described below.

(1) Method 1 Since the processor capable of interrupt processing is fixed, the failure of a specific processor is directly connected to the system failure, and even if the load of the processor is large, the interrupt target cannot be changed. is there.

(2) Method 2 The processor that first accepts an interrupt and performs interrupt processing does not always become the optimum processor for performing interrupt processing in the system. Further, since interrupt requests are issued to all the processors, it is necessary to invalidate the interrupts in the processors that do not execute the interrupts.

(3) Method 3 It is necessary to take measures when the processor that has requested the data transfer processing goes down before the interrupt is accepted.

(4) Method 4 Since the interrupt controller needs to monitor the status of the processor, the interface requires a large amount of hardware resources. This drawback becomes remarkable when the number of processors increases.

[0012]

A multiprocessor system according to the present invention comprises a plurality of processors, a network connecting the plurality of processors, a shared memory connected to the network, the shared memory and an extended storage device. In a multiprocessor system having a data transfer processing device for transferring data between devices, a means for issuing an interrupt destination designation register rewriting instruction is provided in each processor, and the data transfer processing device is provided with the interrupt destination designation register. An interrupt destination designation register that is rewritten by a rewriting instruction, and means for requesting a data transfer end interrupt request to the processor according to the designation of the data transfer end interrupt by the interrupt destination designation register are provided, and the interrupt from the data transfer processing device is provided. Software for the destination processor Characterized in that makes it possible to vary the A.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

One embodiment of the present invention shown in FIG. 1 is that a plurality of processors 10, 11, ...
A data transfer processing device 3 connected to the network 2 by connecting a network 2 connecting 11 ... 12, a shared memory 4 connected to the network 2, and an extended storage device 5 to each other.
It is composed of In the processors 10, 11 ... 12, an interrupt destination designation register rewriting instruction issuing means 10 is provided.
1 and the data transfer processor 3 includes a processor 1
The interrupt destination designation register 31 rewritten by the interrupt destination designation register rewriting instruction issued by 0, 11, ... 12 and the data transfer end interrupt request means 302 for requesting a data transfer end interrupt according to the contents of the interrupt destination designation register 31 are provided. There is.

Next, an operation example of this embodiment will be described.

The processor 10 for system management uses the interrupt destination designation register rewriting instruction issuing means 101 to rewrite the interrupt destination designation register 31 in the data transfer processing device 3 to designate the interrupt destination processor 11.

The arbitrary processor 12 that executes the data transfer instruction issues the data transfer instruction to the data transfer processing device 3, and the data transfer processing device 3 performs the data transfer operation between the shared memory 4 and the extended storage device 5. To do.

At the end of the data transfer operation, the data transfer processing device 3 recognizes the interrupt destination processor 11 according to the contents of the interrupt destination designation register 31, and the data transfer end interrupt request means 32 issues a data transfer end interrupt to the processor 11. To do.

An example of a situation where the interrupt destination processor is changed is shown below.

(A) Based on the dynamic load status obtained by monitoring the status of the processors 10, 11 ...
Alternatively, a processor suitable for interrupt processing is designated at each time point based on a load occurrence situation predicted in advance.

(B) When a processor designated for interrupt processing fails, a substitute processor is designated.

Even in the cases of (a) and (b), in the present invention, the interrupt destination processor can be changed by rewriting the interrupt destination designation register 31 by the interrupt destination processor rewrite instruction issuing means 101 from the processor 10. It is possible. Also, it is possible to easily change the interrupt destination processor in a situation other than the examples shown in (a) and (b).

[0023]

As described above, according to the present invention, the interrupt destination designation register in the data transfer processing device is rewritten by the interrupt destination designation register rewriting instruction issued by the processor. Can be easily changed.

As a result, (a) dynamic load distribution,
It is possible to realize a system capable of flexibly coping with (b) dynamic change of interrupt destination when a failure occurs, and (c) dynamic change of interrupt destination due to other requests. This makes it possible to give the system a high degree of freedom with respect to the interrupt destination control means created by the hardware.

The present invention can be realized by adding a small amount of hardware to the processor and the data transfer processing device. Special interrupt control means for the dynamic interrupt destination change mechanism by conventional hardware,
Alternatively, it can be realized at low cost without requiring a dedicated interface between the processor and the interrupt control means, which causes a sharp increase in cost when the number of processors increases.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a conceptual diagram of a conventional first example.

FIG. 3 is a conceptual diagram of a second conventional example.

FIG. 4 is a conceptual diagram of a third conventional example.

FIG. 5 is a conceptual diagram of a fourth conventional example.

[Explanation of symbols]

10, 11 ... 12 Processor 2 Network 4 Shared memory 3, 20 Data transfer processing device 5 Extended storage device 101 Interrupt destination designation register rewriting instruction issuing means 31 Interrupt destination designation register 32 Data transfer end interrupt request means

Claims (1)

[Claims] 1. A processor having a plurality of processors, a network connecting the plurality of processors, a shared memory connected to the network, and a data transfer processing device for transferring data between the shared memory and an extended storage device. In the multiprocessor system, means for issuing an interrupt destination designation register rewriting instruction is provided in each of the processors, and an interrupt destination designation register rewritten by the interrupt destination designation register rewriting instruction and data are provided to the data transfer processing device. Means for requesting a data transfer end interrupt request to the processor according to the designation of the transfer end interrupt by the interrupt destination designation register, and the interrupt destination processor from the data transfer processing device can be made variable by software. Characterized by Multi-processor system that.