JPH03257634A - Method and device for parallelly processing program - Google Patents

Abstract

PURPOSE:To simultaneously execute plural tasks at real time by executing the plural tasks on the same memory by using plural central processing units (CPU). CONSTITUTION:A CPU 7a executes an initial processing by power-on interruption and executes the task by task activation interruption and CPUs 7b-7m do not generate interruption by power-on but execute the tasks by the task activating interruption. Corresponding to a task activation requiring signal outputted from any one of CPUs 7a-7m, an interruption controller 9 generates the interruption in any one of the CPUs 7a-7m. Thus, the plural tasks stored in an integrated computer can be executed in parallel and simultaneously.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is a simple method for executing various program tasks (hereinafter referred to as tasks) in parallel in embedded computer programs that require high-speed real-time processing. The present invention relates to a program parallel execution method and apparatus that achieve this.

[Prior Art] Conventionally, when multiple programs stored in one memory area are executed in parallel, each program is assigned a priority level and defined as a task, and their execution is controlled by an operating system (hereinafter referred to as O8). ), and the task with the highest priority level at the time of execution was executed, so it appears that multiple tasks are running in parallel when several tasks are activated. , actually one central processor (hereinafter referred to as CPU)
At the same time, only one task could be executed.

``Problems to be solved by the invention'' In the conventional task scheduling method for embedded computer programs, there was only one CPU, so it was difficult to simultaneously execute multiple tasks in the same memory in parallel. .Also, when a high-level task is started while a low-level task is being executed, execution control is transferred to the high-level task at that point, and the execution of the low-level task is interrupted, so the execution of the low-level task is interrupted. The completion time varied depending on the high-level task execution status.Furthermore, since each task was executed serially, the execution time of one task affected the execution completion time of the entire task, and the completion time of the entire task was determined by the specified time. There were cases where it fell outside the range.9 Genkai has begun to appear in improving the performance (for example, MIPS value) of embedded computers, and high-level languages are also being adopted in the field of embedded computers. Therefore, the execution time tends to be longer than before, so it has become necessary to improve computer processing performance not only by improving hardware performance but also by improving software algorithms.

The present invention has been made to solve these problems.

[Means for solving the problem] C that executes various programs stored in main memory
PU, a task start address register that stores the execution start address of a task, a task status register that sets a task execution request, a CPU busy flag register that sets the CPU usage status, and a free CPU that is determined by a task execution request from an application program. search for
When there is a free CPU, an interrupt is generated by the interrupt control device in the CPLJ to issue a corresponding task execution request, and when there is no free CPU, the O8 registers the task execution request in the queue buffer. .

E-effect] By executing multiple tasks on the same memory using multiple CPUs, multiple tasks can be executed simultaneously in real time.

[Embodiment] Fig. 1 shows an embodiment of a program parallel execution device according to the present invention. In Fig. 1, (1) is an address setting device that sets the start address of a task, and (2a) to (2n) are tasks. (3) is the task status register that sets the task execution request, (4) is the CPU (7a) to (7peng)
CPU busy flag register, which sets the usage status of (
5) is a task queue buffer that registers tasks that are requested to be executed when all CPUs (7a) to (7m) are in use, and (6) is a task queue buffer that registers tasks that are requested to be executed when all CPUs (7a) to (7m) are in use. A task/CPU correspondence buffer for determining whether the task is being executed; (7a) is a CPU that executes initial processing by a power-on interrupt, and a CPU that executes a task by a task activation interrupt; (7b) to (7m);
) is a cpv that does not generate an interrupt upon power-on and executes a task by a task activation interrupt, (s) is the main memory that stores various programs, and (9) is a CPV.
Any CPU from U (7a) to CPU U (7a+)
The CPU (
This is an interrupt control device that generates an interrupt to any of the CPUs 7a) to CPU (7+n).

2 to 5 show the processing contents of an embodiment of the program parallel execution method according to the present invention. In the figure, the double-lined processing block means that the O3 processing is called. Figure 2 shows the processing content of the CPU (7a).

Figure 3 shows the processing content of CPU (7b), and Figure 4 shows the processing content of CPU (7b).
The processing content of pU (7c) is shown in FIG. 5, and the processing content of O8, which is commonly used by each CPU, is shown in FIG. For convenience of explanation, a case will be considered in which three tasks are executed simultaneously: task level (hereinafter referred to as task 1), task level 2 (hereinafter referred to as task 2), and task level 3 (hereinafter referred to as task 3). Further, it is assumed that various flags of task 1 are processed using bit 1 of data. In Figure 2, CPU
When a power-on interrupt occurs at (7a), task 1 is activated (step 10). When the activation request for task 1 is issued, the task activation request processing of O3 is activated, and a flag indicating that an execution request for task I has been generated is set in bit 1 of the task status register (step 23), and the CPU busy flag register is set. (step 24) and check the CPU occupancy status (step 25). At this point, no task has been started yet, so turn on bit 1 of the CPU busy register and set the busy flag for the CPU (7a) (step 26), and check the CPU used by task 1 in the task/CPU correspondence buffer. A task activation interrupt is generated in the CPU (7a) by generating a task activation request signal to the CPU (7a) (step 28). The CPU (7a) executes task activation interrupt processing (step 11), and in the task activation interrupt processing that starts the OS task activation interrupt processing (steps 31 to 33), it checks the contents of the task status register and turns on bit 1. Step 31) Clear the task status register. Step 32) Find the execution start address of task 1 from the task start address register.

cb-Branch (step 33). Task 1 processing (1
) (Step 12) is executed, and then a request to start task 3 is issued (Step 13). The same procedure as when task 1 was activated (steps 23 to 3).

At step 27), a task activation interrupt is generated in the CPU (7b) (step 28). After the interrupt activation to the CPU (7b), control is transferred to the next position (step 14) where the task activation request process was issued (step 30).
The CPU (7a) performs task 1 processing (2) (step 14).
), task 2 activation request processing (step 15) is executed.
) to start task 2. At this point, the CPU
Since (7a) and CPU (7b) are in use, task activation request processing (steps 23 to 28)
An interrupt is issued to cPU (7c) and the process returns to task 1 termination processing (step 16). CP IJ (
The task executed in step 7a) determines whether there is a task waiting in the task queue buffer (5) in the task end processing of O3 (steps 34 to 39) (step 34).
), in this case there are no waiting tasks (step 35)
, and since the CPU registered in task l of task/CPU correspondence buffer (6) is CPU (7a), clear bit I of the CPU busy flag register (step 3g) and stop CPU (7a). do(
Step 39). If task queue buffer (5)
If there is a task waiting to be processed, step 36) takes out the waiting task from the task queue buffer (5), takes out the start address of the corresponding task from the task start address register (2a to 2n), and branches to the target task. . At this time, the execution task of the corresponding CPU in the task/CPU correspondence buffer (6) is set to the corresponding number. On the other hand, the CPU (7b) generates an interrupt by the task activation interrupt generation process (step 28), starts the task interrupt process of O5 (step 17), executes task 3 (step 18), and executes task 3 (step 19).
) terminates the CPU (7b) (7) processing FI. Similarly, the CPU (7c) executes task start interrupt processing of O3 (step 2o), executes task 2 (step 21), and task 2 termination processing (step 22).
) terminates the execution of CPU (7c).

[Effects of the Invention] As described above, according to the present invention, a plurality of tasks stored in an embedded computer can be simultaneously executed in parallel. Furthermore, even if the number of tasks to be executed simultaneously is greater than the number of CPUs, waiting tasks can be registered in the task queue buffer, so the number of CPU0 can be changed arbitrarily.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention. (2a) to (2n) are task start address registers, (3) are task status registers, (4)
) is the CPU busy flag register, (5) is the task queue buffer, and (6) is the task/CPU response buffer (
7a) to (7m) are CPU, (8) is main memory i (9)
is an interrupt controller.

Claims (2)

[Claims] (1) Input a task activation request from the task status register, search for a free CPU from the contents of the CPU busy flag register, and when there is a free CPU, use the interrupt control device to interrupt the corresponding CPU to activate the CPU. In an embedded computer system where multiple CPUs exist, by inputting the start address of the corresponding task stored in the task start address register in the integrated CPU and executing the corresponding task stored in the main memory. A program parallel execution method characterized by making it possible to execute multiple tasks. (2) A task start address register that stores the start address of a task, a task status register that stores task activation requests, a CPU busy flag register that stores the CPU usage status, and all CPU
A task queue buffer that temporarily registers startup request tasks when the CPU is in use, a task/CPU correspondence buffer that stores information about tasks being executed by the CPU being used, and a CPU that executes various programs. A program parallel execution device comprising: a main memory for storing various programs; and an interrupt control device that generates an interrupt when a task is executed.