JPH04302352A - Multi processor system - Google Patents

Abstract

PURPOSE:To obtain a multi processor system with high flexibility and reliability which can achieve the efficient distribution of the input output request. CONSTITUTION:An input output processing means 15 to process the interrupting request from plural input output devices is provided between plural. processors and plural input output devices, the input output processing means 15 has id holding memories A1-An, a flag holding memory 12, and an interrupting processing controller 11 to process the interruption with these memories, and the content of these memories can be rewritten from a CPU side.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to an interrupt processing function from an input/output device.

0002

2. Description of the Related Art Methods for processing interrupts from input/output devices in multiprocessor systems include the technique shown in Figure 1 of Japanese Patent Application Laid-Open No. 10381/1981 (in which a processor that accepts interrupts is fixed); Second
The technique shown in the figure (in which the channel stores the requesting processor that issued the input/output request), or the technique shown in FIG. 6 (in which the priority of the interrupt destination CPU is set outside the processor), Furthermore, JP-A-60-24660
There are some that utilize interrupt destination determination logic circuits.

0003

SUMMARY OF THE INVENTION The above-mentioned conventional technology has the following problems. (1) Every time the state of each CPU changes, the conditions for determining the interrupt destination must be changed, and the power of the CPU and the bandwidth of the bus are sacrificed by the amount of the change. (2) If each CPU has a cache memory,
When the input/output device processed by one CPU changes, the cache miss rate may increase. (3) When interrupt requests are received from multiple input/output devices simultaneously, it is difficult to efficiently and evenly distribute these requests to each CPU, making parallel processing impossible and reducing processing speed. (4) Unforeseen circumstances on the input/output device side, such as a failure in one of the input/output devices, or a CPU failure, etc.
It is difficult to take immediate and flexible responses that take into account unforeseen circumstances.

The present invention has been made in view of these problems, and its purpose is to provide a flexible and highly reliable multiprocessor system that can achieve efficient distribution of input/output requests. be.

[0005]

[Means for Solving the Problems] The present invention provides an input/output processing means for processing interrupt requests from the plurality of input/output devices, which is provided between a plurality of processors and a plurality of input/output devices. This input/output processing means has an id holding memory, a flag holding memory, and an interrupt processing controller that processes interrupts using these memories, and is configured so that the contents of these memories can be rewritten from the CPU side. It is characterized by the fact that

[0006]

[Operation] Each input/output device and each processor (CP)
Make a correspondence (preferably 1:1) with U),
Decide which CPU should give priority to processing the interrupts of which input/output devices. More preferably, when the highest priority CPU is unable to process the interrupt, the CPU that should handle it next (next priority CPU) should also be determined, and the ID numbers of these highest priority, next priority, etc. CPUs should be determined. , is stored in an ID holding memory provided for each input/output device. All interrupt requests from each input/output device are first received by the interrupt processing controller.

[0007] This interrupt processing controller reads the CPU ID number of the input/output device that made the interrupt request, then searches the flag holding memory, checks the flag state for the CPU with that ID number, and determines whether the flag is set. If not, the CPU determines that the request can be processed, generates an interrupt, and sets a flag at the corresponding location in the flag holding memory. Similar operations are performed for the next priority CPUid. The CPU that receives the interrupt request refers to the flag in the flag holding memory via the interrupt processing controller, confirms the input/output device that is the source of the interrupt request, and then processes the interrupt according to the processing program for this input/output device. When the processing is completed, the CPU accesses the flag holding memory via the interrupt processing controller and releases the flag.

Since the contents of the id holding memory and the flag holding memory are prepared for each input/output device and each processor, it is possible to process interrupts in parallel (simultaneously), and also to handle interrupts based on priorities in advance. Since this is done, requests can be distributed efficiently. Also, C.P.
Since it can be freely rewritten according to the software on the U side, interrupts from a specific input/output device (for example, a malfunctioning device) can be prohibited by not setting the CPUid, or when a certain CPU malfunctions. , other CPUs can change the CPUid and take over interrupt processing instead, allowing flexible processing to suit the situation.

[0009]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. The feature of this embodiment is that multiple processors (CPU1
~ CPUn) and input/output devices (I/O (1) ~ I/O
(n)) Interrupt processing means 15 is provided between the two.

[0010] This interrupt processing means 15 has n ID holding memories (A1 to An ), a flag holding memory 12 capable of holding a flag (F) for determining the presence or absence of an interrupt from each input/output device for each processor (CPU1 to CPUn), and these memories (A1 to CPUn). An, 12) An interrupt processing controller 11 that processes (controls) interrupts using the following.

When an interrupt request is received from each input/output device, this interrupt processing controller 11 stores an ID holding memory (A1 to A1) for the input/output device that generated the request.
n), then find the id number held in that i
For the CPU specified by the d number, the state of the flag in the flag holding memory 12 is searched, and if there is no flag, the flag is set and an interrupt is generated for that CPU. When there is a read/write request to the holding memory (A1 to An, 12), the internal bus 14 is connected to the system bus 13 to enable access from the CPU side.

[0012] Furthermore, each processor (CPU1 to CPUn
) and each input/output device (I/O(1) to I/O(n)) are associated in advance, and it is determined which CPU will process interrupts from which input/output device with priority. It is being Furthermore, when the highest priority CPU cannot process the interrupt, the CPU that should handle it next (next priority CPU) is also determined, and the ID numbers of these highest priority, next priority, etc. CPUs are set for each input. ID provided for each output device
It is stored in the holding memory (A1 to An). Each ID holding memory (A1 to An) can have multiple entries for multiple ID numbers (this number corresponds to the CPU number), for example, as shown in the lower right of Figure 1. A certain ID number has a higher priority. Therefore, in the example shown in the figure, if there is an interrupt request from an input/output device (I/O (1)), CPU1 will process it preferentially, if this is not possible, CPU2 will process it, and other processors will is uninterruptible (id number "0" indicates that there is no processor to interrupt).

Furthermore, as shown in the lower left of FIG. 1, the flag holding memory 12 has flag set areas for each CPU, the number of which corresponds to each input/output device (n), and when interrupts are received from the input/output device. If so, a flag (F) is set in the area corresponding to that input/output device. For example, in the example shown in the figure, CPU1 is currently processing an interrupt request from an input/output device (I/O(1)), and CPU3 is currently processing an interrupt request from an input/output device (I/O(3)). is being processed. Once set, the flag is set after the CPU processes the request using the processing program 15.
It is canceled by an instruction from PU.

FIG. 2 is a flowchart for explaining the operation (processing procedure) of the interrupt processing controller 11 in the embodiment of FIG. Interrupt processing controller 1
1, when there is an interrupt from the input/output device (step 2
0), identifies the input/output device (that is, the type of interrupt) (step 24), and reads the first ID number of the ID holding memory (A1 to An) corresponding to the input/output device (step 24).
Step 26), the flag state (content of the flag holding memory 12) of the CPU indicated by the ID is checked (Step 27). If the flag is set and the CPU is executing a process (step 27), the next CPU ID is read (step 28), and the flag state of the CPU indicated by that ID is similarly checked (step 29). Repeat this to generate an interrupt to a free CPU (
Step 30). Next, it is checked whether there is an interrupt from another input/output device (step 31), and if there is no interrupt, the process moves to step 21, and this time it is checked whether there is an access request from the CPU. If there is an access request, the internal bus 14 is released to that CPU (step 22), and the
Wait until U's access (for example, access to clear the flag or rewrite the ID number) is completed (step 2).
3), return to step 20.

[0015]

[Effects of the Invention] As explained above, the present invention has the following effects by setting the interrupt destination CPU for each input/output device using an ID number and making the setting controllable by software on the CPU side. can get. (1) Since a plurality of input/output processing devices can be distributed separately from the CPU, their interrupt processing requests can be processed quickly and almost simultaneously. (2) The software on the CPU side allows the interrupt load to be optimally distributed to each input/output processing device (that is, to each type of interrupt), and changes can be made flexibly. (3) In a CPU with a cache, the interrupt destination can be specified by an ID number so that the CPU does not have to update its own cache, so the performance of input/output processing can be improved. (4) By not setting the CPUid, you can disable interrupts from a specific input/output device (for example, a failed device), or if a CPU fails, another CPU can change its CPUid and interrupt instead. It can perform flexible input/output processing according to the situation, such as taking over processing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation (processing procedure) of the interrupt processing controller 11 in the embodiment of FIG. 1;

[Explanation of symbols]

11 Interrupt processing controller 12 Flag holding memory 13 System bus 14 Internal bus 15 Interrupt processing means A1~An　CPUid holding memory

Claims (1)

[Claims] 1. An input/output processing means (15) for processing interrupt requests from the plurality of input/output devices is provided between the plurality of processors and the plurality of input/output devices,
This input/output processing means (15) includes an ID holding memory (A1 to An) that holds ID information for each input/output device that specifies the processor to be interrupted, and an ID storage memory (A1 to An) for each input/output device.
Flag holding memory (12) capable of holding flags for determining the presence or absence of interrupts from each input/output device
When an interrupt request is received from each input/output device, the ID information stored in the ID storage memory for the input/output device that generated the request is searched, and the processor specified by the ID information is searched for. The state of the flag in the flag holding memory is searched, and if there is no flag, the flag is set to generate an interrupt to the processor, and when there is a read/write request from each processor to the ID holding memory or the flag holding memory, A multiprocessor system comprising: an interrupt processing controller (11) that processes the request.