JPH0969593A - Semiconductor device and package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a reliable semiconductor element and a package for the semiconductor element for reducing warpage or residual stress due to the difference in thermal coefficient of expansion between GaAs substrate and Au plated layer and obtaining improved electrical characteristics without any scattering in bonding wire length at the time of packaging. SOLUTION: An Au plated layer 5 for cooling which is approximately 40μm thick and thermoplastic polyimide layer (TPI layer) 6 where a conductive filler is mixed at a part which is not related to cooling on the reverse side of the GaAs substrate 1 are formed on the reverse side of the GaAs substrate 1 where the GaAs substrate with a low thermal conductivity to enhance cooling property is made thin up to approximately 30μm by etching. Also, the GaAs substrate 1 ranging from 100 to 200μm is made thinner to 30-50μm by etching to enhance cooling property only at the lower portion of an FET part 2 to form a recessed part and a TPI part is formed in the recessed part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor device package.

[0002]

2. Description of the Related Art FIG. 11 is a sectional view showing a conventional high-frequency high-power semiconductor device composed of a GaAs substrate and an Au plating layer. In the figure, reference numeral 1 denotes a GaAs substrate, which has a low thermal conductivity of 0.46 W / cm ° C, and is thinned to about 30 μm by etching in order to enhance heat dissipation. Reference numeral 2 is a FET portion formed on the GaAs substrate 1, and 3 is a via hole provided so as to penetrate from the chip surface to the chip rear surface so that the source electrode of the FET is directly connected to the chip front surface from the chip rear surface. , Via hole 3
Au plating 4 is applied to the inside to make electrical conduction. Numeral 5 is a heat radiation device 30-made under the GaAs substrate 1
It is a 50 μm thick Au plating layer. FIG. 12 is a cross-sectional view of a high-frequency high-power semiconductor device composed of two conventional FETs, which is different from the structure shown in FIG. 11 composed of a GaAs substrate and an Au plating layer. In the figure, 1 indicates a thickness of 100 to
The GaAs substrate is 200 μm thick, and the lower part of the FET part 2 is etched to a thickness of 30-
The recessed portion 7 is formed to a thickness of 50 μm, and the recessed portion 7 is plated with Au, which is a good heat conductor, to form the first plated portion 9. Furthermore, in the lower part of the first plating part 9,
GaA to be the ground plane of high frequency high power semiconductor devices
The second Au plated portion 10 is formed on the entire back surface of the substrate 1 by several μm. Reference numeral 3 is a via hole provided so as to penetrate from the chip front surface to the chip back surface so that the source electrode of the FET is directly connected to the chip front surface, and Au plating 4 is applied in the via hole 3. It has electrical continuity.

FIG. 13 is a cross-sectional view showing a conventional example of a method of mounting a high-frequency high-power semiconductor element on a package or the like. First, an AuSn solder 41 is used to C-plat the surface with Au.
uW42, first ceramic layer 43, and second ceramic layer 4
Approximately 300 ° on the CuW42 of the package composed of 4
The element 40 is die-bonded at the hot station C. Next, the bonding pad 45 formed on the surface of the element and the pad 46 formed on the package side are
The u-wire 47 is used for electrical connection with the outside. At this time, the wiring 49 in the package for electrical connection generally has the characteristic impedance of the line in order to match the line impedance with the external high frequency line, the line width, the thickness of the first ceramic layer 43, and the second ceramic layer 44. The permittivity is set to an appropriate value and set to 50 ohms. Finally, the package is sealed with a cap 48 made of metal such as Kovar to complete the mounting of the device.

[0004]

The conventional device shown in FIG. 11 is constructed as described above and mounted in a package. However, when the device is die-bonded, the GaAs substrate 1 and the Au plating layer 5 have a thermal expansion coefficient. Each coefficient is 6.5 × 1
0 ^-6 ° C ^-1 , ^14.0 × 10 ^-6 ° C ^-1
The element warps concavely. This amount of warpage depends on the size of the element, GaA
s The substrate length and the Au plating layer thickness vary, but for example, the element long side length is 3 mm and the GaAs substrate thickness is 30 to 40.
um, Au plating thickness is 40-50um, die bond temperature is 3
When the temperature is around 00 ° C, this warp amount is about 30 at the element end.
~ 50um. When such a warp occurs, there is a problem in that there is a difference in the solder thickness between the central portion of the element and the end portion of the element, the thermal resistance varies, and voids are generated in the solder, which lowers heat dissipation. Further, there is a problem that it is difficult to automatically recognize the element surface because the element surface is not flat due to warpage during wire bonding. Also, FIG.
In the conventional element shown in FIG. 2, the thermal expansion coefficient between the GaAs substrate 1 and the first Au-plated portion 9 is different as described above due to the temperature change under the actual use environment, so that the stress remains in the peripheral portion of the FET. However, there is a problem that reliability is lowered. Further, in the conventional mounting method shown in FIG. 13, since characteristic impedance control of the line at the bonding wire portion cannot be performed due to variations in the bonding wire length, reflection due to impedance mismatch occurs and the electrical characteristics of the element deteriorate. There was a problem.

The present invention has been made to solve the above problems, and reduces warpage and residual stress due to the difference in thermal expansion coefficient between the GaAs substrate and the Au plating layer,
Another object of the present invention is to provide a highly reliable semiconductor element and a semiconductor element package that can obtain good electrical characteristics without variations in bonding wire length during mounting.

[0006]

A semiconductor device according to the present invention is a GaA having a heating element such as an FET formed on the surface thereof.
An s substrate and a heat dissipation plate formed on the back surface of the GaAs substrate are provided. The heat dissipation plate is provided with an Au plating layer having high heat dissipation properties, and at a high temperature, fluidity is obtained at high temperatures, and sticking property is obtained at low temperatures. It is formed of a thermoplastic polyimide resin. In the heat sink, only the lower portion of the heating element, which is a main conduction area of heat generated by the heating element, is formed by the Au plating layer, and the other area is formed by the thermoplastic polyimide resin. Further, a GaAs substrate having a heating element such as an FET formed on the surface thereof, a recess formed by cutting the GaAs substrate to enhance heat dissipation on the back side of the GaAs substrate under the heating element, and the inside of the recess are filled. And a thermoplastic polyimide resin. Further, a Si resin having a rubber-like property is mixed with the thermoplastic polyimide resin. Further, a conductive filler is mixed in the thermoplastic polyimide resin.

Further, the final layer on the back side of the GaAs substrate is made of thermoplastic polyimide resin, and the thermoplastic polyimide resin is used as a die bonding material. In addition, a GaAs substrate on which elements such as FETs are formed on the surface and Ga
A via hole that penetrates the As substrate and electrically connects the element to the back surface of the GaAs substrate, an electrode portion formed in the via hole portion on the back surface of the GaAs substrate, and a GaA excluding the electrode portion.
s A ground portion is formed on the back surface of the substrate, and the electrode portion and the ground portion are formed by using a thermoplastic polyimide resin. In addition, the electrode part and the ground part are
It is separated by a groove of about um.

Further, in the chip die bond portion on the ceramic substrate, electrode pads and ground portions formed corresponding to the electrode portion and the ground portion formed on the back surface of the mounted semiconductor element, and formed on the ceramic substrate, An electrode pad and a ground portion are provided with through holes for connecting to an external electrode, and the electrode pad and the ground portion formed on the back surface of the semiconductor element and the electrode pad and the ground portion formed on the chip die bond portion are respectively aligned, Bonding is performed.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. 1 is a sectional view showing a high-frequency high-power device according to a first embodiment of the present invention. In the figure, 1 is a GaAs substrate, which has a low thermal conductivity of 0.46 W / cm ° C.
It is thinned to about um. Reference numeral 2 is a FET portion formed on the GaAs substrate 1, and 3 is a source surface of the FET so that the source electrode of the FET is directly connected to the front surface portion of the chip and other wiring patterns (not shown). It is a via hole that is provided to penetrate
Au plating 4 is applied to the inside of the via hole 3 to establish electrical continuity. Reference numeral 5 is an Au plated layer for heat dissipation having a thickness of about 40 μm provided on the back surface of the GaAs substrate 1, and 6 is GaAs.
Thermoplastic polyimide mixed with a conductive filler formed in a portion of the back surface of the substrate 1 that does not contribute to heat dissipation (hereinafter referred to as TPI).
Respectively) are shown.

The FET section 2 is used during actual operation of the high frequency and high output device.
The heat generated in the GaAs substrate 1 as shown by A in FIG.
It conducts inside at an angle of 45 degrees. Therefore,
The heat dissipating Au plating layer 5 may be applied only to the portion where heat is conducted, and for example, the width of the FET portion 2 (W1 in FIG. 1) is 15
0 μm, the thickness of the GaAs substrate 1 is 30 μm, and the thickness of the Au plating layer 5 is 40 μm, the width of the Au plating layer 5 (W2 in FIG. 1).
Can be 290 um.

Next, a method of manufacturing the high frequency high power device of this embodiment will be described. First, after patterning the surface and forming via holes 3 on a normal 600 μm thick GaAs substrate by photolithography, wax 30 is applied to the surface as shown in FIG. Polish the thickness to 30 um. Next, a plated power supply layer 32 is formed by patterning using a photoengraving technique, and then an Au plating layer 5 is formed by electroplating as shown in FIG.
Form 0 um. Next, in parts other than the Au plating layer 5,
Ag as conductive filler in liquid polyamic acid varnish
A resin mixed with is formed by a spin coating method. The coating thickness of the resin can be easily controlled by the viscosity of the resin and the number of rotations. After that, it is dried by baking at 200 ° C. for about 30 minutes, imidized, and when the glass transition temperature becomes a high temperature, the fluidity is obtained, and conversely, when the temperature is low, the adhesiveness is obtained. A thermoplastic polyimide (TPI) layer having reversibility depending on temperature is formed, and the wafer is peeled off from the glass plate 31 to complete the process.

By configuring the high-frequency high-power device as described above, the coefficient of thermal expansion of the GaAs substrate 1 and the Au plating layer 5 is 6.5 × 1 each when the device is die-bonded.
The warp amount that makes the element concave because it is different from 0-6 ° C ^-1 and ^14.0 × 10 ^-6 ° C ^-1 is because the length of the Au plating layer 5 is shortened and Coefficient of thermal expansion is about 6.0 × 1
Although it is as high as 0 ^-5 ° C ^-1 , it can be reduced by the glass transition temperature of the TPI layer exceeding the glass transition temperature during die bonding and becoming a softened state.

Embodiment 2. FIG. 3 is a sectional view showing a high-frequency high-power device according to the second embodiment of the present invention.
In the present embodiment, as in the first embodiment described above, a combination structure of the Au plating layer 5 and the TPI layer 6 of the high frequency and high output element is adopted, and the thickness of the TPI layer 6 is set to the Au plating layer 5.
The Au plating layer 5 is covered with the TPI layer 6 so that the Au plating layer 5 is covered with the TPI layer 6. Here, the difference between the thickness of the TPI layer 6 and the thickness of the Au plating layer 5 (D1 in FIG. 3) is 5 μm or less. The manufacturing method of the high frequency high power device of the present embodiment is
The formation method up to the PI layer 6 is the same as that of the first embodiment, but the thickness of the TPI resin applied is controlled to be slightly thicker than the thickness of the Au plating layer 5 by controlling the viscosity of the resin and the rotation speed of the spin coating method. To do.

In the high-frequency and high-power device constructed as described above, the coefficient of thermal expansion between the GaAs substrate 1 and the Au plating layer 5 is 6.5 × 10 ⁻⁶ when die bonding the device, similarly to the first embodiment. ° C ^-1, 14. 0 warpage amount × 10 ^-6 ° C ^-1 and different elements to become concave is, Au plating layer 5
Although the length of TTP is shortened and the thermal expansion coefficient of the TPI layer itself is as high as about 6.0 × 10 ^-5 ° C ^-1 , TP
When the I layer is die bonded, it exceeds the glass transition temperature,
It can be reduced by becoming a softened state. further,
By using the TPI layer 6 as the die bonding material, AuSn solder is not required and die bonding can be performed at the glass transition temperature of TPI (about 200 ° C.), the die bonding temperature can be lowered, and the warpage amount can be reduced. Further, since AuSn solder is not required, the number of steps is reduced and the manufacturing efficiency is improved.

Embodiment 3 FIG. 4 is a sectional view showing a high-frequency high-power element according to the third embodiment of the present invention. In the figure, 1 is a GaAs substrate having a thickness of 100 to 200 μm,
In the lower part of the FET part 2, the GaAs substrate is thinned to 30 to 50 μm by etching in order to enhance heat dissipation to form a recessed part 7, and the TPI part 8 is formed in the recessed part 7 instead of the conventional Au plating.
Are formed. Further, under the TPI portion 8, GaAs is formed so as to serve as the ground plane of the high frequency high power semiconductor device.
A few μm of Au plated portion 10 is formed on the entire back surface of the substrate 1. Reference numeral 3 is a via hole provided so as to penetrate from the chip front surface to the chip back surface so that the source electrode of the FET is directly connected to the chip back surface, and the inside of the via hole 3 is plated with Au. , TPI is mixed with Ag as a conductive filler, and therefore has electrical continuity.

The method of manufacturing the high-frequency high-power element according to this embodiment is the same as the conventional element of this type shown in FIG. 12 up to the formation of the recess 7, and the GaA is formed by etching.
Although the s substrate is thinned, thereafter, the TPI portion 8 is formed in the recess 7 by the spin coating method, and then the Au plated portion 10 is formed on the entire back surface of the GaAs substrate 1. In the high-frequency high-power element configured as described above, the elastic modulus of TPI is 0.51 × 10 ³ Kg / mm ² , and the elastic modulus of Au of the above-described conventional embodiment is 7.8 × 10 ³ °. Since it is sufficiently soft compared to CKg / mm ² , F due to the difference in thermal expansion coefficient
It is possible to reduce the residual stress in the peripheral portion of the ET.

Embodiment 4 FIG. 5 is a sectional view showing a high-frequency high-power element according to the fourth embodiment of the present invention. In the present embodiment, the second TPI portion 11 is formed on the entire back surface of the GaAs substrate 1 instead of the Au plated portion 10 of the high frequency and high output device of the third embodiment. TP
Since I is mixed with I as a conductive filler in I, electrical continuity is achieved. The manufacturing method is the same as in the third embodiment, in which the first T
The PI portion 8 is formed, and the second TPI portion 11 is continuously formed on the entire back surface of the GaAs substrate 1. In the high-frequency high-power device configured as described above, the elastic modulus of TPI is 0.51
The residual stress at the peripheral portion of the FET due to the difference in the thermal expansion coefficient is × 10 ³ Kg / mm ² , which is sufficiently soft compared to the elastic modulus of Au of the above-mentioned conventional example of 7.8 × 10 ³ ° C Kg / mm ^2. Can be reduced. Further, by using the second TPI portion 11 as a die bonding material, AuS
n Solder is no longer needed and the glass transition temperature of TPI (about 2
Since the die bonding can be performed at 00 ° C. and the die bonding temperature can be lowered, the residual internal stress can be reduced.

Embodiment 5 FIG. 6 is a sectional view showing a high frequency and high output device according to a fifth embodiment of the present invention. In this embodiment, the TPI in which the Si resin is mixed is used in the TPI portion of the high-frequency, high-power element shown in the third and fourth embodiments. In the figure, reference numeral 12 is a TPI portion mixed with Si resin and having a rubber-like property. In the high-frequency high-power element configured as described above, the TPI portion 12 mixed with the Si resin exhibiting rubber-like properties can reduce residual stress in the FET peripheral portion.

Embodiment 6 FIG. 7 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention, and FIG. 8 is a plan view showing the back surface. In the figure, 1 is a GaAs substrate, 3 is a
13 is a via hole formed in a portion corresponding to the bonding pad 45 of the conventional example shown in FIG. 13, 13 is an electrode TPI portion formed in the via hole 3 portion on the back surface of the chip, and 14 is a ground TPI portion. The electrode TPI portion 13 and the ground TPI portion 14 are formed so as to be electrically separated by the isolation portion 15. At this time,
A high-frequency signal input / output unit (not shown) is arranged beside the electrode and the via hole so as to be a ground, a signal, and a ground by the ground electrode and the via hole.

The semiconductor element manufacturing method according to this embodiment is a semiconductor element surface pattern, and the via hole 3 forming method is a photolithography technology, a film-forming technology, and an etching technology. It forms like. After that, a resist is patterned on the isolation portion 15 by using a photoengraving technique, and TP for electrodes is used.
The I portion 13 and the ground TPI portion 14 are formed by spin coating, and the resist is removed to complete the process.

The semiconductor element configured as described above can be bonded on a chip bonding substrate provided with pads according to the arrangement of electrodes formed on the back surface of the chip.
The connection with the Au wire 47 as in the conventional example shown in FIG. 13 is not necessary, reflection due to impedance mismatch due to variations in wire length, etc. can be reduced, the electrical characteristics of the element are improved, and reliability is improved.

Embodiment 7 FIG. 9 is a plan view showing a semiconductor device package according to a seventh embodiment of the present invention, and FIG.
FIG. 0 is a cross-sectional view showing a state in which the semiconductor element according to the sixth embodiment is mounted on the semiconductor element package according to the seventh embodiment of the present invention. In the figure, 16 is a cavity, 17 is an electrode pad, 18 is a ground part, and 19 is an isolation part. In this embodiment,
In the chip die bond portion on the ceramic substrate 20 such as alumina in the cavity 16, the electrode pad 17 and the ground portion 18 are isolated so as to correspond to the electrode pattern arrangement formed on the back surface of the semiconductor element according to the sixth embodiment of the present invention. It is electrically separated and formed by the abutment portion 19. The electrode pad 17 and the ground portion 18 are electrically connected to an electrode portion 22 and a ground electrode portion 23 formed outside the package by a through hole 21 formed in the ceramic substrate 20. The external electrodes may be formed on the back surface of the package to have a so-called BGA structure. Alternatively, internal wiring may be formed in the ceramic substrate 20 and external electrodes may be provided on the side surfaces of the package to attach leads made of Kovar material or the like to the QFP. Type or SOP type package may be used. At this time, a high-frequency signal input / output unit (not shown) is arranged beside the electrode and the through hole so as to serve as a ground, a signal, and a ground through the ground electrode and the through hole.

Next, a mounting method for mounting the semiconductor element shown in FIG. 7, which is the sixth embodiment of the present invention, in the semiconductor element package of the present embodiment will be described. For chip bonding, a commercially available automatic die bonder or the like is used, and the package is heated to 200 ° C.
The electrode TPI portion 13 and the electrode pad 17 formed on the back surface of the substrate 1 and the ground TPI portion 14 and the ground portion 18 are chip-handled by a collet so that they are aligned with each other, and the alignment is performed. The alignment accuracy at this time is within 30 μm due to the recognition of the optical system, and therefore the isolation part 19 may be set to a width of about 50 μm. Next, it is sealed with a cap 24 and completed.

By configuring the semiconductor element and the package for the semiconductor element as described above, the electric signal transmission path is provided from the electrode portion of the IC or FET pattern formed on the surface of the GaAs substrate 1 via the via hole 3. Since it is connected to the electrode portion 22 and the ground electrode portion 23 formed outside the package through the electrode TPI portion 13 on the back surface of the GaAs substrate 1 and further through the through hole 21 formed in the ceramic substrate 20 of the package. , As before, A
Since it is not necessary to connect with u wires, reflection due to impedance mismatch can be reduced. Further, a pad for wire bonding on the package side is not required, and the package size can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a high-frequency high-power element according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the high-frequency high-power element according to the embodiment of the present invention.

FIG. 3 is a sectional view showing a high-frequency high-power device according to a second embodiment of this invention.

FIG. 4 is a sectional view showing a high-frequency high-power device according to a third embodiment of the present invention.

FIG. 5 is a sectional view showing a high-frequency high-power element according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view showing a high-frequency high-power element according to a fifth embodiment of the present invention.

FIG. 7 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention.

FIG. 8 is a plan view showing a back surface of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 9 is a plan view showing a semiconductor element package according to a seventh embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a state in which a semiconductor element package according to a sixth embodiment of the present invention is mounted on a semiconductor element package according to the seventh embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a conventional high-frequency high-power device.

FIG. 12 is a cross-sectional view showing a conventional high-frequency high-power element.

FIG. 13 is a cross-sectional view showing a conventional method of mounting a high-frequency high-power element.

[Explanation of symbols]

1 GaAs substrate, 2 FET section, 3 via holes,
4 Au plating, 5 Au plating layer, 6 TPI layer, 7
Recessed portion, 8 TPI portion, 9 Au plated portion, 10 Au
Plated part, 11 TPI part, TPI part mixed with 12 Si resin, 13 TPI part for electrode, 14 T for ground
PI portion, 15 isolation portion, 16 cavity, 17 electrode pad, 18 ground portion, 19 isolation portion, 20 ceramic substrate, 21 through hole, 22 electrode portion, 23 ground electrode portion, 24
Cap, 30 wax, 31 glass plate, 32
Power feeding layer, 40 elements, 41 AuSn solder, 42 C
uW, 43 first ceramic layer, 44 second ceramic layer, 45 bonding pad, 46 pad, 47
Au wire, 48 cap, 49 wiring.

Claims (10)

[Claims] 1. A semiconductor device comprising a GaAs substrate having a heating element such as an FET formed on the front surface thereof, and an Au plating layer formed on the back surface of the GaAs substrate and a heat dissipation plate made of a thermoplastic polyimide resin. . 2. The heat dissipation plate is such that only a lower portion of the heating element, which is a main conduction area of heat generated by the heating element, is formed of an Au plating layer, and the other area is formed of a thermoplastic polyimide resin. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 3. A GaAs substrate having a heating element such as an FET formed on the surface thereof, and a recess formed by grinding the GaAs substrate on the lower surface of the GaAs substrate below the heating element to enhance heat dissipation. A semiconductor device comprising a thermoplastic polyimide resin filling the inside thereof. 4. The semiconductor device according to claim 3, wherein a Si resin is mixed with a thermoplastic polyimide resin. 5. The semiconductor device according to claim 1, wherein a conductive filler is mixed in the thermoplastic polyimide resin. 6. The semiconductor device according to claim 1, wherein the outermost layer on the back surface side of the GaAs substrate is a thermoplastic polyimide resin, and the thermoplastic polyimide resin is used as a die bonding material. . 7. A Ga having an element such as a FET formed on the surface thereof.
An As substrate, a via hole penetrating the GaAs substrate and electrically connecting the element to the back side of the GaAs substrate, an electrode portion formed in the via hole portion on the back surface of the GaAs substrate, the electrode portion excluding the electrode portion A semiconductor device comprising a ground portion formed on the back surface of a GaAs substrate, wherein the electrode portion and the ground portion are formed of a thermoplastic polyimide resin. 8. The semiconductor device according to claim 7, wherein the electrode portion and the ground portion are separated by a groove of about 50 μm. 9. An electrode pad and a ground portion formed corresponding to an electrode portion and a ground portion formed on the back surface of a semiconductor element to be mounted on a chip die bond portion on the ceramic substrate, formed on the ceramic substrate. A through hole for connecting the electrode pad and the ground portion to an external electrode is provided, and the electrode portion and the ground portion formed on the back surface of the semiconductor element are aligned with the electrode pad and the ground portion formed on the ceramic substrate, respectively. A semiconductor device package characterized by performing bonding. 10. A semiconductor device in which the semiconductor device according to claim 6 or 7 is mounted on the package for a semiconductor device according to claim 9.