JPH0965363A - Recording processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a recording processor which more increases the processing speed of NTSC signal conversion in a digital computing element. SOLUTION: The video signal obtained by A/D conversion of the output of a CCD 1 is stored in a first storage part 3a with one field as a unit. Data of (four vertical lines) × (m horizontal data blocks) out of stored data are transferred to an internal RAM 5, and a two-line portion of a luminance signal is generated at a time by an operation in a digital computing element 4. FM modulation processing is performed in the unit of data blocks in the case of even lines, and FM modulation of an odd line is performed when the processing of one even line is terminated. When the processing (including FM modulation) to generate the luminance signal of two lines is terminated, data of (four vertical lines) × (m horizontal data blocks) for which the luminance signal of next two lines should be generated are subjected to the same processing, and this processing is repeated up to the last line. Since transfer between an external RAM and the internal RAM 5 is reduced, the processing speed is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention A / D converts the CCD output of a subject image formed through an optical system to obtain NTS.
More specifically, the present invention relates to a recording processing device that records on a recording medium after C signal conversion processing, and more specifically, to a recording processing device that can perform NTSC signal conversion processing at high speed.

[0002]

2. Description of the Related Art In a recording processing apparatus such as an electronic still camera, in order to generate a luminance signal from CCD data, data for three lines in the vertical direction is basically required for vertical enhancement processing. This makes it possible to generate a luminance signal for one line from data for three lines. In such cases,
The A / D converted data of the CCD output is stored in an external RAM with a large capacity, and the external RAM is accessed by the digital arithmetic unit to perform the NTSC signal conversion processing.
There is a problem that the processing time is long because the access time is long.

[0003]

As a method for solving this, an internal RA of a digital arithmetic unit having a fast access time is used.
A circuit configuration is conceivable in which three lines are transferred to M, the internal RAM is accessed by a digital processor and processed (sequentially processed line by line) to be converted into an NTSC signal and recorded. FIG. 4 shows the internal R of the digital computing unit.
FIG. 5 is a diagram showing an example in which data for three lines is transferred to an AM to generate a luminance signal, and FIG. 5 is a flowchart for explaining the operation in that case. Initial setting is made for each circuit (step (hereinafter referred to as “S”) 301), the A / D converted CCD output is stored in the external RAM, and the internal RA is further stored.
Three lines are transferred to M (S302). In this case, since the capacity of the internal RAM is small, it is impossible to hold all the data for one line in the internal RAM. Therefore, the data is divided into several blocks and stored in the horizontal direction.

The digital processor performs color signal processing and luminance signal processing by accessing the internal RAM (S303). Next, FM modulation is performed and the data is transferred from the internal RAM to the external RAM (S304, S305). Then, the luminance signal processing for one line ends (S306).
Then, it is judged whether or not the process (for 525 lines) has been completed up to the final line, and when it is completed, the process for one frame is completed. In the above arithmetic processing, in order to reduce the processing time as much as possible, an internal RAM that can be accessed at high speed is used, and an internal RAM and an external R that has a slow access time
It is necessary to minimize data transfer with AM. RA is used for calculations that use a lot of data, such as filtering.
One of the factors that determines the processing speed is the access speed to M
Because it will be one. Further, although the internal RAM has a short access time, it has a small capacity as described above, so that the processing efficiency is poor and the processing time does not become so fast. An object of the present invention is to provide a recording processing device capable of further increasing the processing speed of NTSC signal conversion in a digital arithmetic unit.

[0005]

In order to achieve the above object, a recording processing apparatus according to the present invention stores data from a CCD in an external RAM and then stores an internal RA of a digital arithmetic unit.
In the recording processor for transferring to the external RAM and performing recording on the recording medium after performing the NTSC signal conversion processing by performing the arithmetic operation by the digital arithmetic unit in the recording medium, the number of vertical 4 lines × m horizontal m 1 block data is transferred from the external RAM to the internal RAM, and the first 3 lines and the next 3 lines of the vertical 4 lines are used to transfer the nth block data.
After the color signal processing is performed on the nth and (n + 1) th lines, the luminance signal processing is performed, and the FM modulation is performed on the nth line to obtain the nth FM modulated data and the (n + 1) th line. ) Th baseband data is transferred to the external RAM, and then four vertical lines for horizontal connection to the first block data × m horizontal second lines.
Block data is processed in the same manner as the first block data, and in this way, the same process is performed from the third block data to the block data at the end of the n-th line. After that, by performing FM modulation processing on the (n + 1) th line, the NTSC signal conversion processing is performed by the digital arithmetic unit. However, m and n are natural numbers.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a more preferred embodiment of the present invention will be described with reference to the drawings. 1 is a circuit block diagram showing an embodiment of a recording processing apparatus according to the present invention. C
A subject image is formed on the CD 1 by an optical system (not shown), and video data is output. The video data is converted into a digital signal by the A / D converter 2, and the external RAM 3
Is accumulated in The external RAM 3 is a storage unit 3 for two frames
1 of the video data from the A / D converter 2 having a and 3b
The field portion is accumulated in the first storage unit 3a. The video data stored in the first storage unit 3a has four vertical lines x
The data is transferred to the internal RAM 5 in units of horizontal m block data.

For the block data of vertical 4 lines × horizontal m transferred to the internal RAM 5, the digital arithmetic unit 4 converts the first, second and third lines of 3 lines × horizontal m data. The data is accessed, and further, the second, third, and fourth three lines × horizontal m data are accessed to perform digital processing of NTSC signal conversion as described later. The digital signal converted from the NTSC signal is stored in the second storage unit 3b, converted into an analog signal by the D / A converter 6, and recorded on the recording medium 8 by the recording circuit 7.

FIG. 2 is a diagram for explaining a method of transferring video data between the external RAM 3 and the internal RAM 5.
Of the one field stored in the external RAM 3, the data blocks a ₁₁ of vertical 4 lines × horizontal m from the upper left are first transferred to the internal RAM 5. When the digital processing is completed for this data block, this data is transferred to the second storage block 3b. Next, the continuous data block a ₁₂ is transferred to the right, the same process is performed, and when the process proceeds to the last part of the line, that is, the data block a _1p , the third, fourth, and fifth blocks continue. And the sixth vertical 4 lines × m horizontal pieces are transferred to the internal RAM 5 and the same processing is performed. In this way, one field is digitally processed up to the data block a _qp and transferred to the second recording unit 3b.

FIG. 3 is a flow chart for explaining the storage processing operation according to the present invention. First, initial setting such as resetting each circuit is performed (S301). CCD
The output of 1 is digitally converted by the A / D converter 2, one field's worth of data is stored in the first storage section 3a of the external RAM 3, and four vertical lines' worth * m horizontal data blocks are transferred to the internal RAM 5. (S302). The digital arithmetic unit 4 stores the first 3 data blocks from the internal RAM 5.
The line is read out and color signal processing and luminance signal processing are performed (Y _n line, even line n). Further, the next three lines are read out, and color signal processing and luminance signal processing are performed (Y _{n + 1} line, odd line (n + 1)). This is baseband processing for two lines (S303).

Then, the odd line data is saved in the second storage section 3b of the external RAM 3 without performing the FM modulation processing (S304). The FM-modulated signal is applied to the baseband-processed signal of the even-numbered line and the external RAM
3 is transferred to the second storage unit 3b (S305, S30).
6). Next, it is determined whether the processing of the luminance signal for one line is completed (S307). If the processing of the luminance signal for one line has not been completed, the process returns to S302, the next consecutive four vertical lines × m horizontal data blocks are transferred to the internal RAM, and the same processing is performed (S302 to S3).
06). When the processing of the even-numbered 1-line luminance signal is completed in this manner, the odd-numbered 1-line data is transferred from the second storage unit 3b to the internal RAM 5 and FM-modulated by the digital arithmetic unit 4 (S308). In this way, the FM modulation is performed for each data block on the even lines, and the FM modulation for one line is performed after the FM modulation for one even line is performed for the odd lines.
This is because the FM modulation requires that the signals be continuous in time and the signals at the top of the screen must be sequentially processed.

Next, it is judged whether or not the processing has been completed up to the final luminance signal line (S309). If the processing has not been completed up to the final luminance signal line, the procedure returns to S302, and the next four vertical lines are multiplied. The horizontal m data blocks are transferred to the internal RAM 5 and the same processing is performed. In this way, when the processing is completed up to the final luminance signal line of one field, the NTSC signal conversion processing is completed and the operation moves to recording on the recording medium. When the luminance signal processing of the first line and the luminance signal of the last line is performed, one line of the data block is missing. In this case, therefore, the same line is overlapped and processed.

[0012]

As described above, according to the present invention, the external R
Of the video data of one field stored in AM, four lines are transferred to the internal RAM, and the brightness signal for two lines is created by one transfer of the internal RAM, and FM modulation is performed. Therefore, although the internal RAM space is small, the efficiency of digital processing for converting into an NTSC signal is improved, and the processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a storage processing device according to the present invention.

FIG. 2 is a diagram for explaining a method of transferring video data between an external RAM 3 and an internal RAM 5.

FIG. 3 is a flowchart for explaining a storage processing operation according to the present invention.

FIG. 4 is a diagram for explaining a processing method in a conventional internal RAM.

FIG. 5 is a flowchart for explaining a conventional storage processing operation.

[Explanation of symbols]

 1 ... CCD 2 ... A / D converter 3 ... External RAM 3a ... 1st memory | storage part 3b ... 2nd memory | storage part 4 ... Digital arithmetic unit 5 ... Internal RAM 6 ... D / A converter 7 ... Recording circuit 8 ... Recording medium

Claims (1)

[Claims] 1. Data from a CCD is stored in an external RAM, then transferred to an internal RAM of a digital arithmetic unit, and an NTSC signal conversion process is carried out by the digital arithmetic unit, and then transferred to the external RAM. In a recording processing device for recording on a recording medium, the first block data of vertical 4 lines × horizontal m pieces is transferred from the external RAM to the internal RAM, and the first 3 lines of the vertical 4 lines and the next 3 lines are transferred. After performing color signal processing on the n-th and (n + 1) -th lines, the luminance signal processing and the FM modulation are performed on the n-th line.
The 4th FM modulated data and the (n + 1) th baseband data are transferred to the external RAM, and then the 4th vertical block is horizontally connected to the 1st block data. The same processing as that performed on the first block data is performed on the data. In this manner, the same processing is performed from the third block data to the block data at the end of the n-th line, and thereafter. A recording processing device, wherein the digital arithmetic unit performs an NTSC signal conversion process by performing an FM modulation process on the (n + 1) th line. However, m and n are natural numbers.