JPH10304356A - Parallel picture compression processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a high speed processing by a single control circuit with a simple configuration by providing a control circuit operating with frequencies which are integral times as high as the operating frequencies of plural picture compressing circuits. SOLUTION: An original picture 201 is converted into a digital picture by an A/D converting circuit 202, and a control circuit 203 stores a picture in a picture memory 204 with J×3 MHz frequencies. At the time of reading, an address generating circuit performs access to three different areas in the picture memory 204 at timings of the J×3 MHz frequencies, and successively reads picture data in each area. The read picture data are stored for a fixed time, and simultaneously outputted to each JPEG- LSI205. The control circuit 203 performs compression by using the JPEG- LSI205 operating with JMHz. Thus, the data can be simultaneously outputted to the tree JPEG- LSI205.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image compression processing device.

[0002]

2. Description of the Related Art In recent years, the capacity of a memory that can be accessed randomly has been expanded, and the capacity of the memory is high.
V) can be easily stored. However, it is still enough to process still images, but not enough to store moving image data directly in memory in real time. Therefore, it is necessary to perform image compression that also improves the efficiency of data transfer. But,
LSIs that use the JPEG method, which is a typical method for compressing a still image, also have a limit in real-time processing up to an image signal equivalent to NTSC.

FIG. 1 shows a general flowchart for compressing, transferring, and reproducing a moving image. As shown in FIG.
In moving images, image capture and image compression are alternately processed. 10-12 for the video not to be too unnatural
This repetition processing is required to be performed at a frame / second. JPEG for HDTV equivalent video signals
As a method of performing image compression processing, a method of performing JPEG processing in parallel is used. The parallel JPEG processing includes a method of performing processing in parallel with respect to a time axis (hereinafter, Conventional Example 1) and a method of dividing an input image and performing JPEG processing on the divided image (hereinafter, Conventional Example 2). Is typical.

In each of Conventional Examples 1 and 2, the size of one frame of an HDTV image is set to 1920 × 1056 pixels. In both examples, the time axis direction is 30 frames / sec, and thus an 8-bit RGB image is used. Further, one JPEG processing LSI can process an NTSC image (about 720 × 480 pixels) in one frame. One JPEG
In order to process an HDTV image by the LSI, the information amount of the HDTV image is about 6 Mbytes per frame for three color elements, and the information amount of the NTSC image is about 1 Mbyte per frame. flame/
Seconds), six JPEG_LSIs are required. In the conventional example taken here, as described above, 10
Up to 12 frames / second can be realized with three LSIs.

FIG. 5 shows a first conventional example of parallel image compression processing, and FIG. 6 shows a timing chart. The numbers in the timing chart indicate frame numbers. In Conventional Example 1, an image memory, a JPEG_LSI, an output memory after compression,
And a plurality of control circuits (three in this example). The size of the image memory is equal to the size of the original image, and the contents of the same frame as the original image are sequentially stored in the three image memories. In this system, high-speed processing is realized by performing processing for storing an original image in the image memory n and image compression by JPEG_LSI in parallel. As a feature of the first conventional example, as described above, since the size of the image memory is equal to the size of the original image (frame), the joint processing after the compression processing required for the second conventional example described below and the method of the present invention Is unnecessary.

FIG. 7 shows a conventional example 2 of parallel image compression processing, and FIG. 8 shows a timing chart. In Conventional Example 2, the image memory is divided into three parts. Therefore, the image memory is reduced to one third as compared with the conventional example 1. However, in this example, one frame is divided into three and compression processing is performed, so that a step of performing a combination processing after compression is required. A feature of the second conventional example is that the image memory only needs to be the same size as the size of the original image.

[0007]

As described above, the prior art 2
Although the two methods have been described, the drawbacks of each conventional example will be summarized here. The disadvantage of the first conventional example is that an input memory of "the number of controls for parallel processing x the size of the original image" is required (three original images in the first conventional example), and the circuit becomes large-scale. .

The disadvantage of the conventional example 2 is that, as shown in the timing chart of FIG.
High-speed control is required because only the time for a frame can be secured. Further, both the conventional examples 1 and 2 require the number of control circuits in parallel, which is also a problem to be improved.

The present invention has been made to solve these drawbacks and problems of the conventional system.

[0010]

Therefore, in the present invention, there is provided a control circuit 203 which operates at a frequency which is an integral multiple of the operation frequency of a plurality of image compression circuits (JPEG_LSI 205). The control circuit 203 divides the image data into a plurality and divides each of the divided image data into a plurality of JPEG images.
_LSI 205 are simultaneously input and controlled by a single control signal 210.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1, in moving images, image capture and image compression are alternately processed. In this embodiment,
This realizes high-speed processing in the "compression processing" portion of FIG. FIG. 2 is a block diagram of the present embodiment, and FIG. 3 is a detailed diagram of a control circuit and an image memory.

In this embodiment, three processes are executed in parallel, as in the conventional examples 1 and 2. In the control circuit 203 of the present embodiment, compression is performed using a JPEG_LSI 205 operating at J MHz. The control circuit 203 uses J × 3 MHz, which is three times the frequency of J MHz, in the address generation circuit 208. After the original image 201 is converted into a digital signal by the A / D converter 202, the control circuit 203 stores the image in the image memory 204 at the frequency of J × 3 MHz. At the time of reading, the address generation circuit is operated at the timing of the frequency of J × 3 MHz.
By accessing three different areas (in FIG. 5) in the image memory 204, the 208 reads out the image data in each area in the order of →→. The read image data is the data storage memory FI shown in FIG.
After being stored in the FO 209 and stored for a certain period of time, they are simultaneously output to the respective JPEG_LSIs 205. JPEG_
The image data compressed by the LSI 205 is temporarily stored in each compressed data memory 206.

By simultaneously outputting the image data to the JPEG_LSI 205, three JPEG_LSs are output.
The operation can be performed by one control signal 210 for I205.
That is, the operating frequency (J ×
3MHz), the image memory is accessed,
Thus, there is a margin for outputting image data to the JPEG_LSI 205 operating at MHz, and image data can be output simultaneously. Therefore, in the present embodiment, it is not necessary to have an image memory and a control circuit divided by the number of parallel processes as in Conventional Example 2, and control can be performed with a single image memory and a single control circuit.

[0014] This margin is also effective in the combining process after compressing the data. As can be seen from the timing chart of Conventional Example 2 in FIG. 8, only one frame time can be secured in the combining process. However, in the timing chart of the present embodiment in FIG. 4, the compressed data combining process has a time of three frames. . Therefore, a low-speed CPU can be used for the combining processing, and the cost of the combining processing circuit 207 in FIG. 2 can be reduced.

In the description of this embodiment, the number of parallel processes is limited to three, but the present invention is not limited to this number.

[0016]

EFFECTS OF THE INVENTION Importing and extracting original images, JPEG
Since the processing can be performed by a single control circuit, the circuit can be simplified. Since there is enough time for the compressed data combining process, a low-speed CPU can be used for the combining process.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of video compression.

FIG. 2 is a block diagram of the present invention.

FIG. 3 is a diagram illustrating the operation of a control circuit according to the present invention.

FIG. 4 is a timing chart of the present invention.

FIG. 5 is a block diagram of a conventional method 1.

FIG. 6 is a timing chart of the conventional method 1.

FIG. 7 is a block diagram of a conventional method 2;

FIG. 8 is a timing chart of the conventional method 2.

[Explanation of symbols]

 201 Original image 202 A / D converter 203 Control circuit 204 Image memory 205 JPEG_LSI 206 Compressed data memory 207 Combination processing circuit 208 Address generation circuit 209 FIFO 210 Control signal

Claims (9)

[Claims] 1. An image compression circuit having n (n is a natural number of 2 or more; the same is true in the following claims), and a control circuit operating at an integral multiple of an operation frequency of the image compression circuit. And a parallel image compression processing device. 2. The parallel image compression processing device according to claim 1, wherein said control circuit includes an address generation circuit for accessing an image memory at a frequency that is an integral multiple of an operation frequency of said image compression circuit. Parallel image compression processing device. 3. A control circuit for controlling n image compression circuits, dividing the image data into n data, and simultaneously inputting the divided image data to the n image compression circuits one by one. And a parallel image compression processing device. 4. A control circuit for operating the n image compression circuits with n image compression circuits and a single control signal;
A parallel image compression processing device having: 5. An image compression circuit comprising: n identical image compression circuits; and a control circuit operating at a frequency that is an integral multiple of an operation frequency of the image compression circuit, wherein the control circuit divides the image data into a plurality of pieces, and Parallel image compression processing device, wherein each of the image data thus obtained is simultaneously input one by one to the n image compression circuits, and a single control signal for operating the n image compression circuits is output. . 6. A parallel image compression processing device according to claim 5, wherein said control circuit includes an address generation circuit for accessing an image memory at a frequency which is an integral multiple of an operation frequency of said image compression circuit. Parallel image compression processing device. 7. The parallel image compression processing device according to claim 1, wherein said integer multiple is three times. 8. The parallel image compression processing apparatus according to claim 1, wherein said n
A parallel image compression processing device, wherein the number is three. 9. An image compression circuit having three identical image compression circuits and a control circuit operating at a frequency three times the operating frequency of the image compression circuit, wherein the control circuit divides the image data into three, A parallel image compression processing apparatus, wherein each of the image data thus obtained is simultaneously input one by one to the three image compression circuits, and a single control signal for operating the three image compression circuits is output.