JPH0865704A - Image processor - Google Patents

Abstract

PURPOSE: To provide an image processor which can process a larger quantity of pixel data by attaining the effective use of a memory that has the same capacity and access time as those of a conventional memory. CONSTITUTION: The digitized N-bit luminance signal Y and chroma signal C undergo the 3/4M reduction of their pixel data through a 3/4M reduction circuit 1 and then undergo the compression processing through the line memories 10a and 10b so that the space is reduced between the pixel data. Then the pixel data are written and read by a memory 11 of MN-bit width and then turned into the original state by the line memories 13a and 13b and a 4M/3 magnification circuit 2 through an operation reverse to the circuit 1. Thus it is possible to reduce and magnify the images by changing the speeds or writing and reading clocks or the the memory 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which uses a memory to perform image processing.

[0002]

2. Description of the Related Art FIG. 3 shows the configuration of a conventional image processing apparatus. In FIG. 3, 101 and 102 are memories, and 103 is a memory control circuit that controls addresses of the memories 101 and 102.

The image processing apparatus configured as described above is
The digitized luminance signal Y and color signal C are written in the memories 101 and 102, respectively, and these memories 101 and 1 are written.
An image can be reduced or enlarged by reading from 02 at a clock speed different from that of writing.

[0004]

However, in the above-mentioned conventional image processing apparatus, since the capacity of the memory is a factorial of 2, in the case of horizontal pixels of a factorial of 2, such as 256, 512, 1024. Good, but especially in case of PAL system 2
If it is not a factorial, a memory with a capacity one step larger is selected, so there is a problem that the memory becomes surplus and the cost of the memory becomes high. There was a problem of increasing the number of pixels.

Further, when trying to increase the number of horizontal pixels,
There has been a problem that an inexpensive memory with a slow access time cannot be used because the drive clock of the memory becomes faster.
In addition, the number of horizontal pixels has to be reduced according to the access time.

The present invention solves the above-mentioned conventional problems, and is capable of increasing the number of horizontal pixels with the same memory capacity and access time as compared with the conventional method, and is an image processing apparatus which is cheaper and has a higher number of pixels than the conventional method. The purpose is to provide.

[0007]

In order to achieve the above object, the present invention provides a digitized luminance signal Y and chrominance signal C.
The luminance signal Y of the N-bit input pixel data and the color signal C are combined, and the number of pixel data of the upper MN bits and the lower MN bits (M and N are integers of 1 or more) of the pixel data to be written in the memory are the same. 3 / 4M to reduce to 3 / 4M
A reduction circuit, a first line memory with an N-bit width that compresses the pixel data from the 3 / 4M reduction circuit by 3 / 4M, and writes / reads the pixel data from the first line memory. A memory with a 2MN bit width, a memory control circuit for controlling the address of this memory, and the pixel data read from this memory are 4M / 3.
A second line memory having an N-bit width, which is expanded to perform an operation opposite to that of the first line memory, and pixel data from the second line memory are separated into a luminance signal Y and a color signal C
It is provided with a 4M / 3 enlargement circuit which operates in the reverse of the M reduction circuit.

[0008]

According to the present invention, with the above configuration, the total number of pixel data of the luminance signal Y and the color signal C is set to 3 /.
By setting the total number of pixel data to 4M and compressing the total number of pixel data to 3 / 4M, and then writing to the memory, the memory capacity of the conventional memory becomes 3 / 4M, and the cost of the memory becomes low. Further, even with a memory having the same capacity and access time as the conventional one, it is possible to process 4M / 3 times as many pixel data.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an image processing apparatus according to an embodiment of the present invention. In FIG. 1, 1
Is a 3/4 M (3/4 M) reduction circuit, 2 is 4 M / 3 (3
4M) enlargement circuit. In the 3/4 M reduction circuit 1, 3, 4, 5, 6, 7, and 8 are flip-flops or latches, and 9 is a selector. In the 4M / 3 enlargement circuit 2, 14, 15, 16 are flip-flops or latches, 17 is a two-stage flip-flop or latch, and 18 is a selector. 10a, 10b
Is a first line memory, 11 is a memory, 12 is a memory control circuit, and 13a and 13b are second line memories.

Next, the operation of the above embodiment will be described.
First, the 3 / 4M reduction circuit 1 is a digitized N bit
Input luminance signal Y and color signal C (N is an integer of 1 or more)
Then, as shown in FIG. 2, the data of the luminance signal Y and the color signal C
Set the total number to 3 / 4M, and set the number of Ya and Ca data to each other.
Do the same. That is, the flip flop 3
The brightness signal Y input to the internal memory 10a is fetched and
The brightness input to the line memory 10b by the flip-flop 4.
Degree signal Y is taken in. The data to import is shown in Fig. 2.
And Y₁, Y₂, Y₃, Y_Five, Y₆, Y₇, Y₉, Y
_Ten, Y₁₁Is taken in by flip-flop 3 and Y_Four,
Y₈, Y₁₂Is taken in by the flip-flop 4. Flip
C on flops 7 and 8₁, C₃, C_Five, C₇, C₉,
C₁₁The data of the color signal is shifted by 2 clocks. Next
To the flip-flop 4 by the selector 9
The luminance signal Y and the color shifted by the flip-flops 7 and 8
The signal C is synthesized. On the other hand, flip-flops 5 and 6
Is the luminance signal Y₁And color signal C₁, Y ₂And Y_Four, Y₃And C
₃Captured by flip-flop 3 to synchronize
The shifted data is shifted by 2 clocks. For the above operation
Therefore, the total number of pixel data is set to 3 / 4M,
The number of data can be the same as each other.

The line memories 10a and 10b are 3/4 M
It is a line memory of H × N bits (H is the number of horizontal pixels), and data Ya and Ca from the 3 / 4M reduction circuit 1 are written, and as shown in FIG. Input to the memory 11. The memory 11 is a memory having a 2MN bit width (M and N are integers of 1 or more). In this embodiment, M is 1. The memory control circuit 12
The outputs Yb and Cb of the line memories 10a and 10b are written / read to / from the memory 11. For writing, Yb is used for the upper MN bit and Cb is used for the lower MN bit (upper / lower reverse is also possible). At this time, the image is reduced by reading with a clock at a speed different from that at the time of writing,
Can be expanded. Next, the line memories 13a and 13b of 3/4 MH × N bits respectively write the data Yc and Cc read from the memory 11 and read them at the vacant timing as shown in FIG.
The reverse operation of a and 10b is performed.

Next, the 4M / 3 enlargement circuit 2 takes in the data Yd and Cd read from the line memories 13a and 13b, separates the luminance signal Y and the chrominance signal C, and restores the timing shown in FIG. That is, the flip-flop 16 takes in C ₁ , C ₃ , C ₅ , C ₇ , C ₉ , and C ₁₁ of Cd in FIG. The Cd Y ₄ , Y ₈ and Y ₁₂ of FIG. 2 are fetched and shifted by 2 clocks by the flip-flop 17, and the selector 1
At 8, the data from the flip-flop 14 and the data from the flip-flop 17 are combined. As a result, Yo,
Co is as shown in FIG. That is, the 4M / 3 enlargement circuit 2 can reverse the operation of the 3 / 4M reduction circuit 1 to restore the data order.

As described above, according to the present embodiment, the pixel data is reduced to 3/4 M before being written in the memory 11, so that the same memory capacity and access time are 4 M / m.
Image processing of triple pixel data can be performed. Although the above embodiment is for the case of M = 1, even when M is an integer of 1 or more, it can be easily realized by the concept of M = 1.

[0014]

As is apparent from the above embodiment, the present invention reduces the number of data to 3/4 M before writing it in the memory, so that the image processing can be performed by the conventional memory having the capacity of 3/4 M. Can be performed and the cost of memory can be reduced. Further, with the memory having the same capacity and access time, it is possible to process pixel data 4M / 3 times as large as the conventional one. From the above, it is possible to realize an image processing apparatus that is cheaper and has a higher number of pixels than the conventional image processing apparatus.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a timing chart of the device.

FIG. 3 is a schematic block diagram of a conventional image processing apparatus.

[Explanation of symbols]

1 3 / 4M reduction circuit 2 4M / 3 enlargement circuit 3, 4, 5, 6, 7, 8, 14, 15, 16, 17 flip-flop or latch 9,18 selector 10a, 10b, 13a, 13b line memory 11 memory 12 Memory control circuit

Claims (2)

[Claims] 1. A luminance signal Y and a color signal C which are digitized.
The luminance signal Y of the N-bit input pixel data and the color signal C are combined, and the number of pixel data of the upper MN bits and the lower MN bits (M and N are integers of 1 or more) of the pixel data to be written in the memory are the same. To reduce by 3 / 4M to achieve
An image processing apparatus comprising: a unit for expanding data read from the memory to 4M / 3. 2. A 3 / 4M reduction circuit for compressing the total number of pixel data to 3 / 4M before writing to a memory, and said 3/4
A first line memory having an N bit width for compressing the pixel data from the M reduction circuit by 3/4 M, and a memory having a 2 MN bit width for writing / reading the pixel data from the first line memory; A memory control circuit for controlling addresses of the memory, and a second line having an N-bit width for expanding pixel data read from the memory by 4M / 3 and performing an operation opposite to that of the first line memory. An image processing apparatus comprising: a memory; and a 4M / 3 enlargement circuit that separates pixel data from the second line memory into a luminance signal Y and a color signal C and performs an operation reverse to that of a 3 / 4M reduction circuit.