JPH0936371A - Method for manufacturing thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin-film transistor where an ion implantation process which can implant ions with one ion implantation and is simpler than a conventional process is included, throughput is proper and cost can be reduced, and a thin-film transistor with a specific performance and reliability can be realized. SOLUTION: After eliminating a gate insulation film 103 covering an active layer 102 at a part for forming source/drain regions 105a and 105b by etching, an impurity is implanted to the active layer 102 at the exposed part, thus directly injecting the impurity into the active layer 102 and hence effectively injecting the impurity at a low acceleration voltage, utilizing, for example, photo resist which can be extremely easily machined when manufacturing a TFT substrate where n and p types are mixed, and easily manufacturing a thing-film transistor with a small number of processes.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art Thin film transistors
or; hereinafter, abbreviated as TFT) is often used as a switching element in an active matrix type liquid crystal display device. The active matrix type liquid crystal display device is a display device which has been actively developed due to its excellent display characteristics.

In such an active matrix type liquid crystal display device, amorphous silicon (a-S) is used as a TFT.
a) Si TFT system using i) and polycrystalline silicon (p
There is a p-SiTFT system using -Si).

The above-mentioned a-Si TFT has a process temperature of
It is as low as 300 ℃ to about 400 ℃, and large glass substrates can be used, allowing for larger screens and multiple chamfering.

However, since the mobility of the a-Si TFT is generally small, it is difficult to apply it to a so-called integrated drive circuit system in which a liquid crystal drive circuit system is formed on the peripheral portion of the substrate around the screen. For this reason, as the screen becomes finer, it becomes more difficult to connect the liquid crystal drive circuit system to the wiring of the pixel section, and the conventional separate liquid crystal driver IC must be used.・ High definition screen,
There are problems that it is a major obstacle to downsizing as a liquid crystal display device, and that production yield is low and cost is also hindered.

On the other hand, since the p-SiTFT has a large mobility as a TFT, it is possible to realize the drive circuit integrated system as described above, which is advantageous for miniaturization of pixels and high definition of a screen.

In recent years, research and development have been carried out to establish a manufacturing method for manufacturing such a p-SiTFT at a lower temperature, which is a maximum temperature in the process of about 500 ° C to 600 ° C.

This is because the maximum temperature during the process is 500 ° C.
This is because at 600 ° C., it is possible to use a glass substrate that has a lower shrinkage rate due to heat treatment than a quartz substrate, is easy to handle, and can also realize cost reduction of materials. Moreover, in recent years, the material properties of the glass substrate itself have been improved, and problems such as elution of alkalis have been solved, and it is because the glass substrate is in an environment where it can be used.

As an example of a conventional manufacturing process having such a maximum temperature of 500 ° C. to 600 ° C., an nMOS type p-Si is used.
A general method of manufacturing a TFT will be described with reference to FIGS. Here, a p-Si material having a planar structure and using a p-Si material for a gate electrode as a TFT is used.
The case of TFT is taken as an example.

On the insulating substrate 301, the active layer 302 becomes a.
After the -Si thin film is formed by the LP-CVD (low pressure chemical vapor deposition) method, the a-Si thin film is polycrystallized by the solid phase growth method.

Next, after performing island-shaped etching by the CDE (chemical dry etching) method, LP-CV is used.
An oxide film to be the gate insulating film 303 is formed by the D method (FIG. 3A).

Next, a p-Si thin film 304 'to be the gate electrode 304 is formed by the LP-CVD method, and then P (phosphorus) is added by the ion doping method as p-type for this gate electrode.
It is injected into the Si thin film 304 '. (FIG.3 (b)).

Next, after the P implanted in the p-Si thin film 304 'is activated by the annealing method, it is etched by the CDE method to form the gate electrode 304. The activation reduces the resistance of the gate electrode 304. (FIG. 3 (c)).

Next, P is implanted into the active layer 302 by an ion doping method using the gate electrode 304 as a self-alignment mask. At this time, P is the gate electrode 3
04 and the gate insulating film 303 (FIG. 3).
(D)).

Next, the source / drain regions 305a, 305a are activated by activating the P implanted in the active layer by an annealing method.
After forming b, the interlayer insulating film 306 is formed by the APCVD (normal pressure chemical vapor deposition) method (FIG. 3E).

Next, contact holes 307a and 307b are formed, Al (aluminum thin film) is formed by a sputtering method, and then this is etched to form wirings 308a and 308a respectively connected to the source / drain regions 305a and 305b. b
To form (FIG. 3 (f)).

[0017]

However, in the conventional method for manufacturing a p-Si TFT as described above, the first problem is that the source / source in the step shown in FIG.
When implanting an impurity (for example, P described above) into the active layer 302 to form the drain regions 305a and 305b, an extremely large acceleration voltage is required to accelerate the impurity. This is because a large acceleration (kinetic energy) is required to pass the impurities through the gate insulating film 303 and reach the active layer 302.

Since impurities are implanted by using such a large acceleration voltage, there is a problem that implantation damage is caused to the active layer 302 which is polycrystallized to have a large grain size.

This implantation damage has an activation temperature of 800 to 900.
In the high temperature annealing / high temperature process of about ℃, impurities are bonded into the Si crystal, so that it is not a practical problem.

However, during the medium to low temperature annealing at 500 to 600 ° C. and the medium to low temperature process, they remain as damages in the crystal of the polycrystallized active layer 302, and as a result, the field effect transfer as the p-Si TFT. There is a problem that the degree is greatly reduced.

Further, the thickness of the gate insulating film of the planar type TFT is 50 to 100 nm. In this case, the acceleration voltage is
Even when set to 100 keV, only about 2/3 to 1/2 of the total amount of impurities projected for implantation reach the active layer 302, and the rest is trapped in the gate insulating film.

Therefore, the required injection amount is 1.5 to 2
Since a double amount must be used at the time of injection, the process requires a long time and there is a problem that throughput is low. .

In the case of the drive circuit integrated type, the n-type and the p-type are formed on the same substrate as the substrate on which the pixel switching elements are formed.
Although two types of TFTs may be manufactured, p-type TFTs must be covered when n-type impurities are injected, and n-type TFTs must be covered when p-type impurities are injected. When the so-called ion implantation method, in which the impurities are mass-separated and the ions are injected, is used, a resist is generally used as a coating protective film of the TFT.

However, in the case of using the so-called ion shower method, which is applicable to the production of a large substrate without mass separation of impurities as described above, the product of the beam current of the ion implantation and the acceleration voltage is used. If the implantation power defined by the above is large, there is a problem that the resist is remarkably lost or disappears until it becomes unpractical due to self-heat storage of ion implantation.

Further, the impurities penetrate the silicon oxide film (SiO _X ) forming the gate insulating film to reach the active layer, but when the SiO _X penetrates, the O _X reaches the active layer together with the impurities. There is a problem that this causes the knock-on phenomenon. As measures against these problems, for example, the use of a metal mask has been proposed, and some have attempted to put it into practical use. However, it is practically difficult to manufacture such a metal mask for a TFT that requires extremely high precision. Moreover, the problem that the manufacturing process is considerably complicated as compared with the resist mask is unavoidable.

That is, when a resist mask is used,
The n-type and p-type can be formed by performing resist patterning at least twice and ion implantation twice. However,
When a metal mask is used, the number of steps of forming an Al film twice and etching the aluminum film four times is increased as compared with a resist mask.

The second problem is that the same impurity implantation step is required twice. That is, the first time is the implantation process into the gate electrode, and the second time is the source
This is a step of implanting into the drain region. The reason why such two implantation steps are required is that the acceleration voltage at the time of implantation is different.

It is necessary to prevent impurities from remaining in the gate electrode during the first impurity implantation, passing through the gate insulating film and reaching the active layer. Therefore, the implantation is performed with a relatively low acceleration voltage of about 30 keV.

On the other hand, during the second impurity implantation, the impurities do not reach the active layer below the gate electrode, reach the active layer through the gate insulating film, and stop at the active layer.
It is necessary not to penetrate in the future. Therefore, 1
The injection is performed at a relatively high acceleration voltage of about 00 keV. Thus, two injection steps are required.

Therefore, in the conventional p-SiTFT manufacturing method, the impurity implantation step is extremely complicated, and an ion implantation apparatus with a special accelerating voltage specification is required to carry out the step.

Further, since the active layer is largely damaged during the impurity implantation and 100% of the accelerated impurities do not reach the active layer, it takes a long time to implant a desired doping amount and the gate electrode is formed. Since the ion implantation conditions for the p-Si film, which is the material, and the ion implantation conditions for the active layer are different, it is necessary to perform two different ion implantation steps despite the same impurity implantation. There is a problem that it is extremely complicated.

Further, since the resist cannot be used as a mask for ion implantation, the mask patterning process is also very complicated.

The present invention has been made to solve such a problem, and an object thereof is to achieve ion implantation required only by one time of ion implantation, which is extremely simpler than conventional ion implantation. It is an object of the present invention to provide a method of manufacturing a thin film transistor, which includes steps, has a good throughput, can realize cost reduction, and can realize a thin film transistor having predetermined performance and reliability.

[0034]

According to the method of manufacturing a thin film transistor of the present invention, firstly, a step of forming an active layer using a semiconductor thin film on an insulating substrate, and a gate insulation covering at least a channel region of the active layer. A step of forming a film, a step of forming a gate electrode,
A method of manufacturing a thin film transistor, comprising the step of forming a drain region by an impurity implantation method,
Implanting impurities into the drain region and implanting impurities into the material of the gate electrode; and, after implanting the impurities, form an insulating film using the same material as the gate insulating film, and form the film in the source / drain regions. And a step of forming an upper insulating film.

Secondly, in the above method of manufacturing a thin film transistor, the step of implanting the impurities is a step of using an ion doping apparatus without using a mass separation apparatus.

Thirdly, a step of forming an active layer using a semiconductor thin film on an insulating substrate, a step of forming a gate insulating film, a step of forming a gate electrode, and source / drain on the semiconductor thin film. In a method of manufacturing a thin film transistor, including a step of forming a region by an impurity implantation method,
Removing the gate insulating film on the source / drain regions of the gate insulating film; and implanting impurities into the source / drain regions by ion shower and implanting impurities into the material of the gate electrode. ,
A step of forming an insulating film covering at least the source / drain regions to the side end of the gate insulating film using the same material as the gate insulating film.

Fourthly, a step of forming an active layer using a semiconductor thin film on an insulating substrate, a step of forming a gate insulating film, a step of forming a gate electrode, and the semiconductor thin film by an impurity implantation method. And a step of implanting impurities to form source / drain regions, wherein a plurality of n-type and p-type thin film transistors different from each other are arranged on the same substrate. Among the plurality of p-type thin film transistors different from each other, a step of covering one type thin film transistor with a photoresist that prevents penetration of impurities, and a mold covered with the photoresist by ion shower Impurities are implanted into the source / drain regions of the thin film transistor exposed by a different type, and the thin film transistor is exposed. A step of injecting impurities into the material of the gate electrode of the transistor, a step of removing the photoresist after the step of injecting the impurities by the ion shower, and at least the source / drain regions on the side of the gate insulating film. And a step of forming an insulating film that covers the end using the same material as the gate insulating film.

In the above fourth manufacturing method,
For example, if an n-type thin film transistor is first covered with a photoresist to expose the p-type, impurities are first implanted into the exposed p-type. And then, this time p
If the n-type thin film transistor is covered with photoresist to expose the n-type, impurities are injected into the exposed n-type. In this way, the n-type impurity and the p-type impurity can be separately injected to form the n-type thin film transistor and the p-type thin film transistor separately.

In the p-SiTFT manufacturing method of the present invention, as described above, the gate electrode is masked with the gate insulating film covering the active layer in the regions where the impurities are to be implanted, that is, the portions forming the source / drain regions. As a result, after removing by etching, impurities are implanted into the exposed portion of the active layer.

This prevents impurities from penetrating the gate insulating film as in the conventional manufacturing method, and impurities can be directly injected into the active layer.

Therefore, by adopting such means, it is possible to inject the impurities into the active layer by using an acceleration voltage which is much lower than that of the conventional one.

As a result, it is possible to minimize impurity implantation damage to the polycrystallized active layer.

Further, since the impurity is directly injected into the active layer as described above, the impurity is not trapped in the gate insulating film at all.
It can be injected into the 00% active layer.

Further, since the dose amount converted into the required dope amount can be injected, the conventional redundant injection time corresponding to the redundant dose amount can be greatly shortened, in other words, the injection can be performed. The power can also be reduced.

Moreover, a general photoresist mask, which is extremely simple in processing such as exposure, etching and removal as compared with a metal mask, can be preferably used even when the so-called ion shower method is used. Therefore,
Combined with the ion shower method and the photoresist mask used at that time, the manufacturing process can be greatly simplified.

Further, p which is a material for forming the gate electrode is used.
-Since the impurity implantation into the -Si film and the active layer can be performed under the same implantation condition, the implantation step which was conventionally required twice under different implantation conditions can be performed once. The process can be simplified and shortened.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION A method of manufacturing a thin film transistor according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing a method of manufacturing a thin film transistor according to the present invention. Here, in this example, similar to the TFT taken up as a conventional example, a case of manufacturing an n-type p-Si TFT having a planar structure provided with a gate electrode formed of p-Si as a material will be described.

A to be the active layer 102 on the insulating substrate 101
After forming a -Si thin film by the LP-CVD method,
-Polycrystallize the Si thin film by the solid phase growth method.

Subsequently, the a-Si thin film is etched into an island shape by the CDE method, and then, as an insulating film to be the gate insulating film 103 by the LP-CVD method, for example, LTO.
A film is formed (FIG. 1A).

Next, a p-Si thin film 105 is formed by LP-CVD as a film for forming the gate electrode 104 (FIG. 1B).

Then, the p-Si thin film 10 is formed by the CDE method.
5 is patterned by etching to form the gate electrode 10
4 is formed, the portion of the gate insulating film 103 which is not covered with the gate electrode 104 and which is exposed is removed by etching by a wet etching method using hydrofluoric acid. That is, the gate electrode 104 serves as a mask during this etching (FIG. 1C).

Next, P (phosphorus) is added as an impurity by the ion shower method to the source / drain region 1 of the active layer 102.
Implantation is performed at the same time (with the same ion shower) into the portions to be 05a and b and the gate electrode 104.

Here, when P is injected into the active layer 102, the gate electrode 104 serves as a self-alignment mask that covers the gate insulating film 103 and the channel region 110 of the active layer 102, and the active layer 102 that is not covered with the self alignment mask. P is directly injected from the surface into the portions to be the source / drain regions 105a and 105b. At this time, P is also implanted into the gate electrode 104 directly from the surface thereof similarly to the source / drain regions 105a and 105b of the active layer 102 (FIG. 1D).

Next, as the first interlayer insulating film 106, an oxide film of the same material as the gate insulating film 103 (here, an LTO film) is formed so as to cover the source / drain regions 105a and 105b of the active layer 102 and the gate electrode 102. ) Is LP-CVD
The film is formed by a method. Here, the first interlayer insulating film 106
Is preferably formed of the same material as that of the gate insulating film 103 because it can be manufactured as a TFT having a structure that is almost the same as that of a conventional structure TFT, and the manufacturing method advantages of the present invention can be obtained. is there. This first
When the interlayer insulating film 106 is an insulating film made of a material different from that of the gate insulating film 103, the electric field and the insulating state in the vicinity of the boundary between the two become unique, and as a result,
TFT designed with the same specifications as the conventional structure TFT
The performance and specifications are different from, and the performance is different from the design specification (prediction). Alternatively, in order to adapt to the peculiar performance, the design specifications must be changed to peculiar ones, and the setting and the design management become complicated. Therefore, in order to avoid such complication, it is preferable to use the above-mentioned materials.

Then, the second interlayer insulating film 107 is formed by the AP-CVD method. During this process, P injected into the active layer 102 and the gate electrode 104 is activated, and
The drain regions 105a and 105b are completed, and the gate electrode 1
04 has a low resistance (FIG. 1 (e)).

Then, the source / drain region 1 is penetrated through the first interlayer insulating film 106 and the second interlayer insulating film 107.
Contact hole 108 exposing part of 05a, b
Drill a and b.

After forming an Al film by the sputtering method, this is patterned by etching to form the wiring 1
09a, b are formed. (FIG. 1 (f)).

Through the manufacturing steps according to the present invention as described above, the main part of the p-Si TFT according to the present invention can be manufactured.

As described above, the p-SiTF according to the present invention is used.
According to the manufacturing method of T, the gate electrode 104 is used as a mask to form the gate insulating film 103 covering the active layer 102 in the regions where the impurities are to be implanted, that is, the portions where the source / drain regions 105a and 105b are to be formed. After removing by etching, impurities are implanted into the exposed portion of active layer 102. This prevents impurities from penetrating the gate insulating film unlike the conventional manufacturing method.
Impurities can be directly injected into the active layer 102.

Therefore, in the present invention, it is possible to implant impurities into the portions of the active layer 102 where the source / drain regions 105a and 105b are formed by using an acceleration voltage that is much lower than that of the conventional one.

As a result, the implantation damage of impurities to the gate insulating film 103 and the channel region 110 of the polycrystallized active layer 102 is completely eliminated, or is suppressed to a minimum level which can be sufficiently ignored for the operation performance of the TFT. You can

Further, since the impurities are directly implanted into the active layer 102 as described above, impurities are completely prevented from being trapped in the gate insulating film 103 on the way.
The projected impurities can be injected into the active layer 102 100% effectively.

Further, since it is possible to inject all of the dose amount converted into the necessary dope amount, it is possible to greatly shorten the conventional redundant injection time corresponding to the redundant dose amount. In other words, The acceleration power at the time of injection can be reduced.

Moreover, since impurity implantation can be performed with low acceleration energy as described above, although not shown in FIG. 1 of the above example, for example, p-type TFTs and n-type TFTs are mixed on the same substrate. In the case where it is necessary to separately implant each p-type / n-type and when the implantation is performed by using the ion shower method, compared with a metal mask, exposure, etching, removal, etc. A general photoresist mask, which is extremely easy to process, can be preferably used. Therefore, combined with the adoption of the ion shower method and the adoption of the photoresist mask at that time,
Even when the p-type / n-type process is separately performed, the manufacturing process can be greatly simplified and the time can be shortened.

Furthermore, since the impurity implantation for lowering the resistance of the p-Si film, which is the material for forming the gate electrode 104, and the impurity implantation for the active layer 102 can be performed under the same implantation condition, the conventional technique is used. 2 with different injection conditions
Since the injection process, which has been required a number of times, can be executed once, the process can be simplified and shortened.

In the above example, the gate insulating film 1
In the step of etching 03 (FIG. 1 (c)), all the gate insulating film 103 covering the portions to be the source / drain regions 105a and 105b was removed, but as shown in FIG. Both sides may be partially left.

By adopting such a method, the LDD (lightly doped drain) region 20 is formed at the same time as the formation of the source / drain regions 105a and 105b, as shown in FIG.
It is also possible to form 1a and 1b.

Further, in the above example, the active layer 102 is formed of an a-Si thin film by the LP-CVD method. However, in addition to this, the a-Si thin film is formed by, for example, the plasma CVD method. Not to mention good things.

Further, in the above example, the solid-phase growth method was used for polycrystallizing a-Si, but a laser annealing method or a lamp annealing method may be used instead of the solid-phase growth method.

Although the p-Si film is used as the material for forming the gate electrode 104, a film of Al, refractory metal, or the like may be used instead. However, even in this case, it is necessary that the metal gate electrode be a combination of a material and an etchant that can be used as a mask during etching of the gate insulating film 103.

Further, in the present example, an example of the case of an n-type p-Si TFT having a planar structure is shown as a TFT to be manufactured, but the manufacturing method according to the present invention is also applicable to other p-Si TFTs, for example. It goes without saying that it is also applicable to p-SiTFT and the like.

[0073]

As is clear from the detailed description above, according to the present invention, it is possible to realize the necessary ion implantation by only one ion implantation, which includes a significantly simpler ion implantation process than the conventional one. Therefore, it is possible to provide a method for manufacturing a thin film transistor, which has good throughput, can realize cost reduction, and can realize a thin film transistor having predetermined performance and reliability.

[Brief description of drawings]

FIG. 1 is a diagram showing a method for manufacturing a p-Si TFT according to the present invention.

FIG. 2 is a diagram showing a manufacturing method in which LDD (lightly doped drain) regions 201a and 201b are formed by partially leaving gate insulating film 103 on both sides of gate electrode 104.

FIG. 3 is a diagram showing an example of a conventional p-Si TFT manufacturing method.

[Explanation of symbols]

 101 Insulation substrate 102 Active layer 103 Gate insulation film 104 Gate electrode 105 p-Si thin film 106 First interlayer insulation film 107 Second insulation layer Film 108 ... Contact hole 109 ... Wiring 110 ... Channel region

Claims (4)

[Claims] 1. A step of forming an active layer using a semiconductor thin film on an insulating substrate, a step of forming a gate insulating film covering at least a channel region of the active layer, a step of forming a gate electrode, and the semiconductor. In a method of manufacturing a thin film transistor, which includes a step of forming source / drain regions in a thin film by an impurity implantation method, a step of implanting impurities in the source / drain regions and implanting impurities in the material of the gate electrode, And the step of forming an insulating film using the same material as the gate insulating film and using the film as an insulating film on the source / drain regions. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the step of implanting the impurities is a step of using an ion doping apparatus without using a mass separation apparatus. . 3. A step of forming an active layer using a semiconductor thin film on an insulating substrate; a step of forming a gate insulating film; a step of forming a gate electrode;
A method of manufacturing a thin film transistor, comprising a step of forming a drain region by an impurity implantation method, a step of removing a gate insulating film on the source / drain region of the gate insulating film, and a step of forming an ion shower on the source / drain region. The step of injecting impurities and also injecting impurities into the material of the gate electrode, and the insulating film covering at least the source / drain regions up to the side edges of the gate insulating film are made of the same material as the gate insulating film. A method of manufacturing a thin film transistor, comprising: 4. A step of forming an active layer using a semiconductor thin film on an insulating substrate, a step of forming a gate insulating film, a step of forming a gate electrode, and implanting an impurity into the semiconductor thin film by an impurity implantation method. Forming a source / drain region by arranging a plurality of n-type and p-type thin film transistors different from each other on the same substrate. Of a plurality of different thin film transistors, one type of thin film transistor is covered with a photoresist that prevents penetration of the impurities, and exposed by an ion shower with a different type from the type coated with the photoresist. Impurity is implanted into the source / drain region of the other thin film transistor, and A step of injecting impurities into the material of the gate electrode, a step of removing the photoresist after the step of injecting impurities by the ion shower, and at least on the source / drain regions to the side edges of the gate insulating film. And a step of forming an insulating film that covers the gate insulating film using the same material as that of the gate insulating film.