JPH0936042A - Formation of semiconductor single crystal layer and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely provide a single crystal layer in a desired shape by forming the semiconductor single crystal layer by permitting the flat plane pattern of the seed part to be a pattern that surrounds the prescribed area on an amorphous semiconductor layer and single-crystallizing the prescribed area of the amorphous semiconductor layer by solid-phase epitaxial growing. SOLUTION: The surface of a silicon single crystal substrate 10 is covered with an oxide film 20, and linear seed parts 30a, 30b, 30c and 30d are provided by patterning the part of the oxide film 20. The internal area 60 surrounded by the seed parts 30a, 30b, 30c and 30d is completely single-crystallized by the connection between the single crystal layers grown by having each seed part as the origin. Therefore, as a result, the seed parts are formed so as to surround the single crystal area 60 to be obtained. Thus, when the flat plane layout is decided, the shape of the single crystal area is unconditionally decided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor single crystal layer and a semiconductor device, and more particularly to SOI (Si
The present invention relates to a method for manufacturing a Licon On Insulator) structure and a highly integrated semiconductor integrated circuit device using an SOI structure.

[0002]

2. Description of the Related Art A semiconductor device using an SOI structure has a simpler element isolation and a higher degree of integration than a conventional semiconductor device in which elements are formed in a substrate, and high-speed operation of the element by reducing stray capacitance. Since it is also possible, active research and development is being conducted.

The technology for producing the SOI structure is roughly classified into a wafer bonding method and an oxygen ion implantation method (SI).
MOX method) or the like to form an SOI structure at the wafer stage, and solid phase epitaxial growth (So
lid phase epitaxy (SPE), etc.
There is a method of forming an I structure.

The method using the SPE method has an advantage that the SOI structure can be formed at an extremely low cost as compared with the method using the SOI wafer.

[0005]

The applicant of the present invention is S
A method for manufacturing an SOI structure using the PE method at a simpler and lower cost has been previously proposed (Japanese Patent Application No. 6-1936).
04). An outline of this manufacturing method is shown in FIGS.
Is shown in

The respective steps will be briefly described below.

As shown in FIG. 12A, an insulating film 1100 is formed on the surface of the Si substrate surface 1000. Next, as shown in FIG. 12B, a part of the insulating film is removed by etching to form a seed part (seed crystal part). At this time, the natural oxide film 1200 exists in the seed crystal portion.

Next, as shown in FIG. 12 (c), the natural oxide film 1200 is removed by immersing it in a dilute HF solution for several seconds, and at the same time, the Si surface is terminated by hydrogen atoms to be inactivated to effect natural oxidation. Inhibits film regrowth.

Next, as shown in FIG. 12 (d), the film is inserted into the apparatus at room temperature and a small amount of SiH ₄ gas is flown to raise the temperature to the film formation temperature while suppressing the regrowth of the natural oxide film.
After that, an amorphous Si film 1300 is formed.

Next, as shown in FIG.
The single crystal layer 1 is subjected to a heat treatment at about ℃ to cause solid phase epitaxial growth starting from the seed portion (seed crystal portion).
400 is processed by dry etching to form a desired single crystal layer (single crystal island) 1500.

According to such elemental process technology, a high-performance element can be manufactured at an extremely low price. The present inventor examined the SPE technique from various viewpoints in order to form an ultrahighly integrated IC by utilizing such element process technique. As a result, the following things became clear.

That is, according to the research by the inventor of the present application, (1
00) SPE using a single crystal plane and a stripe-shaped (linear) seed extending in the crystal direction equivalent to <100>
It has been found that when the single crystal layer is formed by the method, the planar layout shape of the obtained single crystal layer becomes a triangular shape at the end portion of the seed, as shown in FIG.

In FIG. 13, reference numeral 30 is a seed portion, reference numeral 1100 is a surface oxide film, reference numeral 1500 is a single crystal region, reference numeral 1600 is a polycrystalline region, reference numeral 1700, 1710,172
Each of 0 is an edge portion of the single crystal region (a region forming the above-mentioned triangular shape, where θ = 45 degrees in the figure).

In such a single crystal region having a sharp tip, electric field concentration is likely to occur, and there is a problem in that the layout is wasteful. Therefore, it is difficult to design and manufacture a device.

The present invention was obtained by the present inventor.
The present invention has been made based on the above knowledge, and an object thereof is to provide a method for effectively forming a desired single crystal layer by using the SPE method, and a semiconductor device using the method.

[0016]

[Means for Solving the Problems]

(1) The present invention according to claim 1 uses the (100) equivalent plane as a seed portion (seed crystal portion) to single crystallize an amorphous semiconductor layer by an SPE method to form a single crystal layer on an insulating film. And forming a plane pattern of the seed portion around a predetermined region of the amorphous semiconductor layer, and performing solid phase epitaxial growth on the predetermined region of the amorphous semiconductor layer surrounded by the seed portion. A single crystal is formed by the (SPE) method to form the desired semiconductor single crystal layer.

That is, in the invention of this claim, as a result,
The seed portion is formed so as to surround the single crystal region (desired single crystal region) to be obtained.

With this structure, SPE is generated from the surrounding seed portions, and the single crystal layers are connected to each other to form a desired single crystal region.

Therefore, a single crystal layer having a desired shape (for example, a quadrangle such as a rectangle) effective for designing and manufacturing a device is
It is definitely obtained. That is, if the planar layout of the seed portion is determined, the shape of the single crystal region is uniquely determined.

(2) The present invention according to claim 2 provides the invention according to claim 1, wherein the seed portion surrounding a predetermined region of the amorphous semiconductor layer has a linear shape arranged in a crystal direction equivalent to <100>. Are formed by connecting the seed regions of the.

The maximum L-SPE distance is obtained in the crystal orientation equivalent to <100>. Therefore, with the structure of the present invention, a single crystal layer having a sufficient size can be formed.

(3) The present invention according to claim 3 is characterized in that, in claim 2, a scribe region is used as a linear seed region.

The scribe region is a region for scribing the wafer into chips, but the insulating film on the scribe region is removed and the semiconductor substrate is exposed. Therefore, by using this region also as a common seed part (seed crystal part),
Effective use of the scribe area can be achieved.

(4) The present invention according to claim 4 uses the (100) equivalent plane as a seed portion (seed crystal portion) to single crystal the amorphous semiconductor layer by the SPE method, and forms a single crystal on the insulating film. A method of forming a layer, wherein the planar shape of the seed portion is a linear shape, and the length of the linear shaped seed portion is
The single crystal layer to be obtained is made longer than the length of the linear seed portion in the extending direction, and the amorphous seed crystal is grown from the linear seed portion by a solid phase epitaxial growth (SPE) method. The high quality semiconductor layer into a single crystal,
Thereafter, the unnecessary single crystal layer formed at the end of the linear seed portion is removed, whereby only the single crystal layer extending in the direction perpendicular to the extending direction of the linear seed portion is removed. The above-mentioned desired semiconductor single crystal layer is obtained.

When a linear seed is used, the pointed undesired single crystal region is formed at the end of the seed portion.

Therefore, by considering this portion in advance as a seed having a margin, and removing the undesired single crystal region generated at the end portion of the seed after SPE, the device design and Has a desired shape that is convenient for production (for example, a rectangle such as a rectangle),
In addition, a single crystal layer having a desired size (size) can be surely obtained.

(5) According to the present invention of claim 5, in claim 4, the length of a portion of the end portion of the linear seed portion which is extra longer than the length of the single crystal layer to be obtained is ". When the length of the single crystal layer to be obtained is "L2" in the direction perpendicular to the extending direction of the linear seed portion, "L1" is "L2" or more. It is characterized by

In other words, when a stripe-shaped seed is used, the length of the extra-long seed is "L1", and the length in the direction perpendicular to the seed of the single crystal region to be obtained is "L2". ≧ L2.

In this case, "L2" corresponds to the lateral width of the single crystal region to be obtained. In this case, at the end of the seed, the single crystal is formed at an angle of 45 degrees from the end of the lateral width. grow up.

Therefore, "L2" and "L1" correspond to the two sides sandwiching the apex angle (90 degrees) of an isosceles right triangle, and therefore the width "L2" of the single crystal region to be obtained is surely secured. In order to do so, the relationship L1 ≧ L2 needs to be established.

(6) According to the present invention of claim 6, in claim 4, a desired single crystal layer is obtained by an SPE method using first and second linear seed portions that intersect each other at right angles. It is characterized by

That is, in a region sandwiched by orthogonal linear seed portions, the single crystal layers grown from the first and second seeds as starting points are connected to each other to form a desired single crystal region. . Therefore, a sufficiently large single crystal region can be obtained.

(7) The present invention according to claim 7 is characterized in that, in any one of claims 4 to 6, a scribe region is used as the linear seed portion.

As in the third aspect, the scribe area is effectively used.

(8) A semiconductor device of the present invention according to claim 8 is:
A semiconductor element is formed on the semiconductor single crystal layer formed by the method according to any one of claims 1 to 7.

According to the method described in any one of claims 1 to 7, a shape (for example, a quadrangle such as a rectangle) in which a device can be easily manufactured is formed.
The SOI region can be obtained. Therefore, the device can be easily designed and manufactured, and an ultrahigh-integrated and high-speed semiconductor device can be realized.

Further, at the end of the seed portion, the single crystal island does not have a triangular shape, and the disadvantage of electric field concentration does not occur.

(9) The semiconductor device of the present invention according to claim 9 is:
In claim 8, the semiconductor element is an insulated gate field effect transistor.

As a result, a large-capacity, high-speed, high-reliability gate array or other ASIC or M utilizing the SOI structure is provided.
An OS memory or the like can be realized.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment (FIGS. 1, 2 and 3) In the first embodiment shown in FIG. 1, a (100) equivalent plane is used as a seed portion (seed crystal portion). Then, when the amorphous semiconductor layer is single-crystallized by the SPE method to form the single crystal layer on the insulating film, the plane pattern of the seed portion is set to a pattern surrounding a predetermined region of the amorphous semiconductor layer, and the seed portion is formed. A predetermined region of the amorphous semiconductor layer surrounded by is crystallized by solid phase epitaxial growth (SPE) to form the desired semiconductor single crystal layer.

A plane layout pattern of the main part is shown on the upper side of FIG. 1, and a sectional view taken along the line AA is shown on the lower side.

It should be noted that what is used as a semiconductor surface is (10
0) surface or a surface substantially equivalent thereto (in the present specification, these are collectively referred to as (100) equivalent surface), and the paper surface of FIG. 1 corresponds to the (100) equivalent surface.

The crystal directions are shown in FIG. This crystal orientation is similarly established not only in FIG. 1 but also in FIGS. 2, 5, 6, 7, 7, 8, 9, 10, 11 and 13.

As shown in FIG. 1, the surface of the silicon single crystal substrate 10 is covered with an oxide film 20, a part of which is patterned to form linear seed portions 30a, 30b, 30.
c and 30d are provided.

Surface oxide film 20 and seed portions 30a, 3
The amorphous semiconductor layers deposited on 0b, 30c, and 30d are single-crystallized by the element process technique developed by the present inventor shown in FIG.

That is, after the heat treatment at about 600 ° C. for a predetermined time, as shown in FIG.
Internal region 60 surrounded by 30b, 30c, 30d
The single crystal layers grown from the seed portions as the starting points are connected to each other (in the figure, the growth locus is shown by a dotted line for easy understanding), and the single crystal layers are completely crystallized.

Therefore, in the present embodiment, as a result, the single crystal region (desired single crystal region) 60 to be obtained is obtained.
The seed portion is formed so as to surround the periphery of. Thus, if the planar layout of the seed portion is determined, the shape of the single crystal region is uniquely determined. therefore,
A single crystal layer having a desired shape (for example, a quadrangle such as a rectangle) effective for designing and manufacturing a device can be reliably obtained.

A triangular single crystal layer (unnecessary single crystal layer) 50 is formed outside each seed, and a polycrystalline layer 40 is formed around the single crystal layer 50.

Next, as shown in FIG. 2, by removing an unnecessary layer by dry etching (RIE or the like),
A desired single crystal region (single crystal island) is formed.

The process up to this point is summarized in FIG.
It becomes like (a)-(c). That is, as shown in FIG. 3A, a part of the surface oxide film 20 is removed to form a seed portion, and then an amorphous semiconductor layer is deposited as shown in FIG. By processing by crystallization and dry etching, a single crystal island 60 having an SOI structure is formed (FIG. 3C).

Thereafter, as shown in FIG. 3D, diffusion layers 70a and 70b to be the source (S) or the drain (D) are formed on the single crystal island 60, and the gate oxide film 72 is formed on the surface thereof. After the formation, a gate electrode 74 is formed, a passivation film 80 is formed, and electrodes 76a and 76 are formed.
The MOS transistor is completed through the respective steps of forming b.

Using such a MOS transistor,
For example, an ASIC having an SOI structure as shown in FIG.
(IC whose application is specified) can be constructed.

(2) Second Embodiment (FIG. 5) In the second embodiment of the present invention shown in FIG. 5, a single crystal layer is formed by the SPE method using a straight (striped) seed portion 30. Is formed.

A plane layout pattern of the main part is shown on the upper side of FIG. 5, and a sectional view taken along the line BB is shown on the lower side.

The single crystal layer is formed on both sides of the seed portion 30 and the tip portion of the seed portion. As shown in FIG.
The dry etching process leaves the single crystal layers 62a and 62b formed on both sides of the seed portion 30 as desired single crystal layers (single crystal islands).
Unnecessary single crystal layers 67a, 67 generated at the tip of 0
b and the polycrystalline layer 40 around it are removed.

In the present embodiment, the required single crystal layer 62
The lateral widths of a and 62b are "L2", and in order to secure this "L2", the length of the seed portion 30 is made "L1" longer than the required position of the single crystal layers 62a and 62b. ing.

That is, at the end of the seed, 45 from the end of the required lateral width of the single crystal (the part corresponding to L2).
"L2" because single crystal growth stops at an angle of
And “L1” correspond to two sides sandwiching the apex angle (90 degrees) of an isosceles right triangle, and therefore L1 ≧ L2 is required to ensure the width “L2” of the single crystal region to be obtained. The relationship must be established.

Focusing on this, in the present embodiment, L
The length of the seed portion is determined so that 1 ≧ L2. This has the effect of reliably obtaining a single crystal layer of the desired size.

Also, the maximum L-SPE distance is obtained.
Since the seed portion is provided in the crystal direction equivalent to 100>, a sufficiently large single crystal region can be obtained.

(3) Third Embodiment (FIG. 7) In the present embodiment shown in FIG. 7, two linear seed portions 32, which intersect at a predetermined angle (for example, vertical),
In the region sandwiched by 34, the single crystal layers grown from the seed as a starting point are connected to each other to form a single crystal region. Therefore, a sufficiently large single crystal region can be easily obtained.

After the single crystal is formed, it is processed by dry etching to obtain the single crystal island 64.

(4) Fourth Embodiment (FIG. 8) In the present embodiment shown in FIG. 8, when arranging the seed portion in the same form as FIG. 7, a scribe region is provided as at least a part of the seed portion. 80 is used. The single crystal layers starting from the respective seeds are connected to obtain one single crystal layer, which is then processed by dry etching to obtain a desired single crystal island 66.

According to this embodiment, the scribe area can be effectively used.

(5) Fifth Embodiment (FIG. 9) In the present embodiment shown in FIG. 9, when arranging the seed portion in the same form as in FIG. 1, a scribe region is provided as at least a part of the seed portion. 80 is used. An inner region surrounded by the seed portion becomes a desired single crystal region (single crystal island) 80.

According to this embodiment, the scribe area can be effectively used.

(6) Sixth Embodiment (FIG. 10) FIG. 10 shows a single crystal obtained by the above method.
It is a figure which shows the schematic structure of an example (gate array) of the semiconductor device of SOI structure.

A large number of basic cells 210 of a gate array are arranged on the IC chip 200. Basic cell 210
Are configured to include MOS transistors M1 to M4.

FIG. 11 shows the IC chip 200 of FIG.
It is a figure which shows a more concrete structural example.

The IC chip 200 is formed by being integrated on the wafer 300, and each chip 200 is formed by being surrounded by scribe regions 80a, 80b, 80c and 80d on all sides.

In the example of FIG. 11, the linear (striped) seed portion 30 is formed between the scribe regions 80a and 80c, and the scribe regions 80a and 80b are also utilized as seed portions to obtain a single crystal layer. There is. Each of the MOS transistors M1 to M1 forming the basic cell of the gate array
M4 is the single crystal regions 401 to 4 of the SOI structure, respectively.
02. Since each single crystal region has a sufficient size and has a shape that is advantageous for designing and manufacturing an element, it is easy to manufacture an IC.

As described above, according to the present invention, an ultra-high integration and high speed semiconductor device using the SOI structure can be realized.

[0073]

[Brief description of drawings]

FIG. 1 is a diagram for explaining a step of obtaining a single crystal layer by SPE in the first embodiment of the method for forming a single crystal layer of the present invention (an example in which seeds are arranged around).

FIG. 2 is a diagram for explaining a step of processing the single crystal layer formed by the method of FIG. 1 by dry etching to obtain a desired single crystal layer (single crystal island).

3A to 3D are process diagrams showing a process of forming a semiconductor element (MOS transistor) on the semiconductor single crystal layer obtained by the process of FIG.

FIG. 4 is a diagram showing a crystal direction in a (100) equivalent plane used in the present invention (this crystal direction is shown in FIGS.
5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG.
Conforms to 3).

FIG. 5 is a diagram for explaining a step of obtaining a single crystal layer by SPE in the second embodiment of the method for forming a single crystal layer of the present invention (an example using a linear seed).

6 is a diagram for explaining a step of processing the single crystal layer formed by the method of FIG. 5 by dry etching to obtain a desired single crystal layer (single crystal island).

FIG. 7 is a drawing for explaining the third embodiment of the method for forming a single crystal layer of the present invention (an example using orthogonal linear seeds).

FIG. 8 is a drawing for explaining the fourth embodiment of the method for forming a single crystal layer of the present invention (an example in which a scribe region is used as at least one of orthogonal linear seeds).

FIG. 9 shows a fifth embodiment of a method for forming a single crystal layer of the present invention (an example in which a scribe region is used as at least one of linear seeds arranged so as to surround a certain region). It is a figure for explaining.

FIG. 10 is a diagram showing the contents and arrangement of basic cells of an example (gate array) of a semiconductor device to which the present invention is applied.

11 is a diagram showing a configuration example of a basic cell of FIG.

12A to 12F are cross-sectional views of a device for explaining main steps of an element process for forming an SOI structure, which has been previously proposed by the present inventor.

FIG. 13 is a diagram for explaining a problem in forming an SOI structure using the SPE method, which is made clear by the present inventor.

[Explanation of symbols]

10 Silicon Single Crystal Substrate 20 Surface Oxide Film 30a, 30b Seed Part (Seed Crystal Part) 40 Polycrystalline Region 50 Unnecessary Single Crystal Region 60 Desired Single Crystal Region (Single Crystal Island) 70a, 70b Diffusion to Become Source or Drain Region Layer 72 Gate oxide film 74 Gate electrodes 76a, 76b Electrode 80 Passivation film

Claims (9)

[Claims] 1. An opening is provided in a part of an insulating layer provided on a (100) equivalent surface of a semiconductor single crystal substrate to provide the above (10).
(0) A part of the equivalent surface is exposed, and an amorphous semiconductor layer is formed so as to cover the insulating layer and the exposed part of the (100) equivalent surface. 100) The exposed portion of the equivalent surface is used as a seed portion (seed crystal portion), and solid phase epitaxial growth (Solid Phase Epi) is started from this seed portion.
taxy; SPE) to form a desired semiconductor single crystal layer on the insulating layer, wherein the planar pattern of the seed portion is a pattern surrounding a predetermined region of the amorphous semiconductor layer, A predetermined region of the amorphous semiconductor layer surrounded by the seed portion is single-crystallized by a solid phase epitaxial growth (SPE) method to form the desired semiconductor single-crystal layer. Forming method. 2. The seed portion surrounding a predetermined region of the amorphous semiconductor layer according to claim 1, is formed by connecting linear seed regions arranged in a crystal direction equivalent to <100>. And a method for forming a semiconductor single crystal layer. 3. The method for forming a semiconductor single crystal layer according to claim 2, wherein a scribe region is used as the linear seed region. 4. An opening is provided in a part of an insulating layer provided on a (100) equivalent surface of a semiconductor single crystal substrate to provide the above-mentioned (10).
(0) A part of the equivalent surface is exposed, and an amorphous semiconductor layer is formed so as to cover the insulating layer and the exposed part of the (100) equivalent surface. 100) The exposed portion of the equivalent surface is used as a seed portion (seed crystal portion), and solid phase epitaxial growth (Solid Phase Epi) is started from this seed portion.
taxy; SPE) to form a desired semiconductor single crystal layer on the insulating layer, wherein the planar shape of the seed portion is a linear shape, and the length of the linear shaped seed portion is , Of the single crystal layer to be obtained,
The linear seed portion is made longer than the length in the extending direction, and the amorphous semiconductor layer is single-crystallized from the linear seed portion by a solid phase epitaxial growth (SPE) method. , The unnecessary single crystal layer formed at the end portion of the linear seed portion is removed, whereby only the single crystal layer extending in the direction perpendicular to the extending direction of the linear seed portion is removed. A method for forming a semiconductor single crystal layer, wherein the desired semiconductor single crystal layer is obtained. 5. The length of a portion of the end portion of the linear seed portion, which is extra longer than the length of the single crystal layer to be obtained, is set to “L1”, and the end portion of the linear seed portion is also to be obtained. When the length of the single crystal layer to be formed is “L2” in the direction perpendicular to the extending direction of the linear seed portion, “L2”
1 "is" L2 "or more, and a method for forming a semiconductor single crystal layer. 6. The S according to claim 4, wherein the first and second linear seed portions that intersect each other at right angles are used.
A method for forming a semiconductor single crystal layer, which comprises obtaining a desired single crystal layer by a PE method. 7. The method for forming a semiconductor single crystal layer according to claim 4, wherein a scribe region is used as the linear seed portion. 8. A semiconductor device in which a semiconductor element is formed on a semiconductor single crystal layer formed by the method according to any one of claims 1 to 7. 9. The semiconductor device according to claim 8, wherein the semiconductor element is an insulated gate field effect transistor.