JPH0548095A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To prevent effect by quantity of defects on mobility of carrier by causing free carrier of a semiconductor device to run along the crystal growth direction, except for the area near the growth originating point. CONSTITUTION:A p-type channel region 2 of nM0S transistor and n<+> type regions which will become a source and a drain are provided on a quartz glass substrate 1. Moreover, an insulating film 4, a gate electrode 5, a nitride region 20 which will become a seed, a metal 100 which will be become an electrode and an interlayer insulating film 200 are also formed. After Si is grown on a circular box by the gas phase epitaxy method, it is selectively polished to produce a substrate, a circular gate electrode 5 is formed to prepare a OS transistor. With introduction of such structure, defect of gas phase epitaxy enters radially, the carrier runs in the crystal growth direction and also runs along the defects, without crossing the radial defects.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed on an insulating film and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in some semiconductor devices, a method for forming a high quality single crystal on an insulating substrate has been required in order to improve the characteristics.

As one of the methods for forming such a good quality single crystal, a non-nucleation surface having a small nucleation density and an area sufficiently smaller than a single nucleus for crystal growth are formed on an insulating substrate to form a nucleation. A technique for growing a single crystal from a single nucleus arranged on the nucleation surface by subjecting a deposition surface having a high-density nucleation surface to a crystal formation treatment such as vapor phase epitaxy (hereinafter referred to as centaxy) is known. is there.

FIG. 8 is a diagram showing a conventional crystal forming method by such a centering technique. In the figure, a single nucleus (seed) which is a starting point of crystal growth is formed at the center of a box (nucleation surface) on one side L. And a crystal is grown in the box centering on the seed by vapor-phase centaxy.

FIG. 6 (a) is a plan view showing the crystal thus grown.

Further, FIG. 9 shows an MO formed by processing such a crystal and formed by the conventional centering technique.
It is the top view (a) and sectional drawing (b) of an S transistor.

[0007]

Conventionally, as shown in the conventional example of FIG. 8, a device by the vapor deposition of centaxy is prepared by growing a nucleus from a central nucleation starting point (seed) in a square box of one side L. I was making it. for that reason,
As shown in FIG. 6A, in order to grow the crystal at least up to the corner of the square box, it was necessary to grow up to the diameter of √2L.

Further, since this crystal grows in a polygonal shape in a random direction, the seeds cannot be arranged at intervals of L in order to prevent the crystals from colliding with each other, and at least √2L must be set. However, there is a problem that the formation density cannot be increased.

(This must be avoided when the crystals are formed on quartz, because if the crystals hit each other, cracks will form on the quartz glass side due to the difference in expansion coefficient between Si and SiO _2. ) In the solid-phase centaxy, since the growth is essentially radial, the defects are radially centered around the seed. However, as shown in FIG. 9, since the gate is conventionally formed on the seed, the defect is Carriers travel across the carrier, and depending on the number of defects, the carrier mobility of the MOS transistor is greatly affected, resulting in a large variation in the response characteristics of the MOS transistor.

Further, since the circuit is rate-controlled by the one having the smallest mobility, it has become a very serious problem.

[0011]

As a means for solving the above-mentioned problems, the present invention has a semiconductor device having a crystal growth starting point on an insulating base and being formed on a semiconductor base which is selectively crystal-grown. In the semiconductor device, the free carrier of the semiconductor device travels along the crystal growth direction except in the vicinity of the growth starting point.

The semiconductor device is an insulated gate transistor having at least a source, a drain, a gate, and a channel portion, and the gate region is arranged so as to surround the growth starting point.

Further, it is characterized by having a plurality of the gate regions.

Further, the semiconductor device is a transistor having an emitter, a base and a collector, and the base is arranged so as to surround the growth starting point.

Further, the plane shape of the carrier traveling area is 5
It is characterized by being polygonal or circular more than rectangular.

Further, the present invention is intended to solve the above-mentioned problems by a method of manufacturing a semiconductor device, which has a crystal growth starting point in a circular or pentagonal or more concave portion on an insulating substrate, and performs crystal growth from the growth starting point. To do.

[0017]

According to the present invention, by making the box in which nuclei grow at least pentagonal or more or circular, it is possible to prevent the grown crystals from hitting each other and to increase the formation density.

Further, a gate region is provided almost perpendicularly to the defect, the device is constructed so as not to cross the defect, and the vicinity of the seed where defects are concentrated is not used as a carrier traveling region. By doing so, it is possible to prevent the mobility of carriers from being affected by the number of defects.

Further, by providing a plurality of transistors in the same box and designing the shape of the box, the formation density of semiconductor elements can be further increased.

[0020]

EXAMPLE 1 FIG. 1 is a diagram showing an example of the present invention. FIG. 1A is a plan view particularly showing a semiconductor element region, and FIG. 1B is a plan view including electrodes and the like. (A) in the case of
It is a -A 'sectional view.

In FIG. 1, 1 is a quartz glass substrate, 2 is a P-type channel region of an nMOS transistor, and 3 is an n ⁺ region which serves as a source and a drain.

Further, 4 is a gate insulating film, 5 is a gate electrode,
Reference numeral 20 is a nitride film region serving as a seed, 100 is a metal serving as an electrode, and 200 is an interlayer insulating film.

As will be described later, the semiconductor device of this embodiment has a circular box with an S
After i was crystal-grown, selective polishing was performed to form a substrate, and then a circular gate electrode 5 was formed to form a MOS transistor.

Since the defects of vapor-phase centaxy enter radially from the seeds, in the structure of this embodiment, the carriers travel in the crystal growth direction and do not cross the radial defects but along the defects. Become.

FIG. 2 is a histogram showing carrier mobilities of the MOS transistors in the conventional example (FIG. (A)) and the present invention (FIG. (B)).

In the conventional example shown in (a), many of them cross defects, so that the mobility has a peak at 50 cm ² / v · sec, but in the present invention shown in (b),
It has a peak at 00 cm ² / v · sec, and the mobility is improved to almost double. That is, according to the present invention, since the carrier is allowed to travel along the defect, the effect that the mobility is improved is obtained.

Next, an example of the manufacturing process of the first embodiment will be described with reference to the sectional process drawing of FIG.

(1) After the quartz glass 1 is etched into a concave circular box shape, S is used as a seed 20 at the center of the concave portion.
i ₃ N ₄ is deposited by LPCVD and is formed by patterning. After that, SiH ₂ Cl ₂ + HCl, SiCl
Si as seed 20 by using gas such as ₄ + HCl
Crystal growth is performed centering on ₃ N ₄ (FIG. 3A).

(2) Only Si is selectively polished using the quartz glass 1 as a stopper. After that, add B ⁺ to 1 × 10 ¹¹ ~
Ions are implanted at about 1 × 10 ¹³ cm ² and heat-treated to form a P region (FIG. 3B).

(3) After forming the gate oxide film 4 by the direct oxidation method, polysilicon to be a gate electrode is deposited. 1 × 10 ¹⁵ to 1 × 1 of P, As, etc. by ion implantation
After doping about 0 ¹⁶ cm ^-2 and performing heat treatment, patterning is performed (FIG. 3).
(C)).

(4) A using the gate electrode 5 as a mask
n-type impurities such as s and P from the top are 1 × 10 ¹⁵ to 1 × 10
^By ion implantation and heat treatment at about ¹⁶ cm ^-2 ,
Source. An n ⁺ region to be the drain region 3 is formed (FIG. 3D).

(5) After depositing silicon oxide to be the interlayer insulating film 200, the contact hole can be patterned.

A metal such as Al or Al-Si to be the electrode 100 is deposited by a method such as sputtering, and electrodes and wiring are formed by patterning (FIG. 3 (e)).

(Embodiment 2) FIG. 4 shows another embodiment. In FIG. 4, (a) is a plan view particularly showing a semiconductor element region, and (b) is a sectional view taken along the line AA ′ of (a) with electrodes and the like added.

In this embodiment, two MOS transistors are formed in one circular box. The difference from the embodiment of FIG. 1 is that the first transistor is
Drain), region 5 (gate), region 3 '(source or
Drain), a second transistor is formed in a region 3 ′ (source or drain), a region 5 ′ (gate), a region 3 ″ (source or drain), and the element isolation region 10 is formed of two transistors. That is, the active region is separated.

With such a structure, the gate width of the two transistors can be determined by the length of the circumference, and the ratio of the gate widths can be arbitrarily determined. When this is applied as an inverter, for example, it can be designed very conveniently as the minimum unit.

FIG. 5 is an equivalent circuit of FIG. 4, showing an inverter.

In the figure, Vout is common and corresponds to the region 3'in FIG. According to this embodiment, one set of inverters can be easily created in one circular box in this way.

In the above-mentioned embodiments, the box, the gate electrode and the like are manufactured in a circular shape, but it is clear that the same effect can be obtained if the polygon has a pentagonal shape or more. It is natural that

FIG. 6 is a plan view showing the integration densities of the semiconductor devices of the present embodiment and the conventional example. FIG. 6A is a conventional example,
(B) The figure shows an example of the present invention. 4 in the conventional example (a)
Since the rectangular box and the crystal do not coincide with each other, if one side of the box is L, a minimum spacing of √2 L is required to prevent the crystal from colliding. On the other hand, in the present invention, since the circular box and the crystal coincide with each other, in the box having the diameter L, it is possible to approach the minimum L. Therefore, considering the area, the integration degree can be increased by √2L × √2L / L × Lsin 60 ° ≈2.3 times compared with the conventional example.

(Embodiment 3) FIG. 7 is a diagram showing another embodiment of the present invention. (A) is a plan view mainly showing the element region, and (b) is a sectional view in which electrodes and the like are added.
Although the structure of this embodiment is very similar to that of FIG. 1, there is no gate in this embodiment, and the electrode 100 is formed in the P region to form a bipolar transistor.

Also in this example, the carriers travel in the crystal forming direction and do not cross the crystal defects. Therefore, it is apparent that the operation and effect of the present invention can be obtained as in the above-described embodiment.

As described above, the present invention can be easily applied to other devices, for example, in a junction type FET, similarly, by configuring each semiconductor element region such that the carrier traveling direction is the crystal formation direction. Applicable.

That is, by allowing carriers to travel along the defects without traversing the defects, the advantages of the centery crystal can be further utilized.

[0045]

As described above, according to the present invention, a structure in which the carrier travels along a defect without traversing the defect concentration portion or radial defect portion in the vicinity of the generation nucleus is provided. As a result, the mobility of carriers is increased, and the variation in mobility due to the number of defects is reduced, so that a semiconductor device having stable characteristics can be obtained.

Further, since the box shape can be formed as a pentagonal or more polygonal shape or a circular shape, the integration density can be increased.

Further, by forming a plurality of transistors in one box, the semiconductor region in the box can be effectively used. For example, an inverter can be formed in one box. It can be adapted.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a comparison of carrier mobilities between a semiconductor device of Example 1 of the present invention and a conventional device.

FIG. 3 is a diagram showing an example of a manufacturing process of Example 1.

FIG. 4 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an equivalent circuit of an inverter according to a second embodiment.

FIG. 6 is a diagram comparing the degree of integration between the semiconductor device of the present invention and a conventional example.

FIG. 7 is a diagram showing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a plan view showing a square box and a seed of a conventional example.

FIG. 9 is a diagram showing a conventional semiconductor device and its defects.

[Explanation of symbols]

 1 quartz glass substrate 2 channel region 3 source or drain region 4 gate insulating film 5 gate electrode 20 seed 100 electrode 200 interlayer insulating film

Claims (7)

[Claims] 1. A semiconductor device having a crystal growth starting point on an insulating base, and a semiconductor device manufactured on a selectively crystal-grown semiconductor base, wherein free carriers of the semiconductor device are excluded except in the vicinity of the growth starting point, and A semiconductor device characterized in that it is made to travel along the crystal growth direction. 2. The semiconductor device comprises at least a source,
The semiconductor device according to claim 1, wherein the semiconductor device is an insulated gate transistor having a drain, a gate, and a channel portion, and the gate region is arranged so as to surround the growth starting point. 3. The semiconductor device comprises an emitter, a base,
The semiconductor device according to claim 1, wherein the semiconductor device is a transistor having a collector, and the base is arranged so as to surround the growth starting point. 4. The semiconductor device according to claim 1, wherein a plane shape of the carrier traveling region is a polygon having a pentagon or more or a circle. 5. The semiconductor device according to claim 1, wherein a plurality of semiconductor devices are formed in a crystal grown from one growth starting point. 6. The method of manufacturing a semiconductor device according to claim 1, wherein a circular recess on the insulating substrate has a crystal growth starting point, and the crystal is grown from the growth starting point. .. 7. The method of manufacturing a semiconductor device according to claim 1, wherein a polygonal recess having a pentagonal shape or more on the insulating base has a crystal growth starting point, and the crystal is grown from the growth starting point. Method of manufacturing semiconductor device.