JPH01120048A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a high-performance bipolar CMOS transistor or the like by a method wherein amorphous Si is heat-treated at less than a prescribed temperature to form a single crystal so that an SOI structure and a device such as a bipolar transistor by a low-temperature epitaxial growth operation can be formed by one epitaxial growth operation. CONSTITUTION:An insulating film 2 is formed on a substratum Si layer 1; an epitaxial growth operation is executed by making use of openings made in the insulating film 2 as seeds 13, 14; singlecrystal Si parts 16, 15 are formed on the seed 14 or the insulating film 2; semiconductor devices are formed in the single-crystal Si parts 15, 16. When a semiconductor circuit device is formed in this manner, a solid epitaxial growth operation to transform amorphous Si into a single crystal by heat-treating it at 800 deg.C or less is used; a bipolar transistor 12 is formed on the seed 14 and in its neighborhood, and a MOS transistor 11 is formed on the insulating film 2. For example, the surface of a seed is cleaned; amorphous Si is deposited; after that, an SPE growth opera tion is executed by heat-treating it at 600 deg.C in an atmosphere of nitrogen for four hours; in succession, the remaining amorphous Si is removed; a single- crystal layer is formed to be an island shape.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly applies solid phase epitaxial growth technology. The present invention relates to a manufacturing method suitable for forming a bipo50MO5 structure.

[Conventional technology]

In the LSI process, the epitaxial growth of Si is
It has been widely used as a technique for forming a low concentration impurity layer on a high concentration n medium layer of a bipolar transistor.

In recent years, with the aim of increasing the speed of bipolar transistors,
In order to make the emitter, base, and collector layers shallower, the substrate temperature during epitaxial growth was lowered to 1,000 yen.
Many attempts have been made to lower the temperature from .degree. C. or higher to about 800 layers.

On the other hand, as a new application of epitaxial growth, crystal growth is performed laterally on the insulating film from seeds in the openings of the insulating film.
or) Many attempts to create structures have also been reported. SOI
The structure is particularly effective in reducing source-drain parasitic capacitance of MOS transistors, improving resistance to alpha rays, and preventing latch-up phenomena in CMOS transistor structures. Figure 2 shows
In this example, polycrystalline Si is melted by heating with a strip heater and recrystallized to form a SO layer to form a CMO transistor. (19
1984, Inc.-National Electron Device Meeting Proceedings, P, 812 B-Y, Tsa
ur et al. 5) Furthermore, in this example, on the same chip, another Si
A so-called bipolar CMO8 structure is formed by selectively epitaxially growing Si in the opening using a vapor phase chemical growth method to create a bipolar transistor.
Attempts to realize low power consumption, high integration, and high speed of LSI are described.

[Problem that the invention seeks to solve]

However, depending on the above-mentioned conventional technology, in order to form a 5OIftW MOS transistor and a bipolar transistor on the same chip, it is necessary to make full use of two different epitaxial growth methods, which complicates the manufacturing process. There was a problem.

Therefore, an object of the present invention is to realize the formation of an SOI structure and the formation of elements such as bipolar transistors by low-temperature epitaxial growth using a single epitaxial growth method, and to realize the formation of high-performance bipolar transistors, bipolar CMOs, etc.
An object of the present invention is to provide a manufacturing method for forming a semiconductor element such as an S transistor.

[Means for solving problems]

The above purpose is to use amorphous Si as an epitaxial growth method.
This is achieved by using a solid-phase epitaxial growth method called single crystallization.

Furthermore, when forming a device such as a bipolar transistor on an epitaxially grown seed, the patterning direction for drilling holes in the insulating film for forming the seed is set to (100}S
It is effective to select the <110> direction ±20' for the i-substrate, which is different from the orientation conventionally considered to be advantageous for forming an SOI structure.

Therefore, when forming a bipolar CMO3 structure, the above patterning direction is (10
0>±20°, <11 for bipolar transistors
0>±20".

[Effect]

Solid phase epitaxial growth of Si
In the eEpitaxy (SPE) method, as shown in Figure 3, amorphous Si4 is deposited on a sample with a clean Si surface, which will serve as a seed 3 for crystal growth, and then heat treated at a temperature of about 600 layers. This is a method of making a single crystal. Single crystallization is performed in the vertical direction (V (Vertical) -8
PE) as well as the lateral direction (L(Lateral) -S
S OI (Silicon
A layer 5 (on-on In5ulator) can be formed.

Furthermore, since it is a low-temperature process of about 600"C, low-concentration epitaxial Si5 can be formed even if Si containing a high concentration of impurities is used as a seed. In other words, unlike laser annealing methods that use surface melting of the Si film, Impurities do not rise, and it can be applied to bipolar devices.In this way, the SPE method, which is the only crystal growth method, can be used to grow the 801 layer (L-8PE) and shrimp growth (for bipolar devices, etc.). V-8PE) can be performed simultaneously.

According to our research, the L-3PE layer currently contains many crystal defects. Although this is not fatal to MOS transistor formation, this defect is.

It has become clear that there is a possibility that the particles may protrude into the V-8PE layer and deteriorate the characteristics of elements formed there. Fourth
Figure (a) shows this situation.

It is a schematic diagram of a planar photograph taken by a Nomarski interference microscope. In addition, after SPE, Wright
tching processing is performed. It can be seen that etch bits 43 based on crystal defects are distributed in the V-8PE layer 42 on the first seed layer on the four SOI layers.

Further, from experiments in which the Si film thickness was varied, it was found that the penetration distance 44 of this defect was approximately proportional to the film thickness, and approximately 1.5 times the film thickness. With the miniaturization of elements, the seed width is 45 mm.
As the number of defects decreases, the entire surface of the v-8PE layer will be covered with these defects. This uses a (100}Si substrate, which is advantageous for L-8PH, as has been reported many times in the past.

Patterning of insulating film for seed formation (100>
This is the case when the direction is set.

This time, we have newly found that when the patterning direction is set to be in the <110> direction ±20'', the penetration of the defect is significantly reduced.

FIG. 4(b) schematically shows this.

Another type of defect tjA is detected at both ends of the V-8PE layer, but this is due to the (111) facet 51 as shown in FIG.
This is a microtwin 46 based on the formation. This twin penetration distance l547 is as small as eog54.7@40.58 times that of film 4, and the existence of this twin prevents the penetration of defects such as dislocations from L-5PEJI. It is assumed that

Due to the above circumstances, the patterning direction of the insulating film is L-
For example, it is necessary to optimize separately depending on whether 8PEpa or V-5PE layer is used for device formation.
When forming a so-called bipolar 50MO8 structure having a CMOS transistor and a bipolar transistor on the same chip, the seed for forming the SOI layer for 0MO8 is made by patterning in the <100> direction ±20°, and the seed for the bipolar transistor is <110> direction ±2
It is effective to create the pattern using 0° patterning.

Note that even if the Si substrate is tilted by ±10'' from (100), the same effect can be obtained by setting the patterning direction to an equivalent direction tilted by the same angle.

〔Example〕

[Example 1] First, an example in which an S○ICMO8 and a bipolar transistor are formed on the same substrate using the SPE method will be described. FIG. 1(a) shows its cross-sectional structure.

The basic structure of the device is the same as the known example shown in FIG. 2, but SPE is suitable for L-8PE and V-8PE.
The difference is that it forms a seed region for. That is, as shown in the plan view in FIG. 1(b), the SOI
The seed 13 for formation is formed by patterning a 5iOz film in the <100> direction, and the seed 14 for bipolar is formed by patterning a 5iOz film in the <100> direction.
It is patterned in the <110> direction.

The seed surface was cleaned in an ultra-high vacuum, and the amorphous Si was reduced to 0.
After 4 pm was deposited, SPE growth was performed by heat treatment at 600° C. for 4 hours in a nitrogen atmosphere.

Next, the remaining amorphous [Si was removed, the single crystal layer was processed into an island shape, and the surface was oxidized to form 5PES.
The OI layer 15 and the SPE epitaxial Si layer 16 were separated. After that, the collector of the bipolar transistor
Ion implantation for base.

The device was formed according to a normal formation process such as gate formation of a MOS transistor, source/drain ion implantation, and electrode formation.

By using the SPE method, not only can SOI and bipolar single crystal layers be formed in a single process, but also the bipolar epitaxial Si film thickness can be reduced from the conventional 1 μm or more to 0.5 μm.
It was possible to reduce the thickness to 5 μm or less, and achieve high-speed bipolar transistors.

In this example, the collector, base, and emitter were formed after performing SPE, but if these impurities were ion-implanted at the amorphous Si stage, the activation temperature of the impurities could be lowered from the conventional 900°C. It becomes possible to lower the temperature to about 600° C., and it is possible to realize an even shallower impurity distribution. At the same time, in order to lower the formation temperature of the lMo5 transistor, the gate oxide film must be formed by high-pressure oxidation or plasma oxidation, and after the gate is formed, the source and drain regions must be made amorphous again by Si ion implantation. , by implanting impurity ions and setting the activation temperature to about 600°C.

That is, according to the present invention, it is possible to substantially reduce the temperature of the method for forming bipolar CMO3 to 800° C. or lower.

[Example 2] Next, an example in which a bipolar transistor with reduced parasitic capacitance is formed will be described. FIG. 6 is a cross-sectional structural diagram thereof, and the process steps will be described below according to FIG. 7.

(100) LOCO3M on p-type Si substrate 1.

After forming an n buried layer 6 using As ion implantation, the SiOx film 2 is patterned in the (110> direction to form a seed, and amorphous Si is deposited, P for the collector, and B for the base. After ion implantation, an SPE epitaxial Si layer 16 was formed by heat treatment in a nitrogen atmosphere at 600° C. This layer had a trapezoidal shape with (111) facets on the side walls.

(a) Next, the remaining amorphous Si layer 32 is removed, the surface is oxidized, and then Ar sputter etching is performed.

An opening for drawing out the base electrode was provided on the side surface of the Si layer.

(b) Subsequently, polycrystalline 5i62 is deposited on the entire surface by a highly anisotropic vapor deposition method, and after doping with B, the polycrystalline Si on the side and top surfaces of the single crystal layer is removed by the same sputter etching and lift-off method. Removed. (c) Next, after surface reoxidation, a CVD5iOz film 64 was deposited on the entire surface.

(d) Subsequently.

A photoresist was applied to the entire surface and the surface was planarized by an etch-back method, and the upper surface of the single crystal layer was exposed, and emitter diffusion was performed using As-doped n-polycrystalline 5i65. Finally, drilling the contact hole for the collector base, A1
@pole formation was performed to form a bipolar transistor having the structure shown in FIG.

In this structure, the impurity distribution becomes shallower due to lowering the temperature, and the parasitic base region is eliminated, making it possible to achieve a significant increase in speed.

Note that it is also possible to realize a bipolar CMOS structure as shown in the first embodiment using a single bipolar transistor.

〔Effect of the invention〕

According to the present invention, by using only one low-temperature crystal growth method called solid-phase epitaxial growth, a high-performance bipolar transistor with a shallow emitter, base, and collector can be produced on the same chip. can be formed into

[Brief explanation of the drawing]

FIG. 1 is a sectional view and a plan view showing an embodiment of the present invention,
FIG. 2 is a sectional view showing an example of a conventional element, and FIG. 3 is a sectional view showing an example of a conventional element.
A cross-sectional view for explaining the principle of SPE, Figure 4, is 5i
A plan view showing the patterning effect of the Oz film, Figure 5, is (
111) A cross-sectional view showing facet formation. FIGS. 6 and 7 are views showing a cross-sectional structure and a process step cross-sectional view of an embodiment of the present invention. 11...CMOS transistor, 12...Bipolar transistor, 13...(100>Patterning seed, 14...(110>Patterning seed, 15
-8 P E SOI layer, 16 ・S P E : r
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Claims (1)

[Claims] 1. An insulating film is formed on the base Si layer, and single crystal Si is formed on the seed or the insulating film by epitaxial growth using the opening provided in the insulating film as a seed. S
A method for forming a semiconductor device in which a semiconductor element is formed in a semiconductor device uses a solid-phase epitaxial growth method in which amorphous Si is single-crystalized by heat treatment at 800° C. M on the membrane
A method for manufacturing a semiconductor device, the method comprising forming an OS transistor. 2. Form an insulating film on the base Si layer, form single crystal Si on or near the seed by epitaxial growth using the opening provided in the insulating film as a seed, and place a semiconductor element in the single crystal Si. In the method for forming a semiconductor device, the underlying Si layer is a {100} Si layer, and the patterning direction of the insulating film for the opening is selected in the <110> direction ±20°, and the semiconductor device is formed by solid phase epitaxial growth. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the single crystal Si is formed. 3. A bipolar transistor is formed in the single crystal Si on the insulating film opening patterned in the <110> direction ±20°, and the bipolar transistor is formed in the <110> direction within the same chip.
＞A MOS transistor is formed in monocrystalline Si formed by lateral solid-phase epitaxial growth on an insulating film through openings patterned in a direction of ±20°. 2. The method for manufacturing a semiconductor device according to item 2.