JPH0346277A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a super-thin film SOI structure so as to make an element structure adapted for integration by a method wherein a semiconductor layer is composed of a first crystalline support of a certain thickness and a second crystalline semiconductor layer whose thickness is smaller than that of the first crystalline support. CONSTITUTION:A semiconductor layer is composed of a first crystalline support 40 of a certain thickness selectively formed on an insulator substrate 1 or an insulating layer and a second crystalline semiconductor layer 50 whose thickness is smaller than that of the first crystalline support. When a superthin film SOI (semiconductor-on-insulator) 50 is made to grow in solid phase, seeds are formed on the base substrate 1 protruding from it, and the deposition film 50 is formed so as to, at least, make a part of it come into contact with the seeds, whereby the SOI excellent in crystallinity can be formed. The protrudent seeds can be used as contacts of the source.drain of a FET by making it high in impurity concentration through doping. By this setup, a superthin film SOI structure excellent in element characteristic can be uniformly formed throughout the whole face of a water through a method most excellent in control of thickness.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of a semiconductor element suitable for forming a high-density semiconductor integrated circuit and a method of manufacturing the same.

[Conventional technology]

So-called SO in which a semiconductor layer is formed on an insulating substrate
I (S semiconductor-on-I n5
The ulator structure has the advantage that element isolation is more complete, there is less interference from parasitic elements, and elements with excellent high speed and stability can be formed. In recent years, it has been pointed out that ideal three-terminal device characteristics can be obtained by creating an ultra-thin SOI structure with a thickness of 0.1 μm or less and creating a depleted MOSFET channel. Prototype examples have also been reported. For example, IEE, International Electron Devices Meeting 88, Technical Digest,
Pages 294-297 (I E DM88. Techni
cal Digest pp, 294-297), 0.35 μm S i OJ! The n-channel MO8FET, which is made of 85 mm thick SOI formed on top of the
ecade's 5ub-threshold 5lope and 115m5
/m transconductance (Laff=0.75μm)
Performances such as these have been reported. Conventionally, super aW like this
To form AS○■, oxygen was ion-implanted to form a buried insulating film, and the Si remaining on one surface was further thinned and used. This process will be explained using FIG. FIG. 2(a) is a cross-sectional view showing the step of implanting oxygen ions 2 into the Si substrate 1. 150-200 oxygen ions
About 2 x 10" am implanted at keV, at least near the center of the distribution to be higher than the stoichiometric Sin, oxygen concentration Dc, 1200-1350
Heat treatment at ℃ for several hours to several minutes. Then, the region into which oxygen has been implanted is converted into a SiO□ layer 3, and a single crystal region 4 remains on the surface. This remaining single crystal region 4 is a so-called SOI, and its thickness is usually about 0.2 μm. By oxidizing the surface of this 6 and then removing the oxide film, 5
Thin the layer to 0 to 1100n. SO thinned like this
An example of forming a MOSFET in I is shown in Fig. 2(b).
In the device formed through the above steps, the source/drain portions are also thinned, as is the channel portion.

Therefore, the parasitic resistance of the source and drain generally increases, which becomes a factor that limits high-speed operation of the device.

Additionally, SO formed by oxygen ion implantation is generally used.
I has many crystal defects and problems associated with high temperature heat treatment, namely high dissolved oxygen concentration and large wafer warpage.

It has the inherent disadvantage that it is not suitable for complex structures such as multi-layered structures.

Another method for forming ultra-thin film SOI is a melt recrystallization method using an energy beam such as a laser or an electron beam. Even with this method, it is not possible to form an ultra-thin SOI film from the beginning because it tends to agglomerate as it becomes thinner.
After forming an SOI of m, the layer is thinned by oxidation, etching, etc.

In general, crystallization methods that involve melting tend to result in non-uniform film thickness;
Efforts have been made to prevent agglomeration, such as covering with a cap film, but since the surface morphology during deposition of polycrystalline Si is preserved, it is difficult to form a uniform ultra-thin film structure over a wide area even with subsequent gI/Iy conversion. It is difficult to do so.

Further, as another ultra-thin film SOI formation method, there is a lateral in-phase epitaxial growth method. As shown in FIG. 3(a), an oxide film 3 having an opening pattern is formed on a Si substrate 1, and an amorphous Si layer 5 deposited thereon is deposited on a substrate t.
This method produces a single crystal from the contact area. This method provides control over film thickness.

Although the uniformity is excellent, since crystallization progresses along the oxide film with deposition shrinkage, crystal defects are likely to occur near the interface with the underlying oxide film, making it difficult to obtain high-quality SOI.

The above conventional technology has a uniform ultra-thin vA over the entire wafer surface.
It was difficult to obtain an SOI structure. In addition, ultra-thin film S
Regarding the structure of the OI element, problems such as parasitic resistance have not been sufficiently studied.

[Problem to be solved by the invention]

The purpose of the present invention is to provide a uniform ultra-thin film S over the entire wafer surface.
○The goal is to provide an ultra-thin structure suitable for integration of the V4 element, which reduces the parasitic resistance of the source and drain parts in order to maximize the performance of the SOI element.

Another object of the present invention is to provide a new SOI formation process to achieve the above objectives.

Another object of the present invention is to change the process from forming interconnects to forming a semiconductor active layer, whereas the conventional manufacturing process for semiconductor devices is performed from processing the semiconductor substrate to wiring. The objective is to provide a completely new method of manufacturing semiconductor devices.

[Means to solve the problem]

In order to reduce the parasitic resistance of the above-mentioned element, it is effective to use a structure in which the source/drain regions are thickened and only the operating region of the element is made ultra-thin. More preferably, the source/drain regions are made of a silicide alloy,
It may be formed of a low resistance material such as a pure metal or an oxide superconducting material.

However, it is difficult to uniformly and selectively thin an SOI film once formed, and it is even more difficult to partially form an alloy layer or a metal layer as described above.

In order to achieve the above objective, it is effective to repeat in-phase growth twice. In-phase growth has excellent controllability of surface morphology, and is applicable to complex processes because it is a low-temperature process, but it is strongly dependent on crystal orientation, and it is difficult to produce high-quality single crystals by simply repeating the process blindly. Thin film S
OI is not available.

That is, the semiconductor device of the present invention includes, on an insulating substrate,
Or 5OI (Semiconductor-on-In5ul) in which a semiconductor layer is provided on an absolute layer provided on a semiconductor substrate.
ator) structure, the semiconductor layer includes a crystalline support having a first thickness selectively formed on the insulator substrate or the insulator I1 layer, and a crystalline support having a first thickness. The second crystalline semiconductor layer extends over the insulating substrate in contact with at least a portion thereof, and has a thickness thinner than the first thickness.

Further, the crystalline support is provided at intervals on the insulating substrate or the insulating layer, and the second crystalline semiconductor layer is provided at least on the crystalline support and on the crystalline support. It is also characterized in that it is provided on the insulating substrate or the insulating layer between them.

Further, the second thickness is 0.1 pm or less.

The crystalline support is also characterized in that it is made of the same material as the second crystalline semiconductor layer or a material containing at least the constituent elements of the second crystalline semiconductor layer.

Further, the crystalline support is made of a part of the semiconductor separated from the semiconductor substrate, and is also made of the same material as the semiconductor substrate.

It is also characterized in that the angle of the end face of the crystalline support with respect to the substrate surface is 45 to 90°.

Further, in the method for manufacturing a semiconductor device of the present invention, on an insulating substrate or on an insulating layer provided on a semiconductor substrate,
providing a crystalline support having a first thickness; the crystalline support extending over the insulating substrate in contact with at least a portion of the crystalline support and having a thickness thinner than the first thickness; The method is characterized in that it includes a step of providing a second semiconductor layer, and a step of single crystallizing the second semiconductor layer by in-phase epitaxial growth using the contact portion as a seed.

Further, the first and second crystalline supports are provided at intervals on the M textile substrate or the insulating layer, and the second semiconductor layer is provided at least on the crystalline support and on the crystalline support. Provided on the insulating substrate or the insulating layer between the supports, and prior to single crystallization of the second semiconductor layer,
It is also characterized in that the second semiconductor layer in contact with the first crystalline support and the second semiconductor layer in contact with the second crystalline support are processed separately.

For example, the present invention will be described with reference to the case of forming a Si S○ structure. First, a (100) oriented substrate is used as a base semiconductor substrate. An oxide film that will serve as a base substrate for the ultra-thin SOI film is formed on this.

Next, the base oxide film 7 is processed so that its opening ends are along the <100> direction. In such a situation, for example, amorphous Si deposited by ultra-high vacuum evaporation grows epitaxially from the contact area with the underlying substrate (hereinafter referred to as "seed").
A region several micrometers from the seed end becomes a single crystal. in this case,
The thickness of the underlying oxide film is preferably 0.2 .mu.m or less, and the deposited amorphous Si usually needs to be 0.5 .mu.m or more thick.

The SOI formed in this way becomes a film with excellent crystallinity with few crystal defects in the surface layer of the single crystallized region.
A high density of crystal defects is introduced into the region near the interface with the base oxide film. Therefore, even if the layer is made thin as it is, a high quality ultra-thin SOI film cannot be obtained.

Therefore, the single crystallized portion of the SOI formed is <100>
The patterning is performed in the direction along the substrate, and the side surfaces are not perpendicular to the substrate but are inclined. The situation is shown in sectional view in FIG. 1(a).

The first 5OIs 40 are formed at certain intervals. Using this state as a substrate, an amorphous Si layer 50 with a thickness of 0.1μ
It accumulates to a certain extent. FIG. 4 shows the state of in-phase growth resulting from heat treatment. In the deposited amorphous Si layer 50, solid-phase epitaxial growth progresses in the directions shown by the arrows in the first approximation, using the contact portion with the first S○I 40 as a seed. FIG. 4(a) shows the situation when solid phase growth is performed in the deposited state, and FIG. 4(b) shows the situation where the amorphous Si layer 50 is grown before solid phase growth as shown in FIG. This shows the in-phase growth when buttering.

If solid-phase growth is performed in the deposited state, the epitaxial growth proceeds in approximately the same direction, so that in the intermediate portion 51 of the first SOI 40, the growth ends that have progressed from both islands collide, and the crystallinity deteriorates there. This is difficult to recover even by heat treatment when the distance between the first SOIs is as large as several microns. When considering application to microscopic devices, the active part of the device is often formed in this region.

It is desirable to avoid this situation. Figure 4(b) shows a situation where the ultra-thin film SOI part is patterned asymmetrically, but if solid-phase growth is performed after processing in this way, the seed will be on only one side, and the direction of growth of in-phase growth will be uniform. Since the direction is restricted, the probability that a grain boundary will enter the ultra-thin film SOI region is extremely low.

Next, the advantage of providing an inclination to the side surface of the first SOI will be described. FIG. 3(a) is a cross-sectional view showing the seed shape and growth state in conventional solid-phase growth, and FIG. 3(b) is an enlarged cross-sectional view at the seed end showing the seed shape and growth state in the present invention. It is a diagram. In both figures, the surface is (001
2 schematically shows the arrangement of Si atoms when the (010) cross section of the substrate, which is a ) plane, is viewed in the <010> direction. When the seed portion is located in a horizontal plane (perpendicular to the paper) extending the lower interface of the oxide film 3 as shown in Figure 3(a), when solid phase growth is performed upward while forming a crystal lattice, the edge of the oxide film A (101) facet (habit crystal plane) 6 is formed by a series of atomic rows that cannot form a regular lattice starting from the positional mismatch of the 81M molecules of . Since the growth rate of this (101) facet is slower than the growth rate in the upward [001] direction, it can be safely assumed that it starts after the upward epitaxial growth is completed. Since the growth of the (101) facet progresses while receiving interaction with the oxide film 3, the (101) facet 7 grows laterally on the oxide film 3.
is formed. For this reason, there is generally a problem that crystal defects are likely to occur in SOI after growth.

In the case of the present invention, as shown in FIG. 3(b), the first S○
Since I40 and the deposited Si film 50 come into contact with each other in the situation shown in the figure, the growth in the [1oo] direction, where the growth rate is high, takes precedence, and the lateral growth starts from above the deposited film, as shown by arrow 8. That will happen.

Therefore, the crystallinity of the grown SOI is also good. This effect is due to the fact that the seed surface is 45"
This is expected when the slope is higher than that.

If the slope is 45″ or more, there is a (100) downward growth component from the seed end surface in the early stage of growth.
This is because crystallization is led in the upper part of the SOI film during lateral growth. When this slope is 90°, that is, perpendicular to the substrate, it is most advantageous in terms of device miniaturization, but when an amorphous Si layer is formed by a directional thin film deposition method such as vapor deposition, the adhesion of the sidewall portion is Another problem is that it deteriorates and becomes susceptible to defects. In the following description, the first SOI
Although the end face is shown slightly inclined with respect to the substrate, that angle is not essential.

In addition, when the spacing between the first SOIs becomes extremely small, such as 0.2μ or less, defects due to mismatch formed by the collision of the solid-phase growth ends from the supports on both sides, as described above, can be removed by heat treatment. disappears easily. When applying the present invention to such a fine structure, it is not necessarily necessary to limit the growth region prior to solid phase growth.

[Effect]

When growing an ultra-thin SOI film in a solid phase, an SOI with good crystallinity is formed by forming a protruding seed on the underlying substrate and forming a deposited film so that at least a portion of the seed is in contact with this. be able to. By doping the protruding seed portion with impurities at a high concentration, it can be used as a source/drain contact portion of an FET, and can also be used as a wiring portion of an integrated circuit. It is known that amorphous Si doped with active impurities such as B and P has a high solid phase growth rate.
This is advantageous for forming the first SOI portion that becomes the foundation of an ultra-thin film SOI as in the present invention.

〔Example〕

The present invention will be explained below using examples.

Example 1 FIG. 5 is a schematic cross-sectional view showing the process of forming an ultra-thin Si film SOI.

A p-type (100), 9-12Ω1 Si substrate 1 is connected to a known L
Selectively oxidized by OCO8 method, 0.2μ thick 5i
02 Layer 3 obtained Next, after removing the natural oxide film on the opening surface 8 with an HF aqueous solution, it was placed in an ultra-high vacuum deposition tank with an ultimate vacuum of 10-'Pa and heated at 850°C for 30 minutes. After this, amorphous Si was deposited to a thickness of 0.6 μm by electron beam evaporation at a substrate temperature of 200° C. 45 in the same vacuum chamber
After heat treatment at 0° C. for 1 hour, it was taken out from the vacuum chamber and 31P+ was heated at 60 keV by ion implantation.
8X 10"aa-", 130keV, 3.3X10
"(5m-", 236ke V, 7,8X101Sam
-” three stages of doping were carried out. This was carried out in N2,
Heat treatment was performed at 600° C. for 8 hours to obtain an SOI layer with a thickness of approximately 40 μm from the seed end (FIG. 5(a)). Next, this first SOI layer was processed into stripes having a width of 1.0 μm and an interval of 3 μm (FIG. 2(b)). The processing was carried out by wet etching so that the side surface had a trapezoidal cross section inclined at about 70 degrees with respect to the substrate.

Next, this was introduced into the ultra-high vacuum evaporation equipment again, and 850
After heat treatment at 35°C for 30 minutes, electron beam evaporation
Approximately 75 nm of amorphous 5i50 was deposited at 0°C and heat-treated at 600°C for 2 hours in the same vacuum (see Figure 5).
C)).

Through the above steps, an ultra-thin SOI structure supported on both sides by thick SOI was obtained. Next, starting from this structure, C
An example of manufacturing a MOS inverter is shown in FIG.

The ultra-thin SOI film is shaped and separated so that a part thereof covers the striped first thick film SOI portion, and gate oxidation is performed at 850° C. to form a gate oxide film 7 with a film thickness of 20n+w.
1 was formed. Next, doped poly-Si was deposited to form gate pairs 72. Gate thickness is 0.6μ
m, the width is 0.8 μm, and the interval is about 1.2 μm. Next, using this gate 72 as a mask, apply BF2'' to the right gate portion and As'' to the left gate portion, respectively. Ion implantation was performed by selecting an energy that would bring the peak to the middle of the thin film SOI.
The dopant was activated by heat treatment for 0 minutes.

Next, a psG (phosphosilicate glass) film was deposited to a thickness of 0.8 μm using the CVD (chemical vapor deposition) method, and the support 40
A hole was made in the intermediate portion of the gate and the gate, and Al was deposited to a thickness of 0.8 μm. Depending on the electrode formation pattern, Vss[pole 73, node electrode 73', Voo@
Each electrode lead-out portion of the pole 73' was formed to form a CMOS inverter.

Example 2 An example in which a MOSFET with minute dimensions was formed by a similar process will be explained with reference to FIGS. 5 and 6.

Forming the first 5OI40, amorphous S for ultra-thin SOI
The procedure up to the point of forming the i-layer 50 is the same as in Example 1. However, the thickness of the first 5OI 40 is 0.4 μm, the width of the stripes is 0.5 μL, and the interval is 1.0 μm. The thickness of the amorphous Si film 50 for forming the ultra-thin film SOI is 50 nm, and the temperature is 450° C. when the deposition is completed.
After heat treatment for 1 hour, it was taken out from the vacuum chamber. The Si film 50 formed on the left side of the support 50140 was removed by etching, gate oxidation was performed, and a gate 72 of @0.2 μm was processed. As “6” using the gate as a mask
0keV.

A 6×10 14 am −2 implant was performed and annealing was performed at 600° C. for 1 hour. Next, CVD-PSG was applied to a film thickness of 0.5
A drain electrode 74 is deposited on the support, and a source electrode 74' is deposited over the other support and the ultra-thin film SOI.
Holes were made to form electrodes, and electrodes were formed by At vapor deposition. Although the effective channel length of this n-channel type MO8FET was 0.16 μm, normal operating characteristics were obtained.

Furthermore, in a similar process, a p-channel MOSFET obtained by ion-implanting BF,'' instead of As'' to form the source/drain portion had an effective channel length of 0.18 μm, but was also similar. showed normal operation.

Example 3 FIG. 8 shows an example in which a MOSFET with a finer structure was formed by applying the present invention. The substrate used was (100), A
S-doped n7 type, 0.002 ΩG, heated to 600°C, oxygen ions at 180 keV, 1.8X10
"3-" was implanted, CVD S x Oz was applied, and heat treated at 1350°C for 20 minutes. The first SOI serving as the support shown in Example 1.2 is single-crystal Si that remained on the surface during the process of forming the buried oxide film, and contains about 10'ai-'' dislocations. of,
It was fabricated into a structure in which stripes with approximately trapezoidal cross sections were arranged in parallel. This is done by exposing a positive resist using optical photolithography so that one stripe with a width of two trapezoidal stripes remains, and then exposing the center of that stripe to light by scanning an electron beam. was developed. Using this as a mask, dry etching was performed while adding isodirectional etching to produce a tapered shape.

The stripe spacing was 1105n.

This structure was coated with a thickness of 5 cm at 530°C by CVD of Si, H,
A 5 nm undoped amorphous Si layer 50 is formed, and 580
Solid phase growth was performed by heat treatment at ℃. In this case, since the stripe spacing is extremely narrow, the single crystallization that progresses from the contact areas with the supports 40 on both sides coalesces in the center of the supports, and crystal defects due to mismatches that occur at that time are removed by heat treatment in the subsequent process. disappeared due to

After leaving the element forming part of the SOI structure after single crystallization, it is heated to a thickness of 20μ by plasma oxidation at 700°C.
An oxide film 71 of ++w was formed. Next, doped poly S
i was deposited by CVD, and gate 72 was formed by conventional methods. After adding light oxidation again, CVD-
8i○2 and CVD-PSG film 7 were deposited, and the insulating film was patterned so that both supports were exposed. lastly,
Al was deposited to form an FET using the supports on both sides as the source and drain.

This FET has an effective channel length of about 1100n, a channel thickness of 40nm, and an FET close to triode characteristics.
It showed ET behavior.

Example 4 The material of the support is not limited to Si. Next, an example in which a structure similar to that in Example 4 is formed using C08i2 will be described with reference to the same FIG. 8.

After oxidizing a P-type (111), 8Ω Si substrate and drilling a hole in the seed portion, the substrate temperature was adjusted to 100% by ultra-high vacuum electron beam evaporation so that the composition ratio of CO and Si was 1=2. They were simultaneously deposited at 0.degree. C. to form an amorphous film with a thickness of 0.5 .mu.m. This was heat-treated at 380° C. for 3 hours to form a single crystal by solid-phase growth, and a single-crystal Co S j layer was formed in a region 10 μm from the seed end. Using this as the support 40, an FET was fabricated using the same process as in Example 3. In this FET, the parasitic resistance of the source and drain was reduced, and the operating frequency was improved compared to the FET of Example 3.

Example 5 The first 5OI4 was prepared by the method of forming the support shown in Example 1.
After forming 0 and thinning it to a thickness of 0.2 μm,
CO was deposited to a thickness of about 0.15 μm and silicided by heat treatment at 800° C. Unreacted metal C.

After removing C by acid washing, C was removed by the process shown in Example 1.
A perfect example of a MOS inverter.

Also in this element, the gate delay time was improved by about 30% compared to the CMO8 inverter chain described in Example 1 due to the effect of reducing parasitic resistance.

At the time of silicidation, the surface morphology tends to deteriorate due to deposition changes. Deterioration could be prevented.

Example 6 An example in which the present invention is applied to a dRAM cell is shown in FIGS. 9 and 1.
This will be explained using Figure 0.

First, in FIG. 9, the substrates are n'''' (100), 0.
It is a Si wafer 1 with a resistance of 0.02 Ω, has a buried insulating film 3 of 0.2 μm formed by oxygen ion implantation, and has an SO
I has a thickness of 0.15 μm. This first SOI layer was processed into a quadrangular pyramid-shaped support 40 with a side length of 0.3 μm and a thickness of 55 μm.
An ultra-thin film of r++* amorphous Si/l was formed and solid-phase grown. This ultra-thin film 5OI50 was processed in the direction along the plane of the paper to have the width of a square pyramid, and the width of the portion to be used as the FET channel was regulated. Next, gate oxidation is performed to form a 8 nm thick Si
After forming an equivalent film 71, a gate 72 was processed by doped poly Sx deposition and pattern etching. Using the gate as a mask, low-concentration P+ ion irradiation was performed and light oxidation was performed, followed by CVD-8in.

A sidewall spacer 75 was formed using an etch pack, and an n+ region was formed by plasma doping using this as a mask.

Next, as shown in FIG.
After depositing and patterning the capacitor shape, the capacitor Il! An Iil film 77 was deposited. Although FIG. 10 shows the case where the surface is simply oxidized, there is no difference in the subsequent steps even if a SiO, -8i3N4 composite film is used. Next, a doped poly-Si film 78 is deposited and processed into a plate shape, and CVD-3in, film and CV
After depositing the D-PSG film and drilling a contact hole in the truncated pyramid 40 portion, the bit line 79 is formed by depositing metal.
It was shaped into a memory structure.

This embodiment is a stacked capacitor type dRAM cell having a folded structure above a word line 72 using a square pyramid 40 as a common bit line contact. Thin film transistors and isolated capacitors with high radiation resistance have been realized, making it possible to downsize dRAM cells.

Example 7 Taking advantage of the fact that the present invention inherently allows for lowering the temperature,
An example applied to a layered structure element will be explained based on FIG. 11.

FIG. 11 basically shows the CMO of Embodiment 1 shown in FIG.
It has a structure in which two layers of S inverters are stacked.

The process for forming a CMOS inverter using the first SOI layer 50 is the same as that shown in Example 1. Note that the substrate 1 for forming the first SOI layer may have an element portion 11 formed by a conventional process on its surface. The difference from FIG. 7 is that the electrode contacts of the nodes are not on the same cross section as the source and drain shown in the paper.

The point is that it is located at a position shifted in the depth direction relative to the plane of the paper. For example, the gate 172 of the element formed in the upper layer is connected through a region 173' hatched with dotted lines.

The differences from the process in Figure 7 are: CVD-8in, film, CVD
- After forming N7 made of a PSG film, it is planarized by a known method such as applying a resist that has the same etching rate as PSG and etching back, and making holes in the support portion.

An amorphous Si layer is deposited thereon, solid-phase grown using the lower support 40 as a seed, and patterned to form the second layer support 140. Thereafter, a second layer of thin film 5Or150
, and form a gate oxide film 171 and a gate 172.
A second layer 107 consisting of a CVD-8in film and a CVD-PSG film is formed, a contact hole is made to the second support, a metal layer is formed, and the extraction electrode 1 is formed.
73, F3', etc., to create a tandem type C with a laminated structure.
Completed MOS inverter structure.

When forming the 2Nth SOI, the 1Nth ultra-thin SOI
Although it is possible to take the seed from I.

Processing control is difficult and impractical. Therefore, the first
The layer support and the second layer support have a structure in which they are electrically connected at the seed, but this does not limit the connection relationship between the first layer element and the second layer element. . Second
It is possible to electrically isolate the SOI element of the second layer and the support of the second layer by processing after forming the SOI layer, and as in this example, it is possible to electrically isolate the SOI element of the second layer from the support of the second layer. There is no requirement that an upper layer element be placed directly above the element.

Furthermore, although this embodiment shows an example in which up to two layers of SOI/I are used, according to the spirit of the present invention, there is no limit to the number of layers to be laminated, and However, it is clear that it may be formed over the entire surface or may be applied partially.

The main function of the first SOI in the present invention is to
providing seeds for solid phase growth of OI;
The object of the present invention is to provide a low resistance layer when forming an element.

For this purpose, the seed does not necessarily have to be the same material that forms the ultra-thin SOI. The fact that the in-phase rli length is a low temperature process is also advantageous when using other materials.

For the above purpose, a silicide with relatively high lattice matching with Si, such as NiSi (::oSi), can be used. Also, depending on the purpose, a heat-resistant pure metal such as W or Mo can be used. You can also do that.

Silicide-based materials have a higher in-phase a-degradation rate than Si, and lattice relaxation by heating, that is, removal of defects, is easy, so seeds with good crystallinity can be formed over a wide range. However, if the material is changed, the discussion regarding the crystal orientation described above needs to be changed as appropriate to ensure consistency in lattice constants, but the gist of the present invention remains unchanged.

Furthermore, the substrate used for seeding does not necessarily have to be made of ultra-high purity material; for example, even medium-purity Si called solar grade can be used as an LSI substrate in the present invention. It is.

The semiconductor material that also forms the ultra-thin film SOI is not limited to Si.

The present invention can be similarly applied to semiconductors based on group Ⅰ elements such as Ge, 5iGe, and SiC.
lAs, AlGaAs, GaP, AIGaAsP, Al
m-v group compound semiconductors such as Sb, InSb, InP, InAsP, etc.

IF-rV group compound semiconductors such as CdS and CdTe can be similarly applied.

〔Effect of the invention〕

As described above, according to the present invention, an ultra-thin SOI structure having excellent device characteristics can be formed uniformly over the entire wafer surface using a method with the best thickness controllability. Moreover, at low temperatures where impurity redistribution does not substantially occur,
A film with good crystallinity can be obtained. In addition, only the portions necessary for element operation can be obtained with a thin film structure, and portions that are hindered by large parasitic resistance can be formed of a low-resistance material, and can be constructed in a self-aligned manner. Furthermore, it is possible to form a portion for wiring first, and then optionally form a semiconductor portion that will become an active region of the element later.

It is also suitable for forming elements with fine structures, ultra-high density LSIs, three-dimensional circuit elements, etc.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are schematic cross-sectional views showing the basic structure of the embodiment of the present invention, and FIGS. 2(a) and (b) are conventional S
Schematic cross-sectional diagram showing OI applied structure, Figure 3 (a), (b)
4(a) and 4(b) are cross-sectional schematic diagrams for explaining the advantages of the structure of the present invention on crystal growth, and FIGS. 4(a) and 4(b) are effects of shape regulation before growth on solid phase growth in one embodiment of the present invention. FIGS. 5(a), (b), and (c) are schematic cross-sectional views for explaining the steps in one embodiment of the present invention, and FIGS. 6(a), (b), and Figure 7, Figure 8, Figure 9,
FIGS. 10 and 10 are schematic cross-sectional views showing embodiments of the present invention, respectively. 1... Substrate 3... Edge film 40... Crystalline support (first 5oI) 50... Ultra-thin film SOI

Claims (1)

[Claims] 1. SOI (Sem) in which a semiconductor layer is provided on an insulating substrate or an insulating layer provided on a semiconductor substrate.
In a semiconductor device having a structure (conductor-on-insulator), the semiconductor layer includes a crystalline support having a first thickness selectively formed on the insulating substrate or the insulating layer; extending over the insulator substrate in contact with at least a portion of the support;
A semiconductor device comprising a second crystalline semiconductor layer having a thickness thinner than the first thickness. 2. The crystalline support is provided at intervals on the insulating substrate or the insulating layer, and the second crystalline semiconductor layer is provided at least on the crystalline support and on the crystalline support. 2. The semiconductor device according to claim 1, wherein the semiconductor device is provided on the insulating substrate or the insulating layer between them. 3. The semiconductor device according to claim 1 or 2, wherein the second thickness is 0.1 μm or less. 4. Claim characterized in that the crystalline support is made of the same material as the second crystalline semiconductor layer or a material containing at least the constituent elements of the second crystalline semiconductor layer. 3. The semiconductor device according to 1, 2 or 3. 5. The semiconductor device according to claim 1, 2, 3, or 4, wherein the crystalline support is made of a part of the semiconductor separated from the semiconductor substrate, and is made of the same material as the semiconductor substrate. 6. Claims 1 and 2, wherein the angle of the end face of the crystalline support with respect to the surface of the substrate is 45 to 90 degrees.
, 3, 4 or 5. The semiconductor device according to . 7. Providing a crystalline support having a first thickness on an insulating substrate or an insulating layer provided on a semiconductor substrate, and contacting at least a portion of the crystalline support. providing a second semiconductor layer extending over the insulating substrate and having a thickness thinner than the first thickness; and forming the second semiconductor layer by solid phase epitaxial growth using the contact portion as a seed. 1. A method for manufacturing a semiconductor device, comprising the step of single crystallization. 8. The first and second crystalline supports are provided at intervals on the insulating substrate or the insulating layer, and the second semiconductor layer is provided at least on the crystalline support and on the crystalline support. The second semiconductor layer is provided on the insulating substrate or the insulating layer between the supports, and prior to single crystallization of the second semiconductor layer, the second semiconductor layer and the second semiconductor layer are in contact with the first crystalline support. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the second semiconductor layer in contact with the crystalline support is processed separately.