JPH0935421A - Phase locked loop and data reader employing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the stability of a phase control loop while shortening the lock-in time with no limitation on the operational range. SOLUTION: The inventive circuit comprises a PLL circuit 20 for generating a clock based on an input data, a data discriminator circuit 22 for latching the input data with the clock, and a CRC detection means 43 for detecting the lock-in state of PLL based on the latched output. The PLL comprises a VCO 24, a phase comparator 25 for comparing the phases of an oscillation output and an input signal, a limiter circuit 26 provided at the output stage of phase comparator, and a feedback loop for controlling the limiter level. The limiter circuit 26 is operated as a tracking limiter through the feedback loop at the time of lock-in and operated as a locked limiter by opening the feedback loop at the time of lock-out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit suitable for application to a magneto-optical disk recording / reproducing apparatus and the like and a data reproducing apparatus using the same. For details, use the CRC flag when reading the address from the magneto-optical disk, and use the phase locked
The phase feedback loop with the tracking limiter is operated only when the loop is locked to the input signal, and the lock-in time is shortened by fixing the limiter level when unlocked, and the phase control is performed without limiting the operation area. It improves the stability of the loop.

[0002]

2. Description of the Related Art As is well known, a magneto-optical disk is preformatted (precoded) with address data and the like for each sector. In the magneto-optical disk 1 shown in FIG. 5A, the recording area is divided into an inner recording area (channel 1) and an outer recording area (channel 2), and one track formed in each recording area is a plurality of sectors, for example. It consists of 42 sectors.

One sector is composed of a precoded address area (address section) ADD and a recording data write area (data recording section) MO as shown in FIG. 5B. In the address portion ADD, address data of the same content is repeatedly formed three times after the sector marker SM as shown in FIG. The reason for repeating three times is to ensure that the address data can be read even when there is a read error. This address data is composed of VFO data, an address marker AM, and identification data ID. Since a VFO (variable frequency osillator) generates a reference signal (reference clock), a clock generation P
It is a single frequency signal used for pulling the operation of the LL oscillator. Following the address data, postamble data PA is recorded.

Each of these address data is preformatted data, and data is formed by pits. There is a data recording unit MO following the address unit ADD, and a test area is provided at the beginning of this data recording unit MO. In the test area, ALPC data for controlling the power level of the laser diode is followed by VFO data VFO4 (VFO1 to VFO3).
The same data) is recorded.

Data is recorded in the data recording unit MO by controlling the magnetization direction. A buffer area (non-recording portion) is provided at the end of the data recording portion MO to clarify the boundary with the address portion ADD. The illustrated number of sectors and the number of bytes constituting one sector are merely examples.

FIG. 6 shows a conventional example of a data reproducing apparatus 10 for recording data on such a magneto-optical disk 1 and reproducing the recorded data or address data. Laser light is shown as the recording / reproducing light.

In FIG. 6, in the optical pickup means 11, in addition to a laser diode (not shown) as a light source, photodiodes PDa and PDb as a pair of photodetectors are provided.
Is provided, and the reflected light from the magneto-optical disk 1 is received at the same time. The pair of input signals (currents) obtained by receiving the light are supplied to the adder 12a to form a sum signal.
This sum signal is a light intensity signal, and is a reproduction signal SR of the address data preformatted in the address section ADD.
Becomes Also, a pair of input signals is supplied to the subtractor 12b to form a difference signal. The difference signal is a rotation phase signal in which the optical signal is deviated by the Kerr effect, which is a reproduction signal S related to the data recorded in the data recording unit MO.
It becomes M.

The reproduction signal SR is supplied to the switching pulse generation circuit 14 through the preamplifier 13a, and a switching pulse corresponding to the envelope output of the reproduction signal SR is generated. The pair of reproduction signals SR and SM supplied to the switching circuit 15 are switched by this switching pulse, and the two are combined (addition processing) to form a reproduction signal sequence.

The addition reproduction signal SO is equalized in the equalizer circuit 16 to have a cosine descending characteristic.
The reason for giving the cosine descending characteristic is to increase the aperture ratio of the eye pattern of the reproduction signal by reducing the intersymbol interference of the reproduction signal in the transmission band. When the aperture ratio of the eye pattern is increased, the waveform shaping error of the reproduced signal is reduced and the reproduced signal can be correctly demodulated (decoded).

The high frequency signal of the reproduced signal RF waveform-equalized is supplied to the waveform shaper 18 and converted into a pulse signal according to the data. The waveform-shaped reproduced signal is supplied to the discrimination circuit 22 composed of a latch circuit,
In order to generate a synchronization signal (clock signal) for discrimination, P
It is supplied to the LL circuit 20. The PLL circuit 20 generates a synchronization signal CK that is synchronized with the basic period of the pulse signal described above, and this synchronization signal becomes a window pulse to discriminate the reproduction signal (pulse signal) RF.

The discrimination circuit 22 forms a detection code string according to the presence or absence of data, and this is supplied to a decoder (not shown) in the subsequent stage and decoded into a data bit string, that is, a data bit string at the time of recording.

The added reproduction signal RF after the waveform equalization is further formed by the multiplier 19 into a signal twice the reference clock and then supplied to the PLL circuit 20 to generate the synchronizing signal CK. As is well known, the PLL circuit 20 has a variable oscillator, which is a voltage-controlled variable oscillator (VCO) 24 in this example. The oscillation output and the multiplied reproduction signal RF are supplied to a phase comparator 25, and its phase is increased. The comparison output is the limiter circuit 26.
Also, it is applied as a frequency control voltage to the variable oscillator 24 via a buffer amplifier (having a low-pass filter function) 27.

The limiter circuit 26 is provided so that the oscillation frequency exceeds the lock-in range (pull-in range or capture range) due to the excessive output of the phase comparator 25 generated when the power is turned on or when disturbance is mixed. This is to prevent control. The limiter circuit 26 stabilizes the operation of the PLL circuit 20. As shown in FIG. 7, the limiter circuit 26 has upper and lower limiter levels LIM (+) and LIM (-), and a frequency control voltage exceeding this limiter level causes the phase comparator 2
When it is output from 5, it operates so as to suppress the control voltage to this limiter level.

[0014]

As described above, in order to secure the stability of the operation, the limiter circuit 26 that operates as an error limiter is provided in the PLL feedback loop. With this limiter circuit 26, the PLL circuit is provided. 20
The operating area of may be returned and limited. This is because the variable oscillator 24 and the phase comparator 25 both have a temperature characteristic, and thus the center value of the frequency control voltage fluctuates up and down due to this temperature characteristic. Since the variable oscillator 24 does not follow a control voltage above the limiter level, if a frequency control voltage accompanied by level fluctuation due to temperature characteristics is input, even if the voltage level does not cause lockout, it is fixed at the oscillation frequency determined by the limiter level. Will be done. As a result, the operation area of the PLL circuit 20 is limited.

Therefore, the present invention solves such a conventional problem, and proposes a PLL circuit in which the stability of the phase control loop is improved without limiting the operation region.

[0016]

In order to solve the above-mentioned problems, in the phase locked loop circuit according to the present invention described in claim 1, the phase of the variable oscillator is compared with that of the oscillation output and the input signal. A phase-locked loop circuit configured to be supplied as an error detection voltage to the variable oscillator via an amplifier having a low-pass filter. A limiter circuit provided at the output stage of the phase comparator, a feedback loop for giving the output of the amplifier to the limiter circuit for limiter level control, and a tracking capacitor connected to the feedback loop, When the phase locked loop is locked in, the feedback loop given to the limiter circuit causes Operates as a tracking limiter circuit, the phase locked loop is characterized in that the feedback loop applied to the limiter circuit is adapted to operate as a fixed limiter circuit is opened while locked out.

In the data reproducing apparatus according to the present invention as defined in claim 3, a phase locked loop circuit for generating a clock based on input data, and a data discrimination in which the input data is supplied and is latched by the clock. From the latch circuit for the
Lock detection means for detecting a lock-in state of the locked loop circuit, the phase locked loop circuit, a variable oscillator, a phase comparator for comparing the phase of the oscillation output and the input signal, An amplifier having a low-pass filter, the phase comparison output of which is supplied as an error detection voltage to the variable oscillator, a limiter circuit provided at the output stage of the phase comparator, and the output of the amplifier to the limiter circuit. The feedback loop, which has a feedback loop for giving it as a limiter level control, and a tracking capacitor connected to the feedback loop, and which is given to the limiter circuit when the phase locked loop is locked in. It operates as a tracking limiter circuit by
When the locked loop is locked out, the feedback loop given to the limiter circuit is opened to operate as a fixed limiter circuit.

When the phase locked loop is locked in, this limiter circuit operates as a tracking limiter circuit by the feedback loop provided to the limiter circuit. As a result, even if the curve of the frequency control voltage fluctuates vertically from the center value of the control data due to temperature fluctuations, the limiter level moves up and down following this. Therefore, the operating region of the PLL circuit is not narrowed by the temperature characteristic.

When the phase locked loop is locked out, the feedback loop provided to the limiter circuit is opened. As a result, the limiter circuit operates as a fixed limiter circuit, and lock-in is performed quickly, so that stable PLL operation can be realized.

The lock detecting means is a CRCC (Cyclic Red
A lock-in state is detected by the presence or absence of a CRC flag. The CRC flag is set when the PLL circuit is locked in, and the CRC flag is not set when the PLL circuit is locked out. When locked in, the feedback loop works and the tracking limiter operates. When locked out, the feedback loop is opened and the capacitor connected to the feedback loop is reset, so that the fixed limiter operation is performed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a case where an embodiment of a phase locked loop circuit according to the present invention and a data reproducing apparatus using the same is applied to the above-mentioned recording / reproducing apparatus for a magneto-optical disk will be described. Will be described in detail with reference to.

In the present invention as well, the basic structure of the data reproducing apparatus 10 shown in FIG. 6 is followed, and the reproducing signal SR from the address part ADD and the reproducing signal S from the data recording part MO.
M composite signal SO is obtained (FIGS. 2A to 2D), and this composite signal S
It is the same as in the prior art that the reproduction signal RF is formed from O in a data format suitable for data reproduction. Then, the reproduction signal RF is supplied to the PLL circuit 20 to supply the synchronization signal C.
It is also the same as the conventional method that K is obtained and data discrimination processing is performed by the discrimination circuit 22 using this.

In the present invention, the waveform shaper 18 and the discrimination circuit 2
2, a switching circuit 30 is provided between the two and the continuous wave signal EE is inserted in a section where the reproduction signal RF is discontinuous. The frequency of the continuous wave signal EE can be the same as the frequency of VFO, for example. The discontinuous section is shown in Figure 2D.
As shown in, the area is between the buffer area BA and ALPC. The continuous wave signal EE given to the terminal 31 is the reproduction signal R
It is supplied to the switching circuit 30 together with F. The reason why the continuous wave signal EE is inserted is to stabilize the operation of the PLL circuit 20 described later.

Further, the combined signal SO output from the waveform equalizer 16 is supplied to the signal detection circuit 32 to be combined signal SO.
A discontinuous section of is detected. The detection signal of this discontinuous section is supplied to the switching circuit 30 as a switching pulse, and the continuous wave signal EE shown in FIG. 2F is inserted into the reproduction signal RF (FIG. 2G).

In this example, the continuous wave signal EE can be inserted in both the manual mode and the recording mode. Therefore, an OR gate circuit 33 is provided, and a manual signal or the like from the terminal 34 is supplied together with the detection signal of the discontinuous section. This OR output is used as a switching pulse.

The PLL circuit 20 for obtaining the synchronization signal CK is shown in FIG.
It is configured as shown in. The basic configuration of the PLL circuit 20 is also the same as the conventional one, and a voltage controlled variable oscillator (VCO) is used.
24, the phase of the oscillation output and the reproduction signal RF is compared by the phase comparator 25, and the phase comparison output is the limiter circuit 2
6 and a variable amplifier 24 via a buffer amplifier 27 having a low-pass filter function as a frequency control voltage. When the reproduction signal is not input to the phase comparator 25, the variable oscillator 24 returns to the frequency of the operation center (free running frequency).

In the present invention, the limiter circuit 26 is controlled so as to perform the tracking limiter operation when the PLL circuit 20 is locked in, and the fixed limiter operation when the PLL circuit 20 is in the lockout state. Therefore, the PLL circuit 2
The following configuration is added to 0.

The limiter circuit 26 has a pair of diodes 37 and 38 and a resistor 36 that determine upper and lower limiter levels. A feedback loop is formed between the output stage of the buffer amplifier 27 and the pair of diodes 37 and 38, and a buffer amplifier 40 is provided in the feedback loop via a switch 39.
Is provided, and a capacitor 41 for charging / discharging is provided in the input stage.
Is connected.

On the other hand, the discrimination circuit 2 composed of a latch circuit
The second output stage is provided with detection means 43 for an error correction code such as CRCC. The detecting means 43 is provided to detect the lock-in state of the PLL circuit 20, and in this example, it is the CRC flag detecting means.

When the PLL circuit 20 is locked in, the reproduction signal RF is generated by the synchronizing signal CK from the PLL circuit 20.
Since the data string of can be correctly latched, CR is
Address part AD by decoding CC code
The CRC flag at D is obtained (FIGS. 3A, B). On the other hand, in the lockout state, the CRCC code cannot be correctly decoded depending on the synchronizing signal CK, and therefore the CRC flag is not set in this case. Therefore, the lock-in state of the PLL circuit 20 can be determined by monitoring the CRC flag in the address section ADD.

The CRC flag is supplied to the switching pulse generation circuit 44. Although not shown, the generation circuit 44 is provided with a waveform shaper such as a mono multivibrator, and a CRC flag is supplied to the mono multivibrator. The pulse width of the mono multivibrator is CRC
Since it is set wider than the flag interval, CRC
By using the flag as a trigger pulse, the first pulse Pa shown in FIG. 3C is generated. The second pulse Pb is generated from the first pulse Pa (FIG. 3D).

The switching pulse SP of high level (FIG. 3E) can be always obtained while the second pulse Pb is obtained. Alternatively, as shown in FIG. 3F, only the VFO section of the address section ADD is obtained. It is also possible to configure so that the switching pulse SP having a high level can be obtained. The switch 39 is controlled by the switching pulse SP.

The CRC flag is also supplied to the reset pulse generating circuit 45, and the reset pulse RP (FIG. 3F) is generated when the CRC flag does not rise for a predetermined period. In this example, as the predetermined period, three flag periods are taken as shown in FIGS. 3B and 3G. This reset pulse RP
The reset switch 46 connected in parallel to the capacitor 41 is controlled by. The reset pulse RP closes the reset switch 46, and the capacitor 41 is reset (discharged).

When the control system for the PLL circuit 20 is configured in this way, the CRC flag is obtained in the steady state where the PLL circuit 20 is locked in, and the switching pulse SP shown in FIG. 3E or F is obtained. To be In the switching pulse SP of FIG. 3E, the switch 39 is always closed, and the switching pulse S of FIG.
When it is P, the switch 39 is closed only in the section where VFO is input in the reproduction signal RF. Then, the switch 46 is controlled to the open state.

As a result, the feedback loop for the limiter circuit 26 is closed, and the limiter level changes according to the level fed back by the buffer amplifier 40.
The limiter circuit 26 operates as a tracking limiter that follows the feedback level. The feedback level is stored in the capacitor 41.

Therefore, as shown in FIG. 4, when the frequency control voltage at a certain temperature (for example, room temperature) is the curve Lc, the upper limiter level LIM (+) is like the curve Lu obtained by translating the curve Lc to the upper side. become. Similarly, the lower limiter level LIM (−) becomes like a curve Ld obtained by moving the curve Lc in parallel. As a result, even if the frequency control voltage curve Lc fluctuates up and down due to temperature fluctuations of the variable oscillator 24, for example, the upper and lower limiter curves Lu and Ld move in parallel, so the PLL circuit 2
The zero operating region is not limited by temperature fluctuations.

Further, when the switching pulse SP shown in FIG. 3E is used, the discontinuous section of the signal input to the phase comparator 25 disappears, and the continuous wave signal EE shown in FIG.
Can be used for PLL stable operation, so that the PLL circuit 20 can be operated stably even if the VFO signal is an intermittent signal. Inserting continuous wave signal EE,
Since the waveform of the reproduced signal is not disturbed before and after the signal insertion section, and noise and error components are not mixed, PL
It contributes to the stabilization of L operation.

Further, if the rotation of the magneto-optical disk 1 has a jitter, the synchronizing signal CK is obtained by following the jitter, so that a discrimination output following the jitter can be obtained.

Next, when the PLL circuit 20 enters the lockout state, the CRC is generated almost at the same time when the lockout occurs.
Since the flag is no longer raised, the feedback loop is cut off by opening the switch 39, and the switch 46 is closed by the reset pulse RP, so that the capacitor 41 is immediately discharged and the output potential of the buffer amplifier 40 becomes a reference potential such as the ground potential.

As a result, the limiter circuit 26 becomes a fixed limiter level (shown by the broken line in FIG. 4), and the variable oscillator 24
The oscillation frequency of does not shift significantly from the value immediately before lockout. As a result, the lock-in is facilitated and the lock-in time is shortened, so that the stability of the operation can be secured.

In the above description, the PLL circuit provided in the recording / reproducing apparatus of the magneto-optical disk and the data reproducing apparatus thereof are applied as one embodiment of the present invention. However, in addition to this, a PLL circuit for extracting various clocks and It is obvious that it can be applied to a data reproducing device using it.

[0042]

As described above, according to the present invention, the phase
When the locked loop is locked in, the feedback loop provided to the limiter circuit operates as a tracking limiter circuit.When the phase locked loop is locked out, the feedback loop provided to the limiter circuit is released. It is designed to operate as a fixed limiter circuit.

According to this, even if the frequency of the variable oscillator fluctuates due to the temperature characteristics of the variable oscillator or the like, it is operated as the timing limiter, so that the operation pull-in range is not narrowed, and the operation region is reduced. It can be wider than before. Also, even when locked out, the limiter circuit is controlled so as to have a fixed limiter level, so that even if locked out, it becomes possible to immediately lock in. As a result, the lock-in time becomes faster.

Even when the reproduced signal is an intermittent signal, a continuous wave signal is inserted so that a discontinuous section is not generated. Therefore, the waveform distortion and noise generated before and after the discontinuous section are mixed into the phase locked loop. It is possible to eliminate the disturbance of the operation. This has a feature that the stability of the operation can be further ensured. Therefore, the present invention is extremely suitable when applied to a data recording / reproducing apparatus such as a magneto-optical disk which handles an intermittent signal.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment in which a data reproducing apparatus to which a phase locked loop circuit according to the present invention is applied is applied to a magneto-optical disk recording / reproducing apparatus.

FIG. 2 is an explanatory diagram of operations related to continuous wave signal insertion.

FIG. 3 is an explanatory diagram of operations related to CRC flag detection.

FIG. 4 is an explanatory diagram of a tracking limiter operation.

FIG. 5 is a diagram showing an example of a recording format of a magneto-optical disk.

FIG. 6 is a system diagram of a data reproducing apparatus using a conventional phase locked loop circuit.

FIG. 7 is an explanatory diagram of a fixed limiter operation.

[Explanation of symbols]

 10 Data Reproducing Device 11 Optical Pickup Means 16 Waveform Equalizer 18 Waveform Shaper 20 PLL Circuit 22 Discrimination Circuit 24 Variable Oscillator 25 Phase Comparator 26 Limiter Circuit 37, 38 Limiter Diode 40 Buffer Amplifier 39, 46 Switch 43 CRC Detection Means 44 switching pulse generation circuit 45 reset pulse generation circuit

Claims (4)

[Claims] 1. A variable oscillator, and a phase comparator for comparing the phase of the oscillation output with the phase of an input signal, the phase comparison output of the phase comparator being fed to the variable oscillator through an amplifier having a low-pass filter. In a phase locked loop circuit that is supplied as an error detection voltage, in order to provide the limiter circuit provided in the output stage of the phase comparator and the output of the amplifier for the limiter level control of the limiter circuit. Feedback loop and a tracking capacitor connected to this feedback loop.When the phase locked loop is locked in, it operates as a tracking limiter circuit by the feedback loop given to the limiter circuit. , If the phase locked loop is locked out, the limit The phase-locked loop circuit is characterized in that the feedback loop given to the reset circuit is opened to operate as a fixed limiter circuit. 2. The phase locked loop circuit according to claim 1, wherein the electric charge of the capacitor is reset during the lockout. 3. A phase-locked loop circuit for generating a clock based on input data, a latch circuit for data discrimination which is supplied with the input data and latched by the clock, and a phase-locked loop from a latch output. A lock detector that detects a lock-in state of the loop circuit, wherein the phase-locked loop circuit includes a variable oscillator, a phase comparator that compares the phase of the oscillation output with the input signal, and the phase of the phase comparator. An amplifier having a low-pass filter whose comparison output is supplied as an error detection voltage to the variable oscillator, a limiter circuit provided in the output stage of the phase comparator, and an output of the amplifier to the limiter circuit. A feedback loop for giving as a level control and a transformer connected to this feedback loop. It has a king capacitor and when the phase locked loop is locked in, it operates as a tracking limiter circuit by the feedback loop given to the limiter circuit, and the phase locked loop locks out. The data reproducing apparatus is characterized in that the feedback loop applied to the limiter circuit is opened when the limiter circuit is in operation to operate as a fixed limiter circuit. 4. The data reproducing apparatus according to claim 3, wherein the lock detecting means is means for detecting an error correction code, and the lock-in state is detected by the presence or absence of a CRC flag. .