JPS5950638A - Clock signal producing circuit for self-synchronism - Google Patents

Abstract

PURPOSE:To attain the reproduction of a stable self-synchronizing clock signal, by comparing a self-synchronism clock component extracted by a resonance circuit and the phase of an output signal of a variable frequency oscillator to control the oscillating frequency. CONSTITUTION:A self-synchronism clock signal producing circuit 50 comprising a preamplifier 30, a waveform equalizer 31, a data extracting circuit 32, a both- edge differentiating circuit 33, a tuning circuit 34, a waveform shaping circuit 35, a phase synchronism circuit 36, and a maximum inverting interval detecting circuit 42 overcomes a defect of a phase locked loop circuit for jitter adsorption of a conventional circuit impossible for synchronism against an input transmission frequency fluctuation. Since the oscillated frequency follows up an input transmission frequency fluctuation, the self-synchronism clock signal is used as a rotation control signal of a rotating system, for example, thus obtaining excellent results.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a self-synchronizing clock signal generation circuit that generates a clock signal from a PCM (pulse code modulation) signal reproduced from a recording medium, for example.

[Technical background of the invention and its problems]

2. Description of the Related Art Recently, with the development of PCM (Pulse Code Modulation) technology, various PCM tape recorders and devices for playing digital audio discs recording PCM signals have been provided.

In this type of PCM device, the self-synchronizing clock signal, which serves as a reference for various operations, is generated based on a predetermined frequency component of a PCM signal reproduced from a recording medium such as a magnetic tape or disk, and is particularly stable. It is hoped that it will be obtained.

For example, as shown in Figure 1, a self-synchronizing clock signal generation circuit in a playback system of a PCM device detects a signal recorded on a magnetic tape, digital audio disk, etc. by a magnetic head or an optical pickup. This signal SHF becomes an input to the IJ transmitter amplifier 11 via the terminal IN. The limiter amplifier 11 has signal outputs "HF1" HIJk with opposite phases to each other,
Each of these outputs is applied to a half-wave rectifier circuit 12.13.

The rectified outputs SR1 and SR2 are added in the summing amplifier 14 to create a signal "'ADD" having a clock signal component.The 5 ADD signal undergoes waveform shaping in the limiter amplifier 15.The output SLMT total clock of the limiter amplifier 15 A repetition frequency component ST is obtained by applying the signal to a resonant circuit 16 that is adjusted to approximately match the signal frequency.The resonant circuit output ST is in the form of a damped sine wave, and its level is equal to the input signal to the resonant circuit 16. Since it depends on the /4' turn of the SLMT, it is further compressed to a certain level by the limiter amplifier 17 and waveform shaped to obtain the clock signal ScK.The extracted clock signal S.K is due to the speed fluctuation between the recording medium and the pickup. This includes transmission frequency fluctuations and bit-by-bit frequency fluctuations.In order to completely absorb the bit-by-bit frequency fluctuations among the frequency fluctuations mentioned above, and to obtain a synchronizing clock signal 5PLcK that follows only the transmission frequency fluctuations, phase synchronization for jitter absorption is performed. The extracted clock signal S c x is input to the circuit 18. The phase synchronization circuit 1
8 is a phase comparator 19, a loop filter 20, a voltage variable frequency oscillator (hereinafter referred to as VCO) 2, and a frequency divider 2.
It consists of 2 parts. The output signal 5HF1 of the limiter amplifier 11 is input to a timing identification circuit 23, and the timing identification circuit 23 identifies high-level and low-level timing based on the output signal PLCK of the phase synchronization circuit 18. performed output signal S
Dk er. As mentioned above, the Q of the resonant circuit 16, which is an important circuit in this self-synchronization clock signal generation circuit, needs to be set high to a certain extent to avoid noise and noise.
is affected by jitter due to the input pulse pattern. Furthermore, it is better to have a high Q in order to continue extracting the synchronization timing signal even in the event of a certain length of dropout (missing of the reproduced signal due to damage to the recording medium, etc.). (Usually, the value of Q is set to 100 to 200.) However, if the Qt of the resonant circuit 16 is set high, a self-synchronization clock signal component with a stable amplitude can be extracted against large fluctuations in the transmission frequency. If this is difficult or impossible, the operation of the phase locking circuit 18 for absorbing jitter may also be malfunctioning.
It has the disadvantage that stable self-synchronization clock signals cannot be generated. In this case, the timing of the high level and low level of the input data may be incorrectly identified, and the error may not be correctable. In particular, when the circuit shown in Figure 1 is used in a PCM device that has a rotating system for driving magnetic tapes or disks, the frequency range that can be synchronized is narrow, so fluctuations in the rotational speed must be kept very small. requires strict mechanical precision and rotation control ability, and requires an expensive PC.
It becomes M device.

In addition, Fig. 2 (,) to (h) represent each of the above-mentioned signals 5, respectively.
− This shows an example of a change in the number.

Further, the resonant circuit 16 includes, for example, a transistor Qllll Q10 and an inductor Lll as shown in FIG.
-Li2, capacitor 1" C16, resistor R1
11R1z'l: Consisting of:

[Purpose of the invention]

The present invention has been made in view of the above points, and even if the transmission frequency of a signal including a digital data signal from which a large number of self-synchronizing clock signal components are to be extracted varies, the self-synchronizing clock signal component can be extremely stably generated. An object of the present invention is to provide a complete self-synchronization clock signal generation circuit that generates a good self-synchronization clock signal.

[Summary of the Invention] The present invention performs binary level identification of a signal including a digital data signal from which a self-synchronization clock signal component is to be extracted, and performs binary level identification of a signal high level, high level, high level, high level, high level, high level, high level, high level, high level, low level, high level, low level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, low level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, high level, and high level of a signal containing a digital data signal from which a clock signal component for self-synchronization is to be extracted. means for outputting a detection pulse of a rising edge and a falling edge of the extracted digital data signal; and a resonant circuit for extracting a clock signal component for self-synchronization from the detected/4' pulse. , a phase comparator compares the phases of the self-synchronizing clock signal component extracted by the resonant circuit and the output signal of the variable frequency oscillator, and changes the oscillation frequency of the variable frequency oscillator based on the comparison output of the phase comparator. A self-synchronizing clock signal generation circuit comprising a phase-locked circuit for controlling a phase synchronization circuit, characterized in that the self-synchronization clock signal generation circuit includes means for changing the resonant frequency of the resonant circuit in accordance with the output signal of the phase comparator. It is something to do.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the drawings.

That is, as shown in Fig. 4, a PGM signal recorded on a recording medium such as a magnetic tape or a digital audio disk by performing digital modulation using a clock-reproducible digital modulation method is processed by a magnetic head or an optical pickup to reduce the code amount. A distorted reproduced signal S n F containing interference, jitter, noise, etc. is obtained. This reproduction signal S
□2 is amplified by the preamplifier 30 and is the amplified output signal SA
is added to the waveform equalizer 31 to correct waveform distortion that occurs during the process of reproducing a digital signal recorded on a recording medium.

Output S8 of the waveform equalizer 31. The data extracting circuit 32 identifies the high level and low level binary signal amplitude, and the rectangular wave signal sequence S is obtained. M. A of the above rectangular wave signal train ScMP?
Since the worth vector does not have a spectrum of the clock signal frequency (equal to the bit rate) when digital modulation is performed, it is necessary to create the frequency component by nonlinear operation.

In the circuit shown in Figure 1, a signal "'LMT (signal S
In this embodiment, a pulse train indicating a polarity change point of nF 1 or S a P 1 is obtained. In this embodiment, for example, the pulse train is composed of an exclusive OR circuit 7o shown in FIG. 5 and a plurality of delay inverters 71. The pulse train signals SD, fr, which are similar to the front distribution signal "LMT" are generated by the double edge differentiating circuit 33.Therefore, this pulse train signal 5DxF is designed to include the frequency spectrum of the clock signal for digital modulation. become.

In other words, the output signal ScM of the data extraction circuit 31
P is applied directly to one input terminal of the exclusive OR circuit 70, and is also applied to the other input terminal of the exclusive OR circuit 70 via a plurality of inverters 71 to generate the pulse train signal SD.

This is what you get.

The pulse train signal 5DIF containing the frequency spectrum of the clock signal during digital modulation is applied to a tuning circuit 34 consisting of an inductance and capacitor parallel circuit in order to extract continuous self-synchronizing clock signal waves. If a component corresponding to the tuning frequency of the tuning circuit 34 exists in the pulse train signal "DIF," a damped oscillation waveform corresponding to the pulse train pattern as shown in FIG. 6, for example, can be obtained as the output signal 8'T. Tuning circuit 9-34 A part of the parallel resonance capacitor is replaced with a voltage variable capacitance diode, and it is a voltage control tuning circuit in which the tuning frequency changes depending on the DC voltage for controlling the voltage variable capacitance diode. .

As shown in FIG. 7, the tuning circuit 34 includes an inductor L1% capacitor C2, and a voltage variable capacitance diode D! The parallel resonant circuit consisting of the transistor Ql
, the output signal of the transistor Ql is connected to the resistor R
After passing through 1, FF, T (field effect transistor) Q
2 and a resistor R2. In addition, resistance R3+ R
4. A circuit such as capacitor C3 is used to apply a control voltage to the voltage variable capacitance diode Dl.

The resistor R3 suppresses high frequency noise contained in the control voltage of the clocker of the tuning circuit 34. Therefore, the inductance 10-tance of the inductor L1, the capacitance of the capacitor itself including the stray capacitance of the circuit, and the capacitance of each capacitor C2 and C3 are indicated by their respective symbols, and the capacitance of the voltage variable capacitance diode is If the capacitance is Cr, the resonance frequency Fo of the tuning circuit 33 is given by:

The extracted signal ST of the resonant circuit 34 is the waveform shaping circuit 3
5, its amplitude is compressed, and it is converted into a rectangular wave extracted clock signal S'cK. The extracted clock signal SCK converted into a rectangular wave by the waveform shaping circuit 35 is supplied to a phase synchronization circuit 36 (described later) for jitter absorption, which absorbs fluctuation jitter in the time axis direction.
A stable self-synchronization clock signal “”PL
It is now possible to get a CK. The phase synchronization circuit 36 has the function of absorbing jitter and generating a control voltage for fully controlling the resonant frequency of the tuning circuit 34. a frequency divider 38, an output signal S'PLCK of the frequency divider 38, and an output S'PLCK of the waveform shaping circuit 35.
'CK and a phase frequency comparator 39 that detects the phase difference and frequency difference, and a voltage variable frequency oscillator 3 that attenuates harmonic components included in the output of the phase frequency comparator 39.
7, a loop filter 40 for generating a control voltage for the tuning circuit 34, and a buffer amplifier 41 for completely preventing the tuning circuit 34 and the voltage variable frequency oscillator 37 from interfering with each other via the control voltage VC. It has become so. The phase difference detection characteristic of the phase frequency comparator 39 is as shown in FIG. Output voltage V of the loop filter 40
As shown in FIG. 9, the LPF adjusts the frequency f so that when the output signal S'cK frequency f of the waveform shaping circuit 35 becomes ft - fo and fl, the frequency f changes to Vcl, vco, and Vc2 correspondingly.
It seems to have characteristics proportional to . The voltage VL
PP, all PP. By providing a control voltage for varying the resonant frequency of the input digital data signal S
The tuning characteristic can be varied as shown in FIG. 10 depending on each state where the HF transmission frequency f is L tfo +f2. The tuning circuit 34 outputs a self-synchronization clock signal "'PLCK" having a regular frequency fo through the buffer amplifier 41 of the jitter absorption phase synchronization circuit 36 in a synchronized state.
Adjustment is made in advance so that it resonates at the frequency fo.

In this way, the output signal S'cK of the waveform shaping circuit 35
The reason why the control voltage of the voltage variable capacitance diode D1 is changed according to the frequency f is that from the well-known relationship between the control voltage and the capacitance of the voltage variable capacitance diode, when the frequency f is lower than the normal state, the control voltage is changed. When the frequency f is higher than normal, the control voltage is increased to lower the resonant frequency of the tuning circuits 13-34. Therefore, even if the transmission frequency of the input signal S'HF of the preamplifier 30 fluctuates, even if the Q of the tuning circuit 34 is high, the tuning circuit 3
The amplitude of the signal ST extracted in step 4 is always extracted to be substantially constant, and fluctuations in the timing of operation (that is, the opposite phase) in the waveform shaping circuit 35 can be reduced.

Further, if the signal S'HF is continuously supplied to the preamplifier 30, the extracted signal S'T of the tuning circuit 34 is continuously taken out and passed through the waveform shaping circuit 35 for self-synchronization. Signal S that is the source of the clock signal. This is derived as K.

As a result, the self-synchronizing clock signal "PLCKk" can be stably obtained from the frequency divider 38 without being affected by fluctuations in the transmission frequency of the signal SHp.

On the other hand, when the input signal of the preamplifier 30, which is the input signal of the self-synchronization clock generation circuit, is S'HF stopped, the input signal S'( HK stops.At this time, since an unnecessary signal is output from the phase/frequency comparison, the output voltage of the loop filter 40 becomes unstable (in this case, the loop filter 40 has a voltage of V or V.1). However, when the input signal S')!F is stopped, the state in which the input signal S')!F is stopped is undefined, so the resonant frequency of the tuning circuit 34 is also undefined. When the input signal S'n F is applied in such a state, the above-mentioned tuned circuit is in an untuned state, so the continuous wave S'T of the self-synchronizing clock signal component is
It becomes difficult to extract.

Therefore, the synchronization pull-in operation of the jitter absorption phase synchronization circuit 36 is difficult, and the normal self-synchronization clock signal S'c
K'! I can't get it.

For this reason, if the signal S'HF is input without falling into the above state, in order to cause the jitter absorption phase synchronization circuit 36 to perform the synchronization pull-in operation quickly and stably, the input signal "IP" is input. The maximum inversion interval detection circuit 42 detects and measures the maximum inversion interval and generates the DC voltage vTMAX corresponding to the transmission frequency, and the output vTMAX of the maximum inversion interval detection circuit 42 and the loop filter 40 in the phase synchronization circuit 36 for absorbing jitter are detected and measured. Output voltage vLP F
The output vc of the buffer amplifier 41 and the switch circuit 43
You can switch by using . The above switch circuit 43
The switching is performed using the output signal S' of the data extracting circuit 32.
cMP is input to the timing identification circuit 44, and from among the data signals SD whose timing is identified by the reproduced self-synchronization clock signal ""1' LCK, a specific data pattern (normal synchronization) pattern is called as a data signal SD. This is performed by a signal SLD outputted from a synchronous four-turn detection circuit 45 which detects a control timing signal 88YNc (periodically inserted into the pattern) and generates a control timing signal 88YNc synchronized with the above pattern. The data signal ST3 is supplied via the terminal 0UTD to a demodulation circuit that demodulates the digital modulation signal.

As shown in FIG. 4, the preamplifier 301 waveform equalizer 3, data extraction circuit 32, both edge differentiating circuit 33, tuning circuit 34, waveform shaping circuit 35, phase synchronization circuit 36, maximum inversion interval detection The self-synchronization clock signal generation circuit 50, which is composed of the circuit 42, is configured to handle the problem that the phase synchronization circuit 36 for jitter absorption cannot synchronize with the transmission frequency fluctuation of the input signal "HP" seen in the circuit of FIG. It overcomes the drawbacks and is particularly suitable for the playback system of a PCM device equipped with a rotating system such as a capstan for running a magnetic tape or a rotational drive mechanism for a digital audio disk, and is suitable for the reproduction system of a PCM device that is capable of handling fluctuations in the transmission frequency of the input signal S'Hy. Therefore, the self-synchronization clock signal 5PLcK can be used as a rotation control signal for a rotation system, for example, which is very convenient.

The control timing signal S8ANC appropriately supplies a master signal of various control signals necessary for demodulating the preamplifier 300 Å power signal S'HF to each part of the PCM device via the terminal OUTM. It is something.

Furthermore, the synchronization/four-turn detection circuit 45 actually has a counter 17 for counting the number of times the control timing signal "BYNO" is not synchronized by the synchronization/nine-turn detection signal. If the synchronization is not performed N times, the instruction signal 5LDf is output.If the self-synchronization clock regeneration circuit 36 is not in a synchronized state, the instruction signal S L o is output, and during this period, the changeover switch circuit 43 is While the changeover switch circuit 43 is closed to the contact ■ side, the tuning circuit 34 outputs the output vTMAX of the maximum reversal interval detection circuit 42.
The resonant frequency is controlled according to the transmission speed of the input signal S, etc. Next, the jitter absorption phase synchronization circuit 36 enters the synchronized state, and when the control timing signal "8YN(!") is not synchronized consecutively less than N times, the instruction signal S
LD is not output, and the changeover switch circuit 43 is a contact point ■
It begins to close to the side. As a result, the resonant frequency of the tuning circuit 34 is controlled by the output vc from the jitter absorption phase-locked circuit 36, and the jitter absorption phase-locked circuit 36 changes the transmission frequency of the input signal S'H1p while maintaining synchronization. Self-synchronization clock signal S'PLc with a frequency corresponding to
There are 18 types that operate to reproduce K.

FIG. 11 shows the configuration of the maximum inversion interval detection circuit 42, in which a timing generator 60. 12th
The signal S shown in the figure. M.

Period when the signal is at high level TMl' 7M217
M3: Pulse width measurement circuit 61 that measures with the full clock signal S'CLK, peak hold circuit 62 that holds all the peak values of the pulse width, newly measured pulse width value and holds it in the peak hold circuit 62. If the pulse width value is larger than the value held in the peak hold circuit 62, a signal is generated to allow the new measured value to be stored in the peak hold circuit 62. A latch circuit 65 for latching the contents of the digital comparator 63 and the peak hold circuit 62 for each signal output from the maximum inversion interval detection period counting circuit 64
and a digital/analog conversion circuit 6 consisting of a resistor network that converts the contents of the latch circuit into a DC voltage vTMAX.
It is made up of 6 different types. The clear signal of the pulse width measuring circuit 61, the memory signal of the peak hold circuit 62, and the clear signal of the maximum inversion interval detection period counting circuit 64 are supplied by the timing generator 60. The maximum reversal interval detection period is obtained by counting the falling edge of SCMP M times.

The maximum inversion interval detection circuit 42 in FIG. 4 uses a clock signal S for measuring the pulse width. LK is provided by the master clock generator 46 of the PCM device.

It goes without saying that this invention is not limited to the above-mentioned embodiments only, and that various modifications and applications are possible without departing from the gist of the invention.

〔Effect of the invention〕

As detailed above, according to the present invention, an extremely stable self-synchronizing clock signal can be generated even if the transmission frequency of the signal containing the digital data signal from which the self-synchronizing clock signal component is to be extracted fluctuates. Thus, it is possible to provide an excellent self-synchronization clock signal generation circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a conventional self-synchronization clock generation circuit, and Figs.
3 is a circuit connection diagram showing a complete summary of the resonant circuit of the circuit in FIG. 1, and FIG. 4 is an embodiment of the self-synchronization clock signal generation circuit according to the present invention. 5 is a circuit connection diagram showing the configuration of the double edge differentiator shown in FIG. 4, FIG. 6 is a diagram showing the output characteristics of the tuning circuit shown in FIG. 4, and FIG. A circuit connection diagram showing the circuit configuration, Fig. 8 is a diagram showing the input/output characteristics of the phase frequency comparator of the circuit in Fig. 4, and Fig. 9 shows the loop filter output for the waveform shaping circuit output of the circuit in Fig. 4. diagram showing,
10 is a diagram used to explain the operation of the phase locked circuit in FIG. 4, FIG. 11 is a block diagram showing the configuration of the maximum inversion interval detection circuit in FIG. FIG. 3 is a diagram used to explain the operation of the circuit. 21- 30... Preamplifier, 31... Waveform equalizer, 32...
...De-evening circuit, 33...Both edge differentiating circuit, 34...Tuning circuit, 35...Waveform shaping circuit, 3
6... Phase synchronized circuit, 37... Voltage variable frequency oscillator, 38... Frequency divider, 39... Phase frequency comparator,
40... Loop filter, 41... Buffer amplifier, 42... Maximum inversion interval detection circuit, 43... Switch circuit, 44... Timing identification circuit, 45... Synchronization pattern detection circuit, 46. ... Master clock generator, 50 ... Self-synchronization clock signal generation circuit, 60.
...Timing generator, 6I...Pulse width measurement circuit,
62...Peak hold circuit, 63...Digital comparator, 64...Maximum inversion interval detection period counting circuit, 65
...Latch circuit, 66...Digital/analog conversion circuit. Applicant's representative Patent attorney Takehiko Suzue 22- 5 Figure 33 Figure 6 Figure 7 Figure 8 Figure 1-2r, 0 27C4

Claims (1)

[Claims] Means for performing binary level identification of a low level and a low level from a signal including a digital data signal from which a self-synchronization clock signal component is to be extracted, and extracting the digital data signal; a resonant circuit for extracting a self-synchronization clock signal component from the detection pulse; and a resonant circuit for extracting a self-synchronization clock signal component from the detection pulse; a phase synchronization circuit that compares the phase of the clock signal component for the oscillator and the output signal of the variable frequency oscillator with a phase comparator, and controls the oscillation frequency variation of the variable frequency oscillator according to the comparison output of the phase comparator. 1. A self-synchronizing clock signal generating circuit characterized in that the self-synchronizing clock signal generating circuit comprises means for changing the resonant frequency of the resonant circuit according to the output signal of the phase comparator.