JP2007288540A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a capture range comes out of upper/lower limit values to cause an unlocked state according to frequency deviation of an input signal and fluctuation in component characteristics because the upper limit value and the lower limit value of a lock determination circuit are fixed, which determines whether a PLL circuit is locked by comparing an output of a loop filter with the upper limit value and the lower limit value. <P>SOLUTION: An upper limit value/lower limit value detection circuit detects and stores the upper limit value and the lower limit value of an output of the loop filter when the PLL circuit is locked, the stored upper/lower limit values are input to a limit circuit, and the limit circuit regulates the output of the loop filter to a value between the upper/lower limit values. Since output voltage of the loop filter is always regulated within the capture range, the PLL circuit can surely be locked regardless of the frequency deviation of the input signal and the fluctuation in the component characteristics. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a PLL (Phase Lock Loop) circuit used for a signal generator or the like, and more particularly to a PLL circuit that can be reliably locked even if a capture range changes due to individual variation or temperature fluctuation.

  FIG. 6 shows the configuration of a conventional PLL circuit. In FIG. 6, the output of the oscillation circuit 10 that outputs a triangular wave having a long period is input to the adder circuit 12 via the switch 11. An input signal that is a periodic signal and an output of a voltage controlled oscillator (VCO) 16 described later are input to the sampler 13. The sampler 13 outputs a signal representing the difference between the frequency of the voltage controlled oscillator 16 output and the input signal to the adder circuit 12. The adder circuit 12 adds the two input signals and outputs the result to the loop filter 14.

  The loop filter 14 has a configuration in which a series circuit of a resistor R1 and a capacitor C1 is connected to the feedback side of the amplifier OP1, and a series circuit of a resistor R2 and a switch 14a is connected in parallel to the series circuit (resistor R1, capacitor C1). The filter characteristics can be varied by operating the switch 14a.

  The loop filter 14 filters the input output of the adder circuit 12 and outputs a Vtune voltage. The Vtune voltage is input to the limit circuit 15, the voltage controlled oscillator (VCO) 16, and the lock determination circuit 17. The output of the voltage controlled oscillator 16 is output to the outside and input to the sampler 13.

  The limit circuit 15 includes an upper limit 15a and a lower limit 15b, and protects the Vtune voltage so that it falls within the standard range of the voltage controlled oscillator 16. The lock determination circuit 17 includes two comparators to which an upper limit value and a lower limit value are input, and determines whether or not the Vtune voltage is between the upper limit value and the lower limit value.

  The output of the sampler 13 is input to the lock determination circuit 18. The lock determination circuit 18 counts the output of the sampler 13 and determines whether it is in the capture range. The outputs of the lock determination circuits 17 and 18 are input to the logic circuit 19. ON / OFF of the switches 11 and 14a is controlled by the output of the logic circuit 19.

  Next, the operation of this PLL circuit will be described. Initially switches 11 and 14a are on. Of the output of the adder circuit 12, the output component of the oscillation circuit 10 is hardly attenuated by the loop filter 14. On the other hand, the output component of the sampler 13 is cut from the high frequency component, and only the offset voltage passes through the loop filter 14. However, since the offset voltage is very small, the component of the oscillation circuit 10 becomes dominant. For this reason, the Vtune voltage slowly changes between the upper limit and the lower limit, which are regulated by the limit circuit 15.

  When the Vtune voltage enters the capture range, the outputs of the lock determination circuits 17 and 18 are inverted. Therefore, the output of the logic circuit 19 is also inverted, and the switches 11 and 14a are turned off. The oscillation circuit 10 and the resistor R2 are disconnected, and the PLL circuit is locked.

  FIG. 7 shows the relationship between the upper and lower limits of the limit circuit 15, the upper and lower limits of the lock determination circuit 17, and the capture range. The range of the upper and lower limit is the widest, the range of the upper and lower limit value is in this range, and the capture range exists in the range of the upper and lower limit value.

JP 2001-94415 A

  However, such a PLL circuit has the following problems. In this PLL circuit, the upper limit value and the lower limit value of the lock determination circuit 17 are fixed. Therefore, the capture range is in the range of the upper and lower limit values due to individual variations in the control voltage of the voltage controlled oscillator 16, shifts in the frequency of the input signal, or changes in characteristics due to changes in the ambient temperature of the components constituting this PLL circuit. There was a problem that it would be impossible to lock if exceeded.

  Accordingly, an object of the present invention is to provide a PLL circuit that can be surely locked even if the capture range changes due to variations in voltage controlled oscillators, shifts in input frequency, changes in ambient temperature, and the like.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a PLL circuit that forms a closed loop with a sampler, an adder circuit, a loop filter and a voltage controlled oscillator to which a periodic signal is input, and generates a signal with a predetermined period,
An oscillation circuit that outputs a signal having a period longer than the period of the periodic signal;
A first switch for inputting and disconnecting the output of the oscillation circuit to the adding circuit;
A second switch that disconnects a portion of the closed loop to make it open loop;
A lock determination circuit for determining whether or not the output of the sampler is input and locked;
An output of the loop filter and an output of the lock determination circuit are inputted, and an upper limit value / lower limit value detection circuit for detecting and holding the upper limit value and lower limit value of the capture range and outputting the held upper limit value and lower limit value When,
A limit circuit that receives an output of the upper limit value / lower limit value detection circuit and regulates an output of the loop filter between an upper limit value and a lower limit value detected by the upper limit value / lower limit value detection circuit;
Is provided. Even if there is a deviation in the frequency of the input signal or a variation in the component characteristics, it can be locked securely.

The invention according to claim 2
In a PLL circuit that forms a closed loop with a sampler, an adder circuit, a loop filter and a voltage controlled oscillator to which a periodic signal is input, and generates a signal with a predetermined period,
An oscillation circuit that outputs a signal having a period longer than the period of the periodic signal;
A first switch for inputting and disconnecting the output of the oscillation circuit to the adding circuit;
A second switch that disconnects a portion of the closed loop to make it open loop;
A lock determination circuit for determining whether or not the output of the sampler is input and locked;
An output of the loop filter and an output of the lock determination circuit are inputted, and an upper limit value / lower limit value detection circuit for detecting and holding the upper limit value and lower limit value of the capture range and outputting the held upper limit value and lower limit value When,
The output of the loop filter is input, and the output voltage of the loop filter at the time of locking is detected and held, and the voltage detection circuit at the time of locking that outputs the held voltage;
The outputs of the upper limit value / lower limit value detection circuit and the lock time voltage detection circuit are input, the output of the lock time voltage detection circuit and the average value of the upper limit value and the lower limit value output by the upper limit value / lower limit value detection circuit An arithmetic unit that adds the difference between the upper limit value and the lower limit value and outputs the difference,
A limit circuit that receives the output of the calculation unit and regulates the output of the loop filter between the outputs of the calculation unit;
Is provided. Even if the frequency of the input signal shifts or the ambient temperature changes, it can be reliably locked.

The invention according to claim 3 is the invention according to claim 1 or claim 2,
The first switch and the second switch are controlled in opposite directions. Switch control is simplified.

The invention according to claim 4 is the invention according to any one of claims 1 to 3,
The first switch is controlled by the output of the lock determination circuit, and the output of the lock determination circuit is input to the first switch, and a third switch for disconnecting is provided. Switch control is simplified.

The invention according to claim 5 is the invention according to any one of claims 1 to 4,
The upper limit / lower limit detection circuit includes a sample hold circuit that holds the output of the loop filter according to an output of the lock determination circuit, an AD converter that converts an analog voltage held by the sample hold circuit into a digital value, and This is composed of a register for holding a digital value converted by the AD converter. The structure is simple and can be held securely.

As is apparent from the above description, the present invention has the following effects.
According to the first, second, third, fourth, and fifth inventions, the upper limit value and the lower limit value of the output of the loop filter when locked are detected and held by the upper limit value / lower limit value detection circuit. The lower limit value is input to the limit circuit, and the output of the loop filter is regulated to a value between the upper and lower limit values by this limit circuit.

  Since the output of the loop filter is regulated within the capture range by the limit circuit, there is an effect that the PLL circuit can be locked without fail regardless of the frequency shift of the input signal or the variation among the individual voltage controlled oscillators. .

  Further, by correcting the output of the upper limit / lower limit detection circuit with the output of the loop filter when locked, the PLL circuit can be reliably locked even if the ambient temperature changes and the component characteristics fluctuate. There is also an effect that can be done.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention. In addition, the same code | symbol is attached | subjected to the same element as FIG. 6, and description is abbreviate | omitted. In FIG. 1, reference numeral 20 denotes a switch, which inputs and disconnects the output of the sampler 13 to the adder circuit 12.

  A limit circuit 21 is composed of an upper limit 21a and a lower limit 21b as in the limit circuit 15, and regulates the output (Vtune voltage) of the loop filter 14 so as to fall between the upper limit 21a and the lower limit 21b. . Values of the upper limit 21 a and the lower limit 21 b in the limit circuit 21 are set by the D / A converter 22.

  Reference numeral 23 denotes an upper limit / lower limit detection circuit which receives the Vtune voltage and the output of the lock determination circuit 18 and detects and holds the upper limit voltage and the lower limit voltage of the capture range. A switch 24 inputs the Vtune voltage to the upper limit / lower limit detection circuit 23 and disconnects it. The output of the upper limit / lower limit detection circuit 23 is input to the D / A converter 22. The D / A converter 22 converts the output of the upper limit / lower limit detection circuit 23 into an analog signal and sets the upper limit 21 a and the lower limit 21 b of the limit circuit 21. A switch 25 is used to input and disconnect the output of the lock determination circuit 18 as a control signal for the switches 11 and 14a. A switch control unit 26 controls the switches 20, 24, and 25.

  Next, the operation of this embodiment will be described. The SW control unit 26 turns off the switches 20 and 25 and turns on the switch 24 when the power is turned on or periodically. The loop composed of the sampler 13, the adder circuit 12, the loop filter 14, and the voltage controlled oscillator 16 is cut and becomes an open loop. Further, the Vtune voltage is input to the upper limit / lower limit detection circuit 23. Further, the control signals are not input to the switches 11 and 14a and are turned on. The switches 11 and 14a must be turned on during this period. However, since these switches are driven by the output of the lock determination circuit 18, the switch 25 is turned off and disconnected from the output of the lock determination circuit 18, and the on state is set. maintain.

  Since the switches 11 and 14a are turned on, the Vtune voltage slowly rises and falls according to the output of the oscillation circuit 10 as in the conventional example of FIG. The upper limit / lower limit detection circuit 23 detects and holds the upper limit value and lower limit value of the capture range based on the output of the lock determination circuit 18 and outputs the detected value to the D / A converter 22. The D / A converter 22 converts the inputted upper and lower limit values into analog signals, and outputs the upper limit value to the upper limit limit 21a and the lower limit value to the lower limit limit 21b as set values.

  As shown in FIG. 2, the output of the lock determination circuit 18 outputs a signal that rises at the lower limit of the capture range and falls at the upper limit. Therefore, the upper limit / lower limit detection circuit 23 holds the Vtune voltage when the output of the lock determination circuit 18 rises as the lower limit, and holds the output when the output of the lock determination circuit 18 falls as the upper limit. do it.

  FIG. 3 shows an example of the configuration of the upper limit / lower limit detection circuit 23. In FIG. 3, reference numerals 30 and 31 denote sample and hold circuits, which receive a Vtune voltage and sample the Vtune voltage in synchronization with the rising edge of the sampling signal. The sample hold circuit 30 receives the output of the lock determination circuit 18 as a sampling signal, and the sample hold circuit 31 receives the output of the lock determination circuit 18 via an inverter 32.

  For this reason, the sample hold circuit 30 holds the Vtune voltage at the rise of the lock determination circuit 18, that is, the lower limit value of the capture range. The held Vtune voltage is converted into a digital value by the AD converter 33, and this digital value is stored in the register 35. Similarly, the sample hold circuit 31 holds the Vtune voltage at the fall of the lock determination circuit 18, that is, the upper limit value of the capture range. The held Vtune voltage is converted into a digital value by the AD converter 34, and this digital value is stored in the register 36. The values stored in the registers 35 and 36 are output to the D / A converter 22.

  Note that a D / A converter may be connected after the registers 35 and 36, and the values stored in the registers 35 and 36 may be converted into analog signals and output. That is, the D / A converter 22 may be built in the upper limit / lower limit detection circuit 23.

  After the upper limit / lower limit detection circuit 23 detects the upper limit and the lower limit, the SW control unit 26 sets the switches 20 and 25 on and the switch 24 off. The loop composed of the sampler 13, the adder circuit 12, the loop filter 14, and the voltage controlled oscillator 16 is closed. Further, since the switch 25 is turned on, the switches 11 and 14 a are controlled by the output of the lock determination circuit 18. Since the Vtune voltage is regulated within the capture range by the limit circuit 21, this PLL circuit maintains the locked state regardless of the change in the component characteristics due to the shift of the input signal or the change in the ambient temperature.

  The upper limit / lower limit detection circuit 23 is disconnected from the loop filter 14, but since the detected lower limit and upper limit are stored in the registers 35 and 36, the values set in the upper limit 21a and the lower limit 21b. Does not change. Further, if the upper and lower limit values are detected and held only once, it is not necessary to disconnect the upper limit / lower limit detection circuit 23 from the loop filter 14, and therefore the switch 24 is not necessarily required.

  After the upper limit and the lower limit are set in the limit circuit 21, the Vtune voltage is always regulated and locked within the capture range. Therefore, after the loop is closed by the switch 20, the output of the lock determination circuit 18 is always at a high level. Therefore, the switches 11 and 14a are not controlled by the output of the lock determination circuit 18, and the off state is maintained. Good. That is, the switches 11 and 14a may be controlled in the opposite direction to the switch 20.

  However, it is not 0% that an abnormal signal is input to the sampler 13 and a part is damaged and the locked state is released. Therefore, the switches 11 and 14a are controlled by the output of the lock determination circuit 18. Is good.

  FIG. 4 shows the relationship between the upper and lower limit and the capture range. (A) is a related art relationship and is the same as FIG. The upper and lower limit values are within the upper and lower limit range, and the capture range is within the upper and lower limit range. Therefore, if the capture range deviates from the upper and lower limit values, it cannot be locked.

  FIG. 4B shows the relationship between the capture range of this embodiment and the upper and lower limits 21a and 21b. The upper and lower limits 21a and 21b and the capture range coincide with each other, and the Vtune voltage is regulated within the upper and lower limits by the limit circuit 21, so that the lock is not released.

  FIG. 5 shows another embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same element as FIG. 1, and description is abbreviate | omitted. In FIG. 5, reference numeral 41 denotes a switch, to which the Vtune voltage that is the output of the loop filter 14 is input and is controlled by the SW control unit 26. Reference numeral 42 denotes a lock time Vtune voltage detection circuit to which the output of the switch 41 is input. That is, the switch 41 inputs the Vtune voltage to the Vtune voltage detection circuit 42 at the time of locking and disconnects it.

  Reference numeral 43 denotes a calculation unit which receives the upper and lower limit values which are the output of the Vtune voltage detection circuit 42 at the time of lock and the output of the upper limit value / lower limit value detection circuit 23, performs a predetermined calculation on these input values, and outputs the result. Output to the D / A converter 22.

  Next, the operation of this embodiment will be described. The SW control unit 26 turns on the switch 24 when the power is turned on or periodically. The upper limit / lower limit detection circuit 23 detects the upper limit value and the lower limit value of the capture range and holds these values. Since this operation has been described with reference to FIG. 1, the detailed description is omitted. At this time, the switch 41 is off.

  Next, the SW control unit 26 turns off the switch 24 and turns on the switch 41. The locked Vtune voltage detection circuit 42 detects the Vtune voltage at this time, holds it as a digital value, and outputs it. Thereafter, the SW control unit 26 turns off the switch 41 and turns on the switches 20 and 25. Thereby, the operation as a PLL is started.

The calculation unit 43 performs the following calculation on the input value and outputs an upper limit value and a lower limit value to the D / A converter 22. Note that the output of the Vtune voltage detection circuit 42 at the time of lock is RV, the upper limit value and lower limit value output by the upper limit value / lower limit value detection circuit 23 are UL and LL, respectively, and the upper limit value and lower limit value output by the calculation unit 43 are SUL, SLL.
SUL = UL + (RV− (UL + LL) / 2)
SLL = LL + (RV− (UL + LL) / 2)
That is, the upper and lower limits of the capture range detected by the upper limit / lower limit detection circuit 23 are corrected by the Vtune voltage at that time.

  When the power is turned on and / or periodically, the switches 24 and 41 are sequentially turned on to detect and hold the upper and lower limits of the capture range and the Vtune voltage at that time. If it is performed when the power is turned on, the variation among the individual voltage controlled oscillators 16 can be corrected. Further, if it is periodically performed after the power is turned on, it is possible to correct the fluctuation of the component characteristics due to the temperature change or the deviation of the input signal so that the locking can be ensured.

It is a block diagram which shows one Example of this invention. It is a waveform diagram of the lock determination circuit 18 output. It is a block diagram which shows one Example of an upper limit / lower limit detection circuit. It is a figure which shows the relationship between an upper / lower limit, an upper / lower limit value, and a capture range. It is a block diagram which shows the other Example of this invention. It is a block diagram of a conventional PLL circuit. It is a figure which shows the relationship between an upper / lower limit, an upper / lower limit value, and a capture range.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Oscillation circuit 11, 14a, 20, 24, 25, 41 Switch 12 Adder circuit 13 Sampler 14 Loop filter 16 Voltage control oscillator 18 Lock determination circuit 21 Limit circuit 21a Upper limit 21b Lower limit 22 D / A converter 23 Upper limit / Lower limit detection circuit 26 SW control unit 42 Vtune voltage detection circuit when locked 43 Calculation unit

Claims (5)

In a PLL circuit that forms a closed loop with a sampler, an adder circuit, a loop filter and a voltage controlled oscillator to which a periodic signal is input, and generates a signal with a predetermined period,
An oscillation circuit that outputs a signal having a period longer than the period of the periodic signal;
A first switch for inputting and disconnecting the output of the oscillation circuit to the adding circuit;
A second switch that disconnects a portion of the closed loop to make it open loop;
A lock determination circuit for determining whether or not the output of the sampler is input and locked;
An output of the loop filter and an output of the lock determination circuit are inputted, and an upper limit value / lower limit value detection circuit for detecting and holding the upper limit value and lower limit value of the capture range and outputting the held upper limit value and lower limit value When,
A limit circuit that receives an output of the upper limit value / lower limit value detection circuit and regulates an output of the loop filter between an upper limit value and a lower limit value detected by the upper limit value / lower limit value detection circuit;
A PLL circuit comprising: In a PLL circuit that forms a closed loop with a sampler, an adder circuit, a loop filter and a voltage controlled oscillator to which a periodic signal is input, and generates a signal with a predetermined period,
An oscillation circuit that outputs a signal having a period longer than the period of the periodic signal;
A first switch for inputting and disconnecting the output of the oscillation circuit to the adding circuit;
A second switch that disconnects a portion of the closed loop to make it open loop;
A lock determination circuit for determining whether or not the output of the sampler is input and locked;
An output of the loop filter and an output of the lock determination circuit are inputted, and an upper limit value / lower limit value detection circuit for detecting and holding the upper limit value and lower limit value of the capture range and outputting the held upper limit value and lower limit value When,
The output of the loop filter is input, and the output voltage of the loop filter at the time of locking is detected and held, and the voltage detection circuit at the time of locking that outputs the held voltage;
The outputs of the upper limit value / lower limit value detection circuit and the lock time voltage detection circuit are input, the output of the lock time voltage detection circuit and the average value of the upper limit value and the lower limit value output by the upper limit value / lower limit value detection circuit, An arithmetic unit that adds the difference between the upper limit value and the lower limit value and outputs the difference,
A limit circuit that receives the output of the calculation unit and regulates the output of the loop filter between the outputs of the calculation unit;
A PLL circuit comprising:   3. The PLL circuit according to claim 1, wherein the first switch is controlled in a direction opposite to that of the second switch. 4.   The first switch is controlled by an output of the lock determination circuit, and includes a third switch for inputting and disconnecting the output of the lock determination circuit to the first switch. The PLL circuit according to claim 3. The upper limit / lower limit detection circuit includes a sample hold circuit that holds the output of the loop filter according to an output of the lock determination circuit, an AD converter that converts an analog voltage held by the sample hold circuit into a digital value, and 5. The PLL circuit according to claim 1, comprising a register that holds a digital value converted by the AD converter.

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