JP2006238157A - Phase matching circuit of clock board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To smoothly and stably switch the clock boards of an operation system and a standby system by accurately matching the phases of a master clock board and a slave clock board even in the case that a comparison frequency in a phase comparator is low and the cut-off of a loop response to jitters is extremely low, regarding the phase matching circuit of the clock board. <P>SOLUTION: Clock signals outputted from the master clock board and the slave clock board respectively are inputted to the phase comparator 1-1, and the phase difference signal of a voltage corresponding to a phase difference outputted from the phase comparator 1-1 is made to pass through a low-pass filter 1-2 and then inputted to a control part 1-3. The control part 1-3 outputs phase control signals for matching the phase on a slave clock board side with the phase on a master clock board side corresponding to the phase difference signals to phase matching PLL circuits 1-4 and 1-4', and the phase matching PLL circuits 1-4 and 1-4' control the phases of the respective clock signals according to the phase control signals and output them. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a phase matching circuit for a clock board. More specifically, in a clock board in a system that handles various digital signals, when the clock board is composed of a master clock board and a slave clock board, the phases of the output signals of the master clock board and the slave clock board are changed. It is related with the circuit to match. When the clock board is composed of a master clock board and a slave clock board, it is necessary to realize a stable (reliable) clock switching characteristic when switching between the master clock board and the slave clock board.

  The master clock board and the slave clock board extract the clock signal from the line and distribute the local clock signal in the system (see FIG. 6). The characteristics of the clock board are required to have low jitter and high stability. On the other hand, the clock signal from the line used as the input signal has a large jitter. In order to satisfy the above characteristics, the clock board is generally composed of the following PLL (Phase Locked Loop) circuit. FIG. 7 shows a block diagram of a clock board using a PLL circuit.

  As shown in FIG. 7, the clock board divides the clock signal input from the line by the frequency divider 7-1 and also divides the clock signal output from the clock board by the frequency divider 7-5. The input clock signal and the output clock signal divided by the frequency dividers 7-1 and 7-5 are input to the phase comparator 7-2, and the phase comparator 7-2 responds to the phase difference between them. The phase difference signal output from the phase comparator 7-2 is input to the voltage controlled oscillator 7-4 through the low pass filter (LPF) 7-3, and the voltage controlled oscillator 7-4 is output. To output a clock signal having a desired frequency.

In the above clock board, the clock signal to be compared by the phase comparator 7-2 is divided and input by the frequency dividers 7-1 and 7-5, and the output signal of the phase comparator 7-2 is Since the voltage is output to the voltage controlled oscillator 7-4 through the low pass filter (LPF) 7-3,
(1) The comparison frequency is low (for example, 8 kHz),
(2) Low cutoff (for example, 1 mHz),
It has the characteristic.

  The reason why the comparison frequency in (1) is lowered is to make the phase comparison range sufficiently wider than the jitter width so that the phase comparator 7-2 can withstand large jitter, and as a result, the comparison frequency is lowered. It becomes. The reason why the cut-off in (2) above is lowered (the response speed to jitter is reduced) is because it is necessary to attenuate and output the jitter, and the cut-off of the loop response to jitter is extremely low. It becomes.

  Using such a clock board as a master clock board and a slave clock board, the clock board is redundantly configured, and switching between the master clock board and the slave clock board, the clock board of one active system (active), the other standby system When used as a (standby) clock board, it is necessary to consider the phase difference between the outputs of the master clock board and the slave clock board.

As a prior art document related to the present invention, the following Patent Document 1 discloses that one clock circuit is operated as a master mode and the other clock circuits are operated as a slave mode, the phases of the clock circuits are aligned, and the master mode described above is used. A clock supply device is described in which one of the clock circuits operating in the slave mode is automatically switched to the master mode when an abnormality occurs in the clock circuit.
JP-A-8-179848

The following cases can be considered as factors causing the phase difference between the output signals of the circuit boards of the master clock board and the slave clock board.
(1) The frequency (comparison frequency) of the input signal of the phase comparator is low. In this case, a large difference occurs in the phase accuracy (resolution) between the input signal and the output signal. For example, when the input signal is 8 KHz and the output signal is 38.88 MHz, a difference of about 5000 times occurs between the two. The phase difference between the output signals of the master clock board and the slave clock board that outputs a 38.88 MHz clock signal based on the phase of the input signal of 8 KHz is difficult to be 1 ns or less.
(2) The cut-off is extremely low.
(3) At power-on and reset.
(4) When inserting / removing the slave clock board side.

  When the master clock board and the slave clock board are switched in a state where there is a phase difference between the output signals of the master clock board and slave clock board, the clock signal is missing (tooth missing) or There has been a problem that a clock phase jump occurs.

  The present invention can adjust the phase of the output clock signal between the master clock board and the slave clock board even when a clock board having a low comparison frequency in the phase comparator and an extremely low cut-off of the loop response to jitter is used. It is an object of the present invention to realize a phase matching circuit that can accurately perform switching between an operating system (active) clock board and a standby system (standby) clock board smoothly and stably.

  The phase alignment circuit for a clock board according to the present invention is (1) a phase alignment circuit for adjusting the phases of clock signals output from an active clock board and a standby clock board, and is output from the operational clock board side. A phase comparator for detecting a phase difference between the clock signal and the clock signal output from the standby clock board side, and the phase of the clock signal on the standby clock board side according to the phase difference detected by the phase comparator. A control unit that outputs a phase control signal that matches the phase of the clock signal on the operating system clock board side, and an output from the control unit for each clock signal that is output from each of the operating system clock board and the standby system clock board And a phase matching PLL circuit for controlling the phase according to the phase control signal.

  (2) As the phase matching PLL circuit, a phase comparator that outputs a voltage signal corresponding to the phase difference between the input signal and the output signal, and a low pass that passes a low frequency component of the output voltage signal of the phase comparator. A filter and a voltage controlled oscillator that oscillates at an oscillation frequency according to an output voltage from the low-pass filter, and controls and outputs a voltage for controlling the oscillation frequency of the voltage controlled oscillator by the phase control signal. The phase of the signal is controlled.

  (3) The phase control signal for controlling the phase of the phase matching PLL circuit is a phase control voltage signal within a predetermined voltage range, and the phase difference between the input signal and the output signal is within the predetermined voltage range. When the phase difference range that can be controlled by (1) is exceeded, a phase difference voltage for one cycle is added to the phase control voltage signal, and phase control is performed within a predetermined voltage range.

  According to the present invention, the phase difference between the clock signal output from the operation system clock board side and the clock signal output from the standby system clock board side is detected, and based on the phase difference, the operation system clock board side By matching the phase of the clock signal output from the standby clock board side to the output clock signal, even if the clock board has a low comparison frequency and extremely low cutoff, the active system and standby system The phase of the output signal of the clock board can be matched with high accuracy.

  In addition, by using a PLL circuit for the phase matching circuit, a buffer PLL circuit or the like existing inside the clock board can be used, so that it can also be configured to be used as a PLL circuit for other purposes. Further, the phase control signal for controlling the phase of the PLL circuit is a phase control voltage signal within a predetermined voltage range, so that the operation of the phase matching PLL circuit can be stabilized.

FIG. 1 shows a configuration example of a phase matching circuit of the present invention. The phase matching circuit of the present invention is roughly composed of the following four parts.
(1) Phase comparator 1-1: It is configured on a back board independent from the master clock board and the slave clock board, and the clock signals output from the clock boards of the master clock board and the slave clock board are inputted, and A signal having a voltage level corresponding to the phase difference between the clock signals is output.
(2) Low-pass filter (LPF) 1-2: Filters the phase difference signal output from the phase comparator 1-1, passes only the low-frequency component, and inputs it to the control unit 1-3 at the next stage.
(3) Control unit 1-3: Outputs phase control signals to the phase matching PLL circuits 1-4 and 1-4 ′ from the phase difference information between the output signals of the master clock board and the slave clock board. The phase control signal controls the slave clock board so as to match the phase of the output signal of the master clock board.
(4) Phase matching PLL circuits 1-4, 1-4 ′: circuits that output signals synchronized with the input signal, and the frequency of the input signal and the frequency of the output signal may be the same or different. . A phase control signal from the control unit 1-3 is input, and based on the phase control signal, the phase matching PLL circuit 1-4 ′ on the slave clock board side performs a linear phase with respect to the phase difference from the master clock board. To converge so that the phase difference becomes zero.

  Based on the configuration of the phase matching circuit of the present invention shown in FIG. 1, the operation and action of phase matching of the present invention will be described. Since the phase adjustment is not performed on the master clock board side after the power is turned on, the phase control signal to the phase adjustment PLL circuit 1-4 on the master clock board side is an initial value for fixing the phase between the input and output signals (for example, If the phase control voltage is 0V to 5V, the control unit 1-3 applies the central value of 2.5V).

The phase adjustment is performed on the slave clock board side, but since it is a closed loop operation, the basic operation of one round will be described below.
(1) An initial value (for example, 2.5 V of the phase control voltage center value) is input from the control unit 1-3 as a phase control signal of the phase matching PLL circuit 1-4 ′.
(2) The phase comparator 1-1 outputs a voltage signal corresponding to the phase difference between the master clock board side and the slave clock board side.
(3) The phase difference signal obtained by filtering the output signal of the phase comparator 1-1 with the low-pass filter (LPF) 1-2 is input to the control unit 1-3 so that the control unit 1-3 has a smaller phase difference. The phase control signal is output to the phase matching PLL circuit 1-4 ′. The slave clock board side always operates so as to match the phase with the master clock board side.

  Next, the operation and action when switching between the master clock board and the slave clock board will be described. The control unit 1-3 controls the phase matching PLL circuit 1-4 ′ on the slave clock board side so as to fix the current phase while holding the current phase control signal simultaneously with the switching. The operation is controlled to be performed on the master clock board side this time.

  Therefore, when switching between the master clock board and the slave clock board, the phase of the output signal of the standby (standby) clock board always matches the phase of the output signal of the active (active) clock board. Therefore, no clock pulse omission (tooth omission) or clock phase skip occurs at the time of switching.

  FIG. 2 shows an example of the configuration of the phase matching PLL circuit shown in FIG. In the figure, a phase comparator 2-1 outputs, as an error signal, a voltage level corresponding to the phase difference between the input signal φr from the clock board side and the feedback signal φc on the output signal side of the phase matching PLL circuit. The low-pass filter (LPF) 2-2 is a filter that uses the reference voltage (VREF) as a reference value of the DC voltage. In the phase matching PLL circuit having this configuration, the phase relationship between the input signal and the output signal is controlled by changing the reference voltage (VREF).

Next, an example of calculating the phase sensitivity of the reference voltage (VREF) is shown below.
・ Input signal frequency: 10 MHz
-Output signal frequency: 10 MHz
・ Frequency of frequency dividers 2-3 and 2-4: 4,
-Phase comparator 2-1 output voltage range: 0-5V (at ± 2π)
Then,
・ Comparative frequency: 2.5 MHz (= 10 MHz / dividing number 4),
・ Comparison period (2π): 400 nS (= 1 ÷ 2.5 MHz),
・ Phase sensitivity of reference voltage (VREF): Kφ = 160 nS / V (= 400 nS ÷ 2.5 V)
It becomes. When the ± 100 nS phase is changed, the reference voltage (VREF) may be changed by ± 0.625 V (= 2.5 V / 4).

  FIG. 3 shows a configuration example of the control unit shown in FIG. As shown in FIG. 1, the control unit inputs the phase difference signal from the phase comparator 1-1 through the low-pass filter (LPF) 1-2. This input signal is converted into a digital signal by an analog-digital converter (ADC) 3-1. This phase difference signal and the voltage value when the phase difference of the phase comparator 1-1 is zero are processed by the adder 3-2 to calculate a phase shift amount. Next, this phase shift is smoothed (averaged) by a low-pass filter (LPF) 3-3 and input to the output data processing unit 3-4.

  In response to the switching signal, the output data processing unit 3-4 outputs the data at the time of switching to the active (active) clock board while retaining the data at the time of switching, and outputs it to the standby (standby) clock board. Outputs a phase control signal so as to perform phase alignment, and the phase control signal passes through each digital-analog converter (DAC) 3-5, 3-5 ′, and a phase alignment PLL circuit of each clock board It is output as a reference voltage (VREF) to the 1-4, 1-4 ′ low-pass filter (LPF) 2-2. By performing this series of operations in a closed loop, the phase difference between the output signals of the master clock board and the slave clock board can be converged to zero.

  FIG. 4 shows an example of the operation of the control unit shown in FIG. The standby (standby) side clock board follows the active (active) side clock board to perform phase alignment. However, the standby (standby) side clock board is positioned during the phase pull-in operation. FIG. 4 shows the phase matching operation when the phase difference is extremely large.

  In the phase matching PLL circuit, if the value of the phase control voltage (reference voltage VREF) deviates greatly from the center, the operation becomes unstable. Therefore, when the phase difference exceeds one cycle, the values are changed to T1 and T2 in FIG. As shown, the phase difference voltage for one cycle is added by the output data processing unit 3-4, and the phase is followed as a phase control voltage (VREF) within the range of the phase difference voltage for one cycle.

  For example, when one cycle is 100 nS, the phase control voltage (VREF) is set to a voltage within a range of ± 0.625 V, and when the phase control voltage (VREF) drops to 1.875 V, 0.625 V is added. When the phase control voltage (VREF) rises to 3.125 V, it is returned to 2.5 V (center voltage) obtained by subtracting 0.625 V.

  FIG. 5 shows an example of a composite configuration of the phase matching PLL circuit of the configuration example shown in FIG. As shown in FIG. 5, the clock board normally receives a plurality of input signals and selects one of them by the selector 5-1. Then, the buffer PLL circuit 5-2 is also provided inside the clock board. Built-in. The buffer PLL circuit 5-2 can be configured to also function as the phase matching PLL circuits 1-4 and 1-4 'shown in FIG.

It is a figure which shows the structural example of the phase matching circuit of this invention. It is a figure which shows an example of a structure of the phase matching PLL circuit of this invention. It is a figure which shows one structural example of the control part of this invention. It is a figure which shows an example of operation | movement of the control part of this invention. It is a figure which shows an example of the composite structure of the phase matching PLL circuit of this invention. It is a figure which shows the structure of the conventional clock board which consists of a master clock board and a slave clock board. It is a block diagram of a clock board using a PLL circuit.

Explanation of symbols

1-1 Phase comparator 1-2 Low pass filter (LPF)
1-3 Control section 1-4, 1-4 'Phase matching PLL circuit

Claims (3)

A phase matching circuit that synchronizes the phase of the clock signal output from the active clock board and the standby clock board,
A phase comparator for detecting a phase difference between a clock signal output from the operation system clock board side and a clock signal output from the standby system clock board side;
In accordance with the phase difference detected by the phase comparator, a control unit that outputs a phase control signal that matches the phase of the clock signal on the standby system clock board side with the phase of the clock signal on the operation system clock board side;
A phase matching PLL circuit that controls the phase in accordance with the phase control signal output from the control unit for each clock signal output from the operational clock board and the standby clock board;
A phase adjusting circuit for a clock panel, comprising:   As the phase matching PLL circuit, a phase comparator that outputs a voltage signal corresponding to a phase difference between an input signal and an output signal, a low-pass filter that passes a low-frequency component of the output voltage signal of the phase comparator, and the low-pass A voltage-controlled oscillator that oscillates at an oscillation frequency according to the output voltage from the filter, and controls the voltage that controls the oscillation frequency of the voltage-controlled oscillator by the phase control signal to control the phase of the output signal The phase adjusting circuit for a clock board according to claim 1, wherein:   The phase control signal for controlling the phase of the phase matching PLL circuit is a signal in a voltage range for controlling the phase difference for one cycle, and the phase difference between the input signal and the output signal is a phase difference for one cycle. 3. The clock board phase matching circuit according to claim 2, wherein when the range is exceeded, phase control is performed by a phase control signal obtained by adding or subtracting a voltage of a phase difference for one cycle.

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