JP2010252126A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit capable of reducing deterioration in phase noise caused by temperature variation. <P>SOLUTION: The PLL circuit 100 includes: a voltage controlled oscillator circuit 81; a frequency divider 82; a phase comparator which compares phases of a reference signal REF-IN and an oscillation signal Output with each other and outputs pulse signals UP, DOWN of pulse widths corresponding to a phase difference; a charge pump 1 with an output current correction function, which outputs CP currents ICPp, ICPn of magnitudes corresponding to the pulse widths of the pulse signals UP, DOWN; a loop filter 85 for controlling a Vt voltage in accordance with the CP currents ICPp, ICPn; and a delay circuit 8 of which the delay time varies in accordance with temperature variation. On the basis of the delay time of the delay circuit 8, the CP current ICPp or ICPn is corrected so that a difference between the CP currents ICPp and ICPn becomes small. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a PLL circuit with a temperature compensation function.

FIG. 9 is a diagram showing an existing PLL circuit.
The PLL circuit 80 shown in FIG. 9 includes a voltage controlled oscillation circuit 81, a frequency divider 82, a phase comparator 83, a charge pump 84, a loop filter 85, and a VCO selection unit 86. .

The frequency divider 82 divides the oscillation signal Output output from the voltage controlled oscillation circuit 81 by 1 / N and outputs the result.
The phase comparator 83 compares the phase of the input oscillation signal REF-IN (reference signal) with the oscillation signal output from the frequency divider 82, and a frequency divider for the oscillation signal REF-IN. A pulse signal UP (first pulse signal) having a pulse width corresponding to the phase difference when the oscillation signal output from 82 is delayed is output from the frequency divider 82 with respect to the oscillation signal REF-IN. A pulse signal DOWN (second pulse signal) having a pulse width corresponding to the phase difference when the oscillation signal to be advanced is output.

  The charge pump 84 outputs a CP current ICPp (first output current) having a magnitude corresponding to the pulse width of the pulse signal UP output from the phase comparator 83 and the pulse signal output from the phase comparator 83. A CP current ICPn (second output current) having a magnitude corresponding to the pulse width of DOWN is output.

  The loop filter 85 increases the Vt voltage (control voltage) according to the CP current ICPp output from the charge pump 84 and decreases the Vt voltage according to the CP current ICPn output from the charge pump 84.

  The voltage-controlled oscillation circuit 81 includes a plurality of voltage-controlled oscillators having mutually different oscillation frequency bands, and the adjacent oscillation frequency bands slightly overlapping each other. Based on the selection signal VCO output from the VCO selection unit 86, a plurality of voltage-controlled oscillation circuits 81 One voltage controlled oscillator is selected from the voltage controlled oscillators, and an oscillation signal Output having a frequency corresponding to the Vt voltage output from the loop filter 85 is output from the selected voltage controlled oscillator. The frequency of the oscillation signal Output output from each voltage controlled oscillator is assumed to increase as the Vt voltage increases in each oscillation frequency band.

The VCO selector 86 outputs a selection signal VCO so that the Vt voltage output from the loop filter 85 falls within a predetermined range.
In the PLL circuit 80 configured as described above, the phase of the oscillation signal Output output from the voltage control oscillation circuit 81 is locked to the phase of the pulse signal REF-IN, and the oscillation signal output from the voltage control oscillation circuit 81 The frequency of the output is controlled by the frequency division ratio 1 / N set in the frequency divider 82.

In addition, since the PLL circuit 80 includes a plurality of voltage controlled oscillators, the oscillation signal Output can be output in a wide oscillation frequency band.
FIG. 10A is a diagram illustrating an example of the charge pump 84.

  The charge pump 84 shown in FIG. 10A includes a current mirror circuit 90 composed of p-channel MOSFETs 87 and 88 and a constant current source 89, and a current mirror composed of n-channel MOSFETs 91 and 92 and a constant current source 93. The circuit 94 includes a switch 95 provided between the current mirror circuit 90 and the output terminal CPO, and a switch 96 provided between the output terminal CPO and the current mirror circuit 94.

  When the pulse signal UP becomes high level and the switch 95 is turned on, the CP current ICPp flowing in the current mirror circuit 90 flows to the output terminal CPO, and the Vt voltage output from the loop filter 85 increases. On the other hand, when the pulse signal DOWN becomes high level and the switch 96 is turned on, the CP current ICPn flowing in the current mirror circuit 94 flows to the output terminal CPO, and the Vt voltage output from the loop filter 85 decreases.

  By the way, due to the characteristics of the MOSFETs 87, 88, 91, and 92, the CP current ICPp decreases as the Vt voltage increases, and the CP current ICPn increases as the Vt voltage increases.

When the difference between the current ICPp and the current ICPn is increased, the phase noise in the oscillation signal Output is deteriorated.
Therefore, the VCO selector 86 needs to output the selection signal VCO so that the difference between the current ICPp and the current ICPn does not increase.

  Therefore, normally, as shown in FIG. 10B, the charge pump 84 is designed so that the CP current ICPp and the current ICPn match at a certain Vt voltage, and the Vt voltage at which the CP current ICPp and the current ICPn match. A selection signal VCO is output from the VCO selector 86 so that the Vt voltage is controlled within a VAS lock range centered at.

  Further, in the PLL circuit 80 configured as described above, if there is a temperature variation after the phase of the oscillation signal Output is locked to the phase of the pulse signal REF-IN, the oscillation signal Output output from the voltage controlled oscillation circuit 81 is output. The Vt voltage changes in order to keep the frequency of the current constant. That is, when the temperature rises, the frequency of the oscillation signal Output increases, and the phase of the oscillation signal output from the frequency divider 82 is delayed with respect to the phase of the oscillation signal REF-IN, so that the Vt voltage increases. On the other hand, when the temperature decreases, the frequency of the oscillation signal Output decreases and the phase of the oscillation signal output from the frequency divider 82 advances with respect to the phase of the oscillation signal REF-IN, so the Vt voltage decreases.

  However, if the Vt voltage changes greatly due to temperature fluctuation, the difference between the CP current ICPp and the CP current ICPn increases. That is, as shown in FIG. 10B, when the Vt voltage increases, the CP current ICPn increases and the CP current ICPp decreases, so that the difference between the CP current ICPp and the CP current ICPn increases. Further, when the Vt voltage decreases, the CP current ICPp increases and the CP current ICPn decreases, so that the difference between the CP current ICPp and the CP current ICPn increases. If the difference between the CP current ICPp and the CP current ICPn becomes large, there is a problem that the phase noise deteriorates as described above.

  As a configuration for reducing the difference between the CP current ICPp and the CP current ICPn, for example, the difference between the CP current ICPp and the CP current ICPn is extracted, and the CP current ICPp is corrected so that the difference becomes zero. (For example, refer to Patent Document 1).

JP 2008-87115 A

  An object of the present invention is to provide a PLL circuit capable of suppressing deterioration of phase noise due to temperature fluctuation.

  The PLL circuit of the present invention includes a voltage-controlled oscillation circuit that outputs an oscillation signal having a frequency that increases as the control voltage increases, a frequency divider that divides and outputs an oscillation signal output from the voltage-controlled oscillation circuit, Compare the phase of the reference signal and the oscillation signal output from the frequency divider, and those when the phase of the oscillation signal output from the frequency divider is delayed with respect to the phase of the reference signal The first pulse signal having a pulse width corresponding to the phase difference of the signal is output, and the level of the oscillation signal output from the frequency divider is advanced with respect to the phase of the reference signal. A phase comparator for outputting a second pulse signal having a pulse width corresponding to the phase difference, and a first output current having a magnitude corresponding to the pulse width of the first pulse signal output from the phase comparator. Together with the phase comparison A charge pump for outputting a second output current having a magnitude corresponding to the pulse width of the second pulse signal outputted from the control circuit, raising the control voltage according to the first output current, and A loop filter that lowers the control voltage according to an output current, a delay circuit that changes a delay time according to a temperature change, and the first output current and the second output based on a delay time of the delay circuit Output current correction means for correcting the first output current or the second output current so that a difference from the current is reduced.

  As a result, even if the temperature fluctuates, the increase in the difference between the first output current and the second output current can be reduced, so that deterioration of phase noise due to temperature fluctuation can be suppressed.

  In the PLL circuit, the frequency of the oscillation signal output from the voltage-controlled oscillation circuit increases as the temperature increases and decreases as the temperature decreases. The delay circuit is designed such that the output current and the second output current coincide with each other, and the delay circuit has a longer delay time as the temperature rises, and a shorter delay time as the temperature falls. The delay circuit may be configured to increase the first output current when the delay time of the delay circuit becomes longer, and to increase the second output current when the delay time of the delay circuit becomes shorter.

  The output current correction means includes a first storage means for storing a delay time of the delay circuit, and a delay time of the delay circuit every time a predetermined time has elapsed since the delay time was stored in the first storage means. And when the value obtained by subtracting the delay time stored in the second storage means from the delay time stored in the first storage means is negative, the first storage means stores the first storage means. The difference between the delay time stored in the storage means and the delay time stored in the second storage means, the first output current is increased, and the delay time stored in the first storage means is used to increase the first time. When the value obtained by subtracting the delay time stored in the second storage means is positive, the difference between the delay time stored in the first storage means and the delay time stored in the second storage means, the first Even if configured to increase the output current of 2. There.

  The PLL circuit includes selection means for outputting a selection signal so that the control voltage output from the loop filter falls within a predetermined range, and the voltage controlled oscillation circuit includes a plurality of voltages having different oscillation frequency bands. A controlled oscillator is provided, and one voltage controlled oscillator is selected from a plurality of voltage controlled oscillators based on a selection signal output from the selection means, and an oscillation signal having a frequency corresponding to the control voltage is selected in the selected voltage controlled oscillator. You may comprise so that it may output.

  According to the present invention, deterioration of phase noise due to temperature fluctuation can be suppressed in a PLL circuit.

It is a figure which shows the PLL circuit of embodiment of this invention. It is a figure which shows the charge pump with an output current correction function. It is a figure which shows the output timing chart of each structure of an output current correction | amendment part. It is a figure which shows an example of a delay circuit. It is a figure which shows an example of a one-shot pulse generation circuit. It is a figure which shows an example of a subtractor. It is a figure which shows an example of an arithmetic circuit. It is a figure which shows an example of the value memorize | stored in a register, and an example of the signal for turning ON / OFF a switch. It is a figure which shows the existing PLL circuit. It is a figure which shows the structure and operation | movement of a charge pump.

FIG. 1 is a diagram illustrating a PLL circuit according to an embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as the structure shown in FIG.
A PLL circuit 100 shown in FIG. 1 includes a voltage controlled oscillation circuit 81, a frequency divider 82, a phase comparator 83, a loop filter 85, a VCO selection unit 86 (selection means), and a charge pump with an output current correction function. 1 (charge pump).

FIG. 2 is a diagram showing the charge pump 1 with an output current correction function. In addition, the same code | symbol is attached | subjected to the same structure as the structure shown to Fig.10 (a).
The charge pump 1 with an output current correction function shown in FIG. 2 includes a charge pump unit 2 and an output current correction unit 3.

  The charge pump unit 2 includes a current mirror circuit 90 including MOSFETs 87 and 88 and a constant current source 89, a current mirror circuit 94 including MOSFETs 91 and 92 and a constant current source 93, switches 95 and 96, and a p-channel. MOSFETs 4 (4-0 to 4-7), n-channel MOSFETs 5 (5-0 to 5-7), switches 6 (6-0 to 6-7), and switches 7 (7-0 to 7-7). Note that the switches 6-0 to 6-8 are each configured by a p-channel MOSFET, and the switches 7-0 to 7-7 are each configured by an n-channel MOSFET. Further, the numbers of the MOSFET 4, the MOSFET 5, the switch 6, and the switch 7 are not particularly limited.

  Since each MOSFET 4 and each switch 6 are connected in series with each other, and they are connected in parallel to the MOSFET 88 and the switch 95, when the number of switches 6 to be turned on increases, a current starts to flow through the MOSFET 4 corresponding to the switch 6 and the output terminal CP current ICPp flowing in CPO increases. Further, each MOSFET 5 and each switch 7 are connected in series with each other, and since they are connected in parallel to the MOSFET 91 and the switch 96, when the number of switches 7 to be turned on increases, a current starts to flow through the MOSFET 5 corresponding to the switch 7. The CP current ICPn flowing through the output terminal CPO increases.

  The output current correction unit 3 includes a delay circuit 8, D-type flip-flops 9 to 31, a register 32 (first storage unit), a register 33 (second storage unit), an M-bit counter 34, A subtractor 35, a one-shot pulse generator 36, an arithmetic circuit 37, and an OR circuit 38 are provided.

  The flip-flops 9 to 31, registers 32 and 33, M-bit counter 34, subtractor 35, one-shot pulse generator 36, arithmetic circuit 37, and OR circuit 38 output current correction described in the claims. Means shall be constructed.

FIG. 3 is a diagram illustrating an output timing chart of each component of the output current correction unit 3.
After the start signal STR input from the outside to the input terminal D through the OR circuit 38 changes from the low level to the high level, the flip-flop 9 receives the clock signal CLK input from the outside to the clock terminal C from the low level. When it becomes high level, the signal data1 output from the output terminal Q changes from low level to high level.

  The delay circuit 8 delays the signal data1 output from the flip-flop 9 for a predetermined time and outputs the signal data2. The elements for configuring the delay circuit 8 are not particularly limited. For example, as shown in FIG. 4, the delay circuit 8 may be configured by including a capacitor 40, a resistor 41, and inverters 42 and 43. Good.

The flip-flops 10 to 23 are connected in series with each other, and a clock signal CLK is input to each clock terminal C.
First, after the signal data1 input from the output terminal Q of the flip-flop 9 to the input terminal D of the flip-flop 10 changes from low level to high level, the clock signal CLK changes from low level to high level. The signal output from the output terminal Q changes from low level to high level.

  Next, after the signal input from the output terminal Q of the flip-flop 10 to the input terminal D of the flip-flop 11 changes from low level to high level, when the clock signal CLK changes from low level to high level, the flip-flop 11 The signal output from the output terminal Q changes from low level to high level.

  Similarly, in the flip-flops 12 to 23, when the output signal of the preceding flip-flop becomes high level and the clock signal CLK becomes high level, the signal output from the subsequent flip-flop becomes high level.

  As described above, when the start signal STR changes from the low level to the high level, the flip-flops 9 to 23 sequentially change the output signal from the low level to the high level every time the clock signal CLK changes from the low level to the high level.

The flip-flops 24 to 31 are connected in series with each other, and the signal data2 output from the delay circuit 8 is input to each input terminal D.
For example, when the signal X2 input from the output terminal Q of the flip-flop 15 to the clock terminal C of the flip-flop 24 changes from the low level to the high level after the signal data2 changes from the low level to the high level, the output of the flip-flop 24 The signal Q0 output from the terminal Q changes from the low level (0) to the high level (1).

  Further, when the signal X1 input from the output terminal Q of the flip-flop 16 to the clock terminal C of the flip-flop 25 changes from the low level to the high level after the signal data2 changes from the low level to the high level, the output of the flip-flop 25 is output. The signal Q1 output from the terminal Q changes from low level to high level.

  When the signal X2 input from the output terminal Q of the flip-flop 17 to the clock terminal C of the flip-flop 26 changes from the low level to the high level after the signal data2 changes from the low level to the high level, the output of the flip-flop 26 is output. The signal Q2 output from the terminal Q changes from low level to high level.

  Further, when the signal X2 input from the output terminal Q of the flip-flop 18 to the clock terminal C of the flip-flop 27 changes from the low level to the high level after the signal data2 changes from the low level to the high level, the output of the flip-flop 27 is output. The signal Q3 output from the terminal Q changes from low level to high level.

  If the signal X4 input from the output terminal Q of the flip-flop 19 to the clock terminal C of the flip-flop 28 changes from the low level to the high level after the signal data2 changes from the low level to the high level, the output of the flip-flop 28 is output. The signal Q4 output from the terminal Q changes from low level to high level.

  Further, when the signal X2 input from the output terminal Q of the flip-flop 20 to the clock terminal C of the flip-flop 29 changes from the low level to the high level after the signal data2 changes from the low level to the high level, the output of the flip-flop 29 is output. The signal Q5 output from the terminal Q changes from low level to high level.

  When the signal X2 input from the output terminal Q of the flip-flop 21 to the clock terminal C of the flip-flop 30 changes from the low level to the high level after the signal data2 changes from the low level to the high level, the output of the flip-flop 30 is output. The signal Q6 output from the terminal Q changes from low level to high level.

  When the signal X2 input from the output terminal Q of the flip-flop 22 to the clock terminal C of the flip-flop 31 changes from the low level to the high level after the signal data2 changes from the low level to the high level, the output of the flip-flop 31 is output. The signal Q7 output from the terminal Q changes from low level to high level.

  Further, since the signal A0 output from the output terminal Q of the flip-flop 23 is input to the input terminal D of the flip-flop 9 via the OR circuit 38, the clock signal is changed after the signal A0 changes from low level to high level. When CLK changes from low level to high level, the signal data1 output from the output terminal Q of the flip-flop 9 again changes from low level to high level. That is, the signals X0 to X7 are repeatedly output from the flip-flops 15 to 22, and the signals Q0 to Q7 indicating the delay time of the delay circuit 81 are repeatedly output from the flip-flops 24 to 31.

  The one-shot pulse generator 36 outputs a one-pulse signal A1 when the clock signal CLK changes from low level to high level after the signal A0 output from the output terminal Q of the flip-flop 23 changes from low level to high level. Output. For example, the one-shot pulse generator 36 may include D-type flip-flops 60 and 61 and a NOR circuit 62 as shown in FIG.

  When a one-pulse signal A1 is output from the one-shot pulse generator 36, signals Q0 to Q7 are stored in the register 32 as D1 [0] to D1 [7], and signals Q0 to Q7 are D2 [0]. ~ D2 [7] are stored in the register 33.

  The M bit counter 34 stores a predetermined number of clocks of the input clock signal CLK (the signals Q0 to Q7 are stored in the register 32 as D1 [0] to D1 [7] after the start signal STR changes from low level to high level). Every time counting is performed, one pulse of signal B is output.

Each time one pulse of the signal B is output from the M-bit counter 34, the signals Q0 to Q7 are overwritten in the register 33 as D2 [0] to D2 [7].
As described above, when the start signal STR is changed from the low level to the high level by the delay circuit 8, the flip-flops 9 to 31, the registers 32 and 33, the M bit counter 34, the one-shot pulse generator 36, and the OR circuit 38, Signals Q0 to Q7 indicating the delay time of the delay circuit 8 in the state are stored in the registers 32 and 33 as D1 [0] to D1 [7], respectively, and thereafter a signal indicating the delay time of the delay circuit 8 every predetermined time. Q0 to Q7 are overwritten in the register 33 as D2 [0] to D2 [7].

  When the signals Q0 to Q7 are stored in the register 33 as D2 [0] to D2 [7] after a lapse of a predetermined time, the delay time of the delay circuit 8 becomes longer if the temperature rises compared to the initial state. , D2 [0] to D2 [7] have a larger number of “0” than D1 [0] to D1 [7]. On the other hand, when the signals Q0 to Q7 are stored in the register 33 as D2 [0] to D2 [7] after a predetermined time has elapsed, if the temperature is lower than the initial state, the delay time of the delay circuit 8 is shortened. Therefore, the number of “0” in D2 [0] to D2 [7] is smaller than that in D1 [0] to D1 [7].

  The computing unit 35 subtracts the number of “0” in D2 [0] to D2 [7] from the number of “0” in D1 [0] to D1 [7] (from the delay time stored in the register 32). When the value obtained by subtracting the delay time stored in the register 33 is negative, that is, when the temperature rises and the delay time becomes longer, a low level signal C is output. The subtractor 35 subtracts the number of “0” in D2 [0] to D2 [7] from the number of “0” in D1 [0] to D1 [7] (delay stored in the register 32). When the value obtained by subtracting the delay time stored in the register 33 from the time) is positive, that is, when the temperature decreases and the delay time becomes shorter, a high-level signal C is output.

  For example, as shown in FIG. 6, the subtractor 35 includes a plurality of full adders 50 (50-0 to 50-7) and a plurality of inverters 51 (51-0 to 51-7). May be. Each full adder 50 includes an OR circuit 52 and half adders 53 and 54. Each of the half adders 53 and 54 includes an XOR circuit 55 and an AND circuit 56.

  Here, D1 [0] to D1 [3] are “0”, D1 [4] to D1 [7] are “1”, D2 [0] to D2 [5] are “0”, D2 [ Consider a case where 6] and D2 [7] are each "1". In this case, the outputs of the full adders 50-0 to 50-3 are at high level, and the outputs of the full adders 50-4 to 50-7 are at low level. Some signal C goes low. D1 [0] to D1 [3] are “0”, D1 [4] to D1 [7] are “1”, D2 [0] to D2 [2] are “0”, and D2 [3 ] To D2 [7] become “1”, the outputs of the full adders 50-0 to 50-3 become low level, and the respective outputs of the full adders 50-3 to 50-7. Since the output becomes high level, the signal C which is the output of the subtractor 35 becomes high level.

  The arithmetic circuit 37 switches the switch 6-0 when the signal C output from the subtractor 35 is low when D2 [0] stored in the register 33 is different from D1 [0] stored in the register 32. The signal SA [0] for turning ON / OFF is set to low level (0), the switch 6-0 is turned ON, and when the signal C output from the subtractor 35 is high level, the switch 7-0 is turned ON, The signal SB [0] for turning off is set to high level to turn on the switch 7-0.

  Further, the arithmetic circuit 37 switches the switch 6 when the signal C output from the subtractor 35 is low when D2 [1] stored in the register 33 is different from D1 [1] stored in the register 32. The signal SA [1] for turning on and off -1 is set to low level to turn on the switch 6-1. When the signal C output from the subtractor 35 is high level, the switch 7-1 is turned on and off. The signal SB [1] for switching is set to the high level to turn on the switch 7-1.

  In addition, when the signal C output from the subtractor 35 is at a low level when the D2 [2] stored in the register 33 is different from the D1 [2] stored in the register 32, the arithmetic circuit 37 switches the switch 6 -2 is turned on and off, the signal SA [2] is set to low level, the switch 6-2 is turned on, and when the signal C output from the subtractor 35 is high level, the switch 7-2 is turned on and off. The signal SB [2] for causing the switch 7-2 to be high level turns on the switch 7-2.

  In addition, when the signal C output from the subtractor 35 is low level when the D2 [3] stored in the register 33 is different from the D1 [3] stored in the register 32, the arithmetic circuit 37 switches the switch 6 The signal SA [3] for turning ON / OFF -3 is set to low level, the switch 6-3 is turned ON, and when the signal C output from the subtractor 35 is high level, the switch 7-3 is turned ON / OFF. The signal SB [3] for switching is set to the high level to turn on the switch 7-3.

  Further, the arithmetic circuit 37 switches the switch 6 when the signal C output from the subtractor 35 is low level when D2 [4] stored in the register 33 is different from D1 [4] stored in the register 32. The signal SA [4] for turning ON / OFF -4 is set to low level, the switch 6-4 is turned ON, and when the signal C output from the subtractor 35 is high level, the switch 7-4 is turned ON / OFF. The signal SB [4] for switching is set to the high level, and the switch 7-4 is turned on.

  The arithmetic circuit 37 switches the switch 6 when the signal C output from the subtractor 35 is low when D2 [5] stored in the register 33 is different from D1 [5] stored in the register 32. The signal SA [5] for turning on and off -5 is set to low level to turn on the switch 6-5. When the signal C output from the subtractor 35 is high level, the switch 7-5 is turned on and off. The signal SB [5] for switching is set to the high level, and the switch 7-5 is turned on.

  The arithmetic circuit 37 switches the switch 6 when the signal C output from the subtractor 35 is low when D2 [6] stored in the register 33 is different from D1 [6] stored in the register 32. The signal SA [6] for turning on and off -6 is set to low level to turn on the switch 6-6. When the signal C output from the subtractor 35 is high level, the switch 7-6 is turned on and off. The signal SB [6] for switching is set to the high level to turn on the switch 7-6.

  The arithmetic circuit 37 switches the switch 6 when the signal C output from the subtractor 35 is low when D2 [7] stored in the register 33 is different from D1 [7] stored in the register 32. The signal SA [7] for turning on and off -7 is set to low level to turn on the switch 6-7. When the signal C output from the subtractor 35 is high level, the switch 7-7 is turned on and off. The signal SB [7] for switching is set to the high level to turn on the switch 7-7.

In the initial state, since the same values are stored in the registers 32 and 33, the switches 6-0 to 6-7 and the switches 7-0 to 7-7 are all turned off.
For example, the arithmetic circuit 37 may include a plurality of comparison circuits 70 (70-0 to 70-7) as shown in FIG. Each comparison circuit 70 includes an XOR (exclusive OR) circuit 71, an AND circuit 72, an OR circuit 73, and an inverter 74.

  Here, for example, as shown in FIG. 8A, the temperature rises compared to the initial state, and D1 [0] to D1 [3] are “0” and D1 [4] to D1 [7] are Consider a case where “1”, D2 [0] to D2 [5] are “0”, and D2 [6] and D2 [7] are “1”, respectively. In this case, the outputs of the XOR circuits 71 of the comparison circuits 70-4 and 70-5 are at the high level (1), and the signal C is at the low level (0), so that the comparison circuits 70-4 and 70-5 The output of each inverter 74 becomes a low level (0), and SA [4] and SA [5], which are the outputs of the OR circuits 73 of the comparison circuits 70-4 and 70-5, respectively become a low level (0). . Accordingly, the switches 6-4 and 6-5 are turned on. As a result, currents flow through the MOSFETs 4-4 and 4-5, respectively, so that the current ICPp can be increased.

  In addition, for example, as shown in FIG. 8B, the temperature decreases as compared with the initial state, D1 [0] to D1 [3] are “0”, and D1 [4] to D1 [7] are respectively Consider a case where “1”, D2 [0] to D2 [2] are “0”, and D2 [3] to D2 [7] are “1”, respectively. In this case, since the output of the XOR circuit 71 of the comparison circuit 70-3 becomes high level (1) and the signal C becomes high level (1), SB [3] which is the output of the AND circuit 72 is high level ( 1). Accordingly, the switch 7-3 is turned on. As a result, a current flows through the MOSFET 5-3, so that the current ICPn can be increased.

  In this way, the switch 6 that is turned on by the subtractor 35 and the arithmetic circuit 37 by the amount of the temperature rise compared to the initial state (the difference between the delay time stored in the register 32 and the delay time stored in the register 33). The CP current ICPp is increased by increasing the number of switches, and the switch 7 to be turned on is the amount that the temperature has decreased compared to the initial state (the difference between the delay time stored in the register 32 and the delay time stored in the register 33). The CP current ICPn can be increased by increasing the number.

The number of switches 4 and 5 to be turned on is set so that the difference between the CP current ICPp and the CP current ICPn approaches zero.
According to the PLL circuit 100 of the present embodiment, when the temperature rises compared to the initial state, the current ICPp can be increased correspondingly, and when the temperature decreases compared to the initial state, the current ICPn is increased accordingly. be able to. Thereby, even if the temperature rises compared to the initial state and the frequency of the oscillation signal Output output from the voltage controlled oscillation circuit 81 increases, or the temperature decreases compared to the initial state and the frequency of the oscillation signal Output Since the difference between the current ICPp and the current ICPn can be reduced even when the current becomes lower, it is possible to suppress the deterioration of the phase noise due to the temperature fluctuation.

  In the PLL circuit 100 of the above-described embodiment, a plurality of oscillation frequency bands are provided to the voltage controlled oscillation circuit 81 by a plurality of voltage controlled oscillators, but only one oscillation frequency band is provided without a plurality of voltage controlled oscillators. The voltage controlled oscillation circuit 81 may be configured to be provided. In such a configuration, the VCO selection unit 86 may be omitted.

1 Charge pump with output current correction function 2 Charge pump unit 3 Output current correction unit 4, 5 MOSFET
6, 7 Switch 8 Delay circuit 9 to 31 Flip-flop 32, 33 Register 34 M-bit counter 35 Subtractor 36 One-shot pulse generator 37 Operation circuit 38 OR circuit 80 PLL circuit 81 Voltage control oscillation circuit 82 Frequency divider 83 Phase comparison 84 Charge pump 85 Loop filter 86 VCO selector 87, 88 MOSFET
89 Constant current source 90 Current mirror circuit 91, 92 MOSFET
93 constant current source 94 current mirror circuit 95, 96 switch 100 PLL circuit

Claims (4)

A voltage-controlled oscillation circuit that outputs an oscillation signal having a frequency that increases as the control voltage increases;
A frequency divider that divides and outputs an oscillation signal output from the voltage controlled oscillation circuit;
Compare the phase of the reference signal and the oscillation signal output from the frequency divider, and those when the phase of the oscillation signal output from the frequency divider is delayed with respect to the phase of the reference signal The first pulse signal having a pulse width corresponding to the phase difference of the signal is output, and the level of the oscillation signal output from the frequency divider is advanced with respect to the phase of the reference signal. A phase comparator that outputs a second pulse signal having a pulse width corresponding to the phase difference;
A first output current having a magnitude corresponding to the pulse width of the first pulse signal output from the phase comparator is output, and according to the pulse width of the second pulse signal output from the phase comparator. A charge pump that outputs a second output current of a magnitude;
A loop filter that increases the control voltage in response to the first output current and decreases the control voltage in response to the second output current;
A delay circuit whose delay time changes according to temperature fluctuations;
An output current for correcting the first output current or the second output current so that a difference between the first output current and the second output current becomes small based on a delay time of the delay circuit. Correction means;
A PLL circuit comprising: The PLL circuit according to claim 1,
The frequency of the oscillation signal output from the voltage controlled oscillation circuit increases as the temperature increases, and decreases as the temperature decreases.
The charge pump is designed such that the first output current and the second output current match at a predetermined control voltage;
The delay circuit has a longer delay time as the temperature increases, and a shorter delay time as the temperature decreases,
The output current correction means increases the first output current when the delay time of the delay circuit becomes longer, and increases the second output current when the delay time of the delay circuit becomes shorter. PLL circuit. A PLL circuit according to claim 1 or claim 2, wherein
The output current correction means includes
First storage means for storing a delay time of the delay circuit;
Second storage means for storing a delay time of the delay circuit every predetermined time after the delay time is stored in the first storage means;
With
When the value obtained by subtracting the delay time stored in the second storage means from the delay time stored in the first storage means is negative, the delay time stored in the first storage means and the second The difference between the delay time stored in the storage means and the first output current is increased, and the delay time stored in the second storage means is subtracted from the delay time stored in the first storage means. When the calculated value is positive, the difference between the delay time stored in the first storage means and the delay time stored in the second storage means, and the second output current are increased. PLL circuit. The PLL circuit according to any one of claims 1 to 3,
Comprising selection means for outputting a selection signal so that the control voltage output from the loop filter falls within a predetermined range;
The voltage-controlled oscillation circuit includes a plurality of voltage-controlled oscillators having mutually different oscillation frequency bands, and selects one voltage-controlled oscillator from the plurality of voltage-controlled oscillators based on a selection signal output from the selection unit, A PLL circuit that outputs an oscillation signal having a frequency corresponding to the control voltage in a selected voltage controlled oscillator.

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