JP2019161592A - Charge pump circuit - Google Patents

Abstract

To reduce the effect of noise without greatly increasing the current consumption and a layout area.SOLUTION: A charge pump circuit includes a first delay circuit that outputs a first delay signal obtained by delaying a first instruction signal that instructs voltage increase, a second delay circuit that outputs a second delay signal obtained by delaying a second instruction signal that instructs voltage drop, a current source circuit that supplies a current to an output node, a current sink circuit that absorbs a current from the output node, a plurality of first switches that switch the connection between the current source circuit and the output node in response to the first instruction signal or the first delay signal, and a plurality of second switches that switch the connection between the current sink circuit and the output node in response to the second instruction signal or the second delay signal.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a charge pump circuit.

  A phase locked loop (PLL) includes a phase filter (PFD: Phase Frequency Detector), a charge pump (CP) circuit, a loop filter such as a low pass filter (LPF), and The circuit includes a voltage controlled oscillator (VCO) and the like, and has a function of generating a new clock signal synchronized with the reference clock signal.

  During operation, the charge pump circuit generates spike-like noise due to parasitic capacitance at the output terminal, and as a result, the oscillation frequency output by the VCO changes instantaneously, which may cause jitter. . In order to reduce such noise, a technique has been proposed in which an overcurrent canceling unit is provided between the main current control unit and the loop filter to cancel the spike-like overcurrent part from the main control current.

  However, the technique as described above has a problem that it is necessary to increase the element size, thereby increasing the layout area and increasing the parasitic capacitance. In addition, there is a problem that current consumption increases due to a canceling current for canceling the overcurrent.

  The present invention has been made in view of the above, and an object of the present invention is to provide a charge pump circuit capable of reducing the influence of noise without greatly increasing the current consumption and the layout area.

  In order to solve the above-described problem and achieve the object, the present invention provides a first delay circuit that outputs a first delay signal obtained by delaying a first instruction signal that instructs voltage increase, and a first delay circuit that instructs voltage decrease. A second delay circuit that outputs a second delay signal obtained by delaying two instruction signals, a current source circuit that supplies current to an output node, a current sink circuit that absorbs current from the output node, and the first instruction signal Or a plurality of first switches for switching the connection between the current source circuit and the output node according to the first delay signal, and the current sink circuit and the second switch according to the second instruction signal or the second delay signal. A plurality of second switches for switching the connection of the output nodes.

  According to the present invention, it is possible to reduce the influence of noise without greatly increasing the current consumption and the layout area.

FIG. 1 is a block diagram illustrating a configuration example of the phase synchronization circuit of the embodiment. FIG. 2 is a diagram illustrating a configuration example of a charge pump circuit of a comparative example. FIG. 3 is a diagram illustrating an example of the terminal voltage of the output node. FIG. 4 is a diagram for explaining an example of the parasitic capacitance. FIG. 5 is a diagram illustrating an example of noise generated at the output node. FIG. 6 is a diagram illustrating a configuration example of the charge pump circuit according to the first embodiment. FIG. 7 is a diagram illustrating a setting example of the delay amount and an example of the terminal voltage of the output node. FIG. 8 is a diagram illustrating a setting example of the delay amount and an example of the terminal voltage of the output node. FIG. 9 is a diagram illustrating a setting example of the delay amount and an example of the terminal voltage of the output node. FIG. 10 is a diagram illustrating a configuration example of the delay circuit. FIG. 11 is a diagram illustrating another configuration example of the delay circuit. FIG. 12 is a diagram illustrating the correspondence between the delay signal and the instruction signal. FIG. 13 is a diagram illustrating a configuration example of the charge pump circuit according to the second embodiment. FIG. 14 is a diagram illustrating a setting example of the delay amount and an example of the terminal voltage of the output node. FIG. 15 is a diagram illustrating a configuration example of the charge pump circuit according to the third embodiment. FIG. 16 is a diagram illustrating a configuration example of the charge pump circuit according to the fourth embodiment. FIG. 17 is a diagram illustrating a configuration example of a delay circuit capable of setting a delay amount. FIG. 18 is a diagram illustrating another configuration example of the delay circuit in which the delay amount can be set.

  Hereinafter, an embodiment of a charge pump circuit according to the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
The charge pump circuit according to the first embodiment includes a plurality of control switches that operate in response to an instruction signal instructing voltage increase and a plurality of control switches that operate in response to an instruction signal instructing voltage decrease. By shifting the control timing, the spike noise caused by the parasitic capacitance is dispersed and the peak is suppressed. Thereby, the influence of noise on the VCO can be reduced without greatly increasing the current consumption and the layout area. That is, it is possible to reduce the jitter of the oscillation frequency output by the VCO.

  FIG. 1 is a block diagram illustrating a configuration example of the phase synchronization circuit of the present embodiment. As shown in FIG. 1, the phase synchronization circuit includes a PFD 10, a CP 20 that is a charge pump circuit, an LPF 30, a VCO 40, and a frequency divider 50.

  The PFD 10 compares the reference clock signal and the feedback clock signal, and outputs an instruction signal UP and an instruction signal DN that control the CP 20. The instruction signal UP is a signal (first instruction signal) for instructing a voltage increase. The instruction signal DN is a signal (second instruction signal) that instructs a voltage drop.

  The CP 20 outputs a current in the inflow direction or the outflow direction based on the instruction signal UP and the instruction signal DN.

  The LPF 30 generates a voltage based on the inflow or outflow direction current output from the CP 20. This voltage becomes the input voltage to the VCO 40.

  The VCO 40 outputs an output clock signal having a frequency corresponding to the input voltage. The smaller the undulation change of the voltage signal input to the VCO 40, the smaller the jitter of the output clock signal.

  The frequency divider 50 divides the output clock signal and inputs the divided signal to the PFD 10 as a feedback clock signal.

  Here, a configuration example of a charge pump circuit that does not include a plurality of control switches will be described. FIG. 2 is a diagram illustrating a configuration example of a CP 20b that is a charge pump circuit of a comparative example that does not include a plurality of control switches. As shown in FIG. 2, the CP 20b of the comparative example includes an inverting element 21, a current source circuit Iup, a current sink circuit Idn, a P-channel transistor Tp, an N-channel transistor Tn, and an output node CPO. . The LPF 30 includes a resistance element 31 and a capacitor 32, for example.

  The inverting element 21 inverts the instruction signal UP and outputs it to the P-channel transistor Tp. The current source circuit Iup is a current source that supplies a current to the output node CPO. The current sink circuit Idn is a current source that absorbs current from the output node CPO.

  The P-channel transistor Tp is turned on / off by an instruction signal UP supplied from the PFD 10. The N-channel transistor Tn performs an on / off operation according to the instruction signal DN. These on / off operations control the outflow of current from the current source circuit Iup and the inflow of current to the current sink circuit Idn, and the outflow and inflow of current to the LPF 30 are controlled.

  Normally, the current from the current source circuit Iup and the current to the current sink circuit Idn are designed to have the same current value. If instruction signal UP and instruction signal DN have the same timing and the same pulse width, ideally the current from current source circuit Iup flows to current sink circuit Idn, and the potential of output node CPO does not change. FIG. 3 is a diagram illustrating an example of the terminal voltage of the output node CPO in such an ideal state.

  As described above, in the CP 20b as shown in FIG. 2, spike-like noise due to the parasitic capacitance is generated at the output node CPO. FIG. 4 is a diagram for explaining an example of the parasitic capacitance generated in the CP 20b as shown in FIG. FIG. 5 is a diagram illustrating an example of noise generated at the output node CPO.

As shown in FIG. 4, the following parasitic capacitance exists in the CP 20b.
-Parasitic capacitance Cp1 of the drain node of the current source transistor
A parasitic capacitance Cp2 between the gate of the P-channel transistor Tp and the output node CPO
-Parasitic capacitance Cn1 at the drain node of the current sink transistor
A parasitic capacitance Cn2 between the gate of the N-channel transistor Tn and the output node CPO

  Note that the current source transistor indicates a transistor constituting the current source circuit Iup. In FIG. 4, the transistor to which the bias voltage BIAS1 is applied is a current source transistor. The current sink transistor is a transistor constituting the current sink circuit Idn. In FIG. 4, the transistor to which the bias voltage BIAS2 is applied is a current sink transistor.

The parasitic capacitance described above can cause the following effects, for example.
Effect of parasitic capacitance Cp1: The P-channel transistor Tp is turned on by the instruction signal UP, and the current source transistor flows the rising constant current to the output node CPO. At the same time, the charge accumulated in the parasitic capacitance Cp1 also flows as a spike-like discharge current, resulting in voltage fluctuation.
Effect of parasitic capacitance Cp2: In response to the transition of the instruction signal UP, coupling due to the parasitic capacitance Cp2 occurs, and spike-like voltage fluctuations occur at the output terminal.
Effect of parasitic capacitance Cn1: The N channel transistor Tn is turned on by the instruction signal DN, and the current sink transistor causes a falling constant current to flow from the output node CPO. At this time, voltage fluctuations in which charges are accumulated as spike-like charging current also occur in the parasitic capacitance Cn1.
Effect of parasitic capacitance Cn2: Coupling due to the parasitic capacitance Cp2 occurs according to the transition of the instruction signal DN, and spike-like voltage fluctuations occur at the output terminal.

  These spike-like voltage fluctuations are proportional to the parasitic capacitance. Therefore, by reducing the transistor size of each transistor (P-channel transistor Tp, N-channel transistor Tn, current source transistor, and current sink transistor), the parasitic capacitance is reduced, and the voltage derived from the parasitic capacitance to some extent. Variation can be reduced.

  However, for example, reducing the gate width of the current source transistor reduces the parasitic capacitance Cp1, but increases the drain-source voltage Vds required for the current source transistor. Therefore, in order for the current source transistor to supply a desired amount of current, there arises a problem that the upper limit of the voltage of the output node CPO is lowered.

  Even in the P-channel transistor Tp, when the gate width is narrowed, the parasitic capacitance Cp2 is reduced, but the on-resistance of the P-channel transistor Tp is increased. An increase in the on-resistance of the P-channel transistor Tp means that a voltage drop generated in the P-channel transistor Tp increases, and as a result, the upper limit of the output node CPO voltage for the current source transistor to supply a desired amount of current is increased. The problem of being lowered arises.

  Similar problems may occur for the current sink transistor and the N-channel transistor Tn. Therefore, there is a limit to reducing the transistor size of each transistor (P-channel transistor Tp, N-channel transistor Tn, current source transistor, and current sink transistor).

  As described above, a technique of providing an overcurrent cancel unit has been proposed in order to reduce spike-like noise. In order to completely cancel the spike-like noise caused by the parasitic capacitance, it is necessary to make the element characteristics of the elements constituting the main current control unit and the overcurrent cancellation unit the same. However, it is difficult to make the device characteristics the same due to manufacturing variations. Moreover, since it is necessary to increase the element size in order to make the element characteristics the same, the area is increased and the parasitic capacitance is increased. Further, an increase in current consumption due to the cancel current is caused in the overcurrent cancel unit.

  On the other hand, in the present embodiment, the influence of noise is reduced by shifting the generation timing of spike-like noise instead of canceling the charge accumulated in the parasitic capacitance. This embodiment can be realized mainly by adding a delay circuit, and the current consumption and layout area do not increase greatly.

  Next, a configuration example of the charge pump circuit of this embodiment will be described. FIG. 6 is a diagram illustrating a configuration example of the CP 20 that is the charge pump circuit according to the present embodiment. As shown in FIG. 6, the CP 20 of the present embodiment includes a plurality of delay circuits (DELAY) 101, 102, 103, 104, a plurality of current source circuits Iup1, Iup2, Iup3, and a plurality of current sink circuits Idn1, Idn2. , Idn3, a plurality of control switches SWp1, SWp2, SWp3, a plurality of control switches SWn1, SWn2, SWn3, and an output node CPO.

  FIG. 6 shows an example in which three current source circuits and three current sink circuits are provided and four delay circuits are provided, but the number of each part is not limited to this.

  The instruction signal UP1 and the instruction signal DN1 are input from the PFD 10 to the CP 20. The instruction signal UP1 is a signal (first instruction signal) for instructing a voltage increase. The instruction signal DN1 is a signal (second instruction signal) for instructing a voltage drop.

  The delay circuit 101 outputs a delay signal UP2 (an example of a first delay signal) obtained by delaying the instruction signal UP1. The delay circuit 102 outputs a delay signal UP3 (an example of a first delay signal) obtained by further delaying the delay signal UP2. The delay circuits 101 and 102 correspond to a delay circuit (first delay circuit) that outputs a delay signal (first delay signal) obtained by delaying an instruction signal (first instruction signal) that instructs voltage increase.

  The delay circuit 103 outputs a delay signal DN2 (an example of a second delay signal) obtained by delaying the instruction signal DN1. The delay circuit 104 outputs a delay signal DN3 (an example of a second delay signal) obtained by further delaying the delay signal DN2. The delay circuits 103 and 104 correspond to a delay circuit (second delay circuit) that outputs a delay signal (second delay signal) obtained by delaying an instruction signal (second instruction signal) instructing voltage drop.

  The plurality of current source circuits Iup1, Iup2, and Iup3 are connected to the control switches SWp1, SWp2, and SWp3, respectively, and supply current to the output node CPO according to the on / off operation of the corresponding control switch.

  The plurality of current sink circuits Idn1, Idn2, and Idn3 are connected to the control switches SWn1, SWn2, and SWn3, respectively, and absorb current from the output node CPO according to the on / off operation of the corresponding control switch.

  The control switch SWp1 is turned on / off according to the instruction signal UP1, and switches the connection between the current source circuit Iup1 and the output node CPO. The control switch SWp2 is turned on / off according to the delay signal UP2, and switches the connection between the current source circuit Iup2 and the output node CPO. The control switch SWp3 is turned on / off according to the delay signal UP3, and switches the connection between the current source circuit Iup3 and the output node CPO.

  The control switches SWp1, SWp2, SWp3 are switches (first switch) for switching the connection between the current source circuits Iup1, Iup2, Iup3 and the output node CPO according to an instruction signal (first instruction signal) or a delay signal (first delay signal). Switch).

  The control switch SWn1 is turned on / off according to the instruction signal DN1, and switches the connection between the current sink circuit Idn1 and the output node CPO. The control switch SWn2 is turned on / off according to the delay signal DN2, and switches the connection between the current sink circuit Idn2 and the output node CPO. The control switch SWn3 is turned on / off according to the delay signal DN3, and switches the connection between the current sink circuit Idn3 and the output node CPO.

  The control switches SWn1, SWn2, SWn3 are switches (second switch) for switching the connection between the current sink circuits Idn1, Idn2, Idn3 and the output node CPO according to the instruction signal (second instruction signal) or the delay signal (second delay signal). Switch).

  By using the delay signals UP2, DN2, UP3, and DN3 delayed from the instruction signal UP1 or the instruction signal DN1 in this way, the timing is shifted for each delay time, and the corresponding control switch is turned on / off. be able to.

  In the CP 20 shown in FIG. 6, each of the current source circuits Iup1, Iup2, Iup3 and the current sink circuits Idn1, Idn2, Idn3 is configured, for example, as a single unit (for example, the current source circuit Iup, the current sink circuit Idn in FIG. 2). ) Current capacity (ie, the size is 1/3). Further, each of the control switches SWp1, SWp2, SWp3, SWn1, SWn2, SWn3 is, for example, three times the on-resistance (ie, the size is smaller than that of the single switch (for example, the P-channel transistor Tp and the N-channel transistor Tn in FIG. 2)). 1/3).

  Therefore, the values of the parasitic capacitances Cp11 to Cp13, Cp21 to Cp23, Cn11 to Cn13, and Cn21 to Cn23 are each 1/3 of the case where they are configured as a single unit (for example, the parasitic capacitances Cp1, Cp2, Cn1, and Cn2 in FIG. 2). Become. By controlling the control switch in three times and shifting the timing, it is possible to suppress the peak of the voltage fluctuation derived from the parasitic capacitance to 1/3.

  In the above example, N is an integer of 2 or more, the size of the current source circuit and the current sink circuit is 1 / N, the size of the control switch is 1 / N, and the control timing of the control switch is divided into N times. Can be generalized to configuration. There is no need to strictly reduce the size of each part to 1 / N, or to divide the control timing exactly N times, and any ratio can be used as long as the voltage fluctuation peak due to parasitic capacitance can be suppressed. Alternatively, the timing may be determined.

  7 and 8 are diagrams illustrating an example of setting the delay amount and an example of the terminal voltage of the output node. As shown in FIG. 7, the delay amount (delay time) may be shorter than the width of the instruction signal UP1. As shown in FIG. 8, the delay amount may be longer than the width of the instruction signal UP1.

  However, when the delay amount is smaller than the noise width, the noise cannot be dispersed, and thus the peak cannot be sufficiently suppressed. FIG. 9 is a diagram illustrating an example of setting the delay amount and an example of the terminal voltage of the output node in such a case. Therefore, it is desirable to set the delay amount to be larger than the noise width.

  Next, a configuration example of the delay circuits 101 to 104 will be described. Hereinafter, the delay circuit 101 will be described as an example, but the other delay circuits 102 to 104 may have the same configuration. FIG. 10 is a diagram illustrating a configuration example of the delay circuit 101. As shown in FIG. 10, the delay circuit 101 can be configured to connect two inverting elements 1001 and 1002 in series. With this configuration, it is possible to output the delay signal UP2 in which a delay is generated with respect to the instruction signal UP1. Note that the number of inversion elements is not limited to two, and an even number of inversion elements other than two may be used.

  FIG. 11 is a diagram illustrating another configuration example of the delay circuit 101. As shown in FIG. 11, the delay circuit 101 can be configured to include inverting elements 1201 and 1204, a resistance element 1202 and a capacitor 1203 connected in series. Based on the time constant RC determined by the resistance value R of the resistance element 1202 and the capacitance C of the capacitor 1203, the delay signal UP2 in which the delay is generated with respect to the instruction signal UP1 can be output.

  FIG. 12 is a diagram showing the correspondence between the delay signal UP2 and the instruction signal UP1 delayed by the delay circuit 101 of FIG. 10 or FIG.

  The configurations of the delay circuits 101, 102, 103, and 104 are not limited to the configurations shown in FIGS. 10 and 11, and may be any configuration.

(Second Embodiment)
Next, a phase synchronization circuit including the charge pump circuit of the second embodiment will be described. The overall configuration of the phase synchronization circuit of the second embodiment is the same as that shown in FIG. The charge pump circuit of this embodiment includes one current source circuit and one current sink circuit.

  FIG. 13 is a diagram illustrating a configuration example of the CP 20-2 which is the charge pump circuit according to the second embodiment. As shown in FIG. 13, the CP 20-2 of the present embodiment includes a plurality of delay circuits 101, 102, 103, 104, one current source circuit Iup, one current sink circuit Idn, and a plurality of control switches SWp1. -2, SWp2-2, SWp3-2, a plurality of control switches SWn1-2, SWn2-2, SWn3-2, and an output node CPO.

  In the present embodiment, the number of current source circuits Iup and current sink circuits Idn is 1, the control switches SWp1-2, SWp2-2, and SWp3-2 are connected to the current source circuit Iup, and the control switches The difference from the first embodiment is that SWn1-2, SWn2-2, and SWn3-2 are connected to the current sink circuit Idn. Since the other configuration is the same as that of the charge pump circuit CP20 of the first embodiment shown in FIG. 6, the same reference numerals are given and description thereof is omitted.

  The current source circuit Iup is connected to the control switches SWp1-2, SWp2-2, and SWp3-2, and supplies current to the output node CPO according to the on / off operation of the corresponding control switch.

  The current sink circuit Idn is connected to the control switches SWn1-2, SWn2-2, and SWn3-2, and absorbs current from the output node CPO according to the on / off operation of the corresponding control switch.

  The control switch SWp1-2 is turned on / off according to the instruction signal UP1, and switches the connection between the current source circuit Iup and the output node CPO. The control switch SWp2-2 is turned on / off according to the delay signal UP2, and switches the connection between the current source circuit Iup and the output node CPO. The control switch SWp3-2 is turned on / off according to the delay signal UP3, and switches the connection between the current source circuit Iup and the output node CPO.

  The control switch SWn1-2 is turned on / off according to the instruction signal DN1, and switches the connection between the current sink circuit Idn and the output node CPO. The control switch SWn2-2 is turned on / off according to the delay signal DN2, and switches the connection between the current sink circuit Idn and the output node CPO. The control switch SWn3-2 is turned on / off according to the delay signal DN3, and switches the connection between the current sink circuit Idn and the output node CPO.

  Even in the configuration as shown in FIG. 13, by using the delay signals UP2, DN2, UP3, and DN3 that are delayed from the instruction signal UP1 or the instruction signal DN1, the timing is shifted for each delay time to cope with each. The control switch to be turned on / off can be operated.

  In CP20-2 shown in FIG. 13, the current source circuit Iup and the current sink circuit Idn have the same current capability as the case where they are configured as a single unit (for example, the current source circuit Iup and the current sink circuit Idn in FIG. 2). On the other hand, each of the control switches SWp1-2, SWp2-2, SWp3-2, SWn1-2, SWn2-2, and SWn3-2 is configured, for example, as a single unit (for example, the P-channel transistor Tp and the N-channel transistor in FIG. 2). The on-resistance (that is, the size is 1/3) that is three times Tn).

  Accordingly, the values of the parasitic capacitances Cp21 to Cp23 and Cn21 to Cn23 are each 1/3 of the case where they are configured as a single unit (for example, the parasitic capacitances Cp1, Cp2, Cn1, and Cn2 in FIG. 2). By controlling the control switch in three times and shifting the timing, it is possible to suppress the peak of the voltage fluctuation derived from the parasitic capacitance to 1/3. However, since current source circuit Iup and current sink circuit Idn are not divided, noise derived from parasitic capacitances Cp1 and Cn1 is generated without being divided when transitioning to instruction signal UP1 and instruction signal DN1.

  FIG. 14 is a diagram illustrating a setting example of the delay amount and an example of the terminal voltage of the output node. Compared to FIG. 7 and the like (first embodiment), the noise corresponding to the instruction signal UP1 and the instruction signal DN1 is not sufficiently suppressed, but it is possible to suppress the peak by dispersing spiked noise.

  Similar to the first embodiment, in the above example, N is an integer of 2 or more, the size of the current source circuit and the current sink circuit is 1 / N, the size of the control switch is 1 / N, and the control switch is controlled. It can be generalized to a configuration in which the timing is divided into N times. There is no need to strictly reduce the size of each part to 1 / N, or to divide the control timing exactly N times, and any ratio can be used as long as the voltage fluctuation peak due to parasitic capacitance can be suppressed. Alternatively, the timing may be determined.

(Third embodiment)
Next, a phase locked loop circuit including a charge pump circuit according to a third embodiment will be described. The overall configuration of the phase synchronization circuit of the third embodiment is the same as that shown in FIG. The charge pump circuit of this embodiment implements a current source circuit, a current sink circuit, and a control switch with transistors.

  FIG. 15 is a diagram illustrating a configuration example of the CP 20-3 that is the charge pump circuit according to the third embodiment. As shown in FIG. 15, the CP 20-3 of this embodiment includes a plurality of delay circuits 101, 102, 103, 104, transistors Tso1, Tso2, Tso3, transistors Tsi1, Tsi2, Tsi3, transistors Tp1, Tp2, Tp3, Tn1, Tn2, Tn3 and an output node CPO are provided. Since the delay circuits 101, 102, 103, and 104 are the same as those in the first embodiment, the same reference numerals are given and description thereof is omitted.

  The transistors Tso1, Tso2, and Tso3 are transistors corresponding to a current source circuit. Transistors Tsi1, Tsi2, and Tsi3 are transistors corresponding to a current sink circuit. The bias voltages BIAS1 and BIAS2 for each transistor can be generated by a current mirror circuit using a reference current, for example.

  The transistors Tp1, Tp2, Tp3, Tn1, Tn2, and Tn3 are transistors that correspond to control switches. The transistors Tp1, Tp2, Tp3, Tn1, Tn2, and Tn3 correspond to the control switches SWp1, SWp2, SWp3, SWn1, SWn2, and SWn3, respectively, in the CP20 of FIG. 6, for example.

  For example, the transistor Tp1 is turned on / off according to the instruction signal UP1, and switches the connection between the transistor Tso1 corresponding to the current source circuit Iup1 and the output node CPO. Similarly, the other transistors Tp2, Tp3, Tn1, Tn2, and Tn3 have a function of switching the connection in the same manner as the corresponding control switches SWp2, SWp3, SWn1, SWn2, and SWn3.

  Note that the configuration in which the current source circuit, the current sink circuit, and the control switch are realized by transistors can be applied to other embodiments.

(Fourth embodiment)
Next, a phase locked loop circuit including a charge pump circuit according to a fourth embodiment will be described. The overall configuration of the phase synchronization circuit of the fourth embodiment is the same as that shown in FIG. The charge pump circuit of the present embodiment uses a delay circuit that can set a delay amount.

  FIG. 16 is a diagram illustrating a configuration example of the CP 20-4 that is the charge pump circuit according to the fourth embodiment. As shown in FIG. 16, the CP 20-3 of the present embodiment includes a plurality of delay circuits 101-4, 102-4, 103-4, and 104-4, a plurality of current source circuits Iup1, Iup2, and Iup3. Current sink circuits Idn1, Idn2, and Idn3, a plurality of control switches SWp1, SWp2, and SWp3, a plurality of control switches SWn1, SWn2, and SWn3, and an output node CPO. Since the configurations other than the delay circuits 101-4, 102-4, 103-4, and 104-4 are the same as those in the first embodiment, the same reference numerals are given and the description thereof is omitted.

  The delay circuit 101-4 outputs a delay signal UP2 (an example of a first delay signal) obtained by delaying the instruction signal UP1 in accordance with the set delay amount. The delay circuit 102-4 outputs a delay signal UP3 (an example of a first delay signal) obtained by further delaying the delay signal UP2 in accordance with the set delay amount.

  The delay circuit 103-4 outputs a delay signal DN2 (an example of a second delay signal) obtained by delaying the instruction signal DN1 according to the set delay amount. The delay circuit 104-4 outputs a delay signal DN3 (an example of a second delay signal) obtained by further delaying the delay signal DN2 in accordance with the set delay amount.

  As described above, when the delay amount is smaller than the noise width, the noise cannot be dispersed, and thus the peak cannot be suppressed. Therefore, the delay amount needs to be larger than the noise width. In the present embodiment, by setting the delay amount, the delay amount can be set to be equal to or greater than the spike width.

  FIG. 17 is a diagram illustrating a configuration example of a delay circuit capable of setting a delay amount. In the example of FIG. 17, the delay circuit includes a selector 1801 that selects one of a plurality of paths in which the number of inverting elements that generate a delay is different from each other. A desired delay amount can be set by inputting information SEL indicating which delay amount is to be input to the selector 1801. FIG. 17 shows an example in which one of the three delay amounts is selected, but the number of selectable delay amounts is not limited to three.

  FIG. 18 is a diagram illustrating another configuration example of the delay circuit in which the delay amount can be set. In the example of FIG. 18, the delay circuit includes inverting elements 1901 and 1904, a variable resistor 1902, and a variable capacitor 1903. By making the time constant RC determined by the resistance value R of the variable resistor 1902 and the capacitance C of the variable capacitor 1903 variable, a desired delay amount can be set.

  As the delay amount, a common value may be set for the plurality of delay circuits 101-4, 102-4, 103-4, and 104-4, or individual values may be set for some or all of the delay circuits. You may comprise as follows. Note that the configuration that allows the delay amount of the delay circuit to be set can be applied to embodiments other than the first embodiment.

10 Phase frequency comparator (PFD)
20, 20-2, 20-3, 20-4 Charge pump circuit (CP)
30 Low-pass filter (LPF)
40 Voltage controlled oscillator (VCO)
50 Divider 101-104, 101-4 to 104-4 Delay circuit Iup1, Iup2, Iup3 Current source circuit Idn1, Idn2, Idn3 Current sink circuit SWp1, SWp2, SWp3, SWn1, SWn2, SWn3 Control switch CPO output node

JP 09-266443 A

Claims (7)

A first delay circuit that outputs a first delay signal obtained by delaying a first instruction signal that instructs voltage increase;
A second delay circuit for outputting a second delay signal obtained by delaying a second instruction signal for instructing a voltage drop;
A current source circuit for supplying current to the output node;
A current sink circuit for absorbing current from the output node;
A plurality of first switches for switching connection between the current source circuit and the output node in response to the first instruction signal or the first delay signal;
A plurality of second switches for switching the connection between the current sink circuit and the output node in response to the second instruction signal or the second delay signal;
A charge pump circuit comprising: A plurality of current source circuits and a plurality of current sink circuits are provided,
Each of the plurality of first switches switches connection between any one of the plurality of current source circuits and the output node,
Each of the plurality of second switches switches connection between any of the plurality of current sink circuits and the output node.
The charge pump circuit according to claim 1. One current source circuit and one current sink circuit are provided;
Each of the plurality of first switches switches connection between the current source circuit and the output node,
Each of the plurality of second switches switches connection between the current sink circuit and the output node.
The charge pump circuit according to claim 1. The first delay circuit and the second delay circuit include an even number of inverting elements.
The charge pump circuit according to claim 1. The first delay circuit and the second delay circuit include a resistance element and a capacitor connected in series,
The charge pump circuit according to claim 1. The first delay circuit outputs the first delay signal obtained by delaying the first instruction signal according to a set delay amount;
The second delay circuit outputs the second delay signal obtained by delaying the second instruction signal according to a set delay amount;
The charge pump circuit according to claim 1. The current source circuit and the current sink circuit are transistors.
The charge pump circuit according to claim 1.

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