JPH09331009A - Lead frame, lead frame member and resin sealed semiconductor device employing them - Google Patents

Lead frame, lead frame member and resin sealed semiconductor device employing them

Info

Publication number
JPH09331009A
JPH09331009A JP8168709A JP16870996A JPH09331009A JP H09331009 A JPH09331009 A JP H09331009A JP 8168709 A JP8168709 A JP 8168709A JP 16870996 A JP16870996 A JP 16870996A JP H09331009 A JPH09331009 A JP H09331009A
Authority
JP
Japan
Prior art keywords
lead frame
plating
semiconductor device
semiconductor element
electroless copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8168709A
Other languages
Japanese (ja)
Inventor
Masahito Sasaki
将人 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP8168709A priority Critical patent/JPH09331009A/en
Publication of JPH09331009A publication Critical patent/JPH09331009A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Abstract

PROBLEM TO BE SOLVED: To provide a lead frame and a lead frame member of copper alloy in which delamination due to formation of a copper oxide on the surface of the lead frame can be prevented regardless of the assembling conditions of an IC without sacrifice of bondability. SOLUTION: The lead frame made of a copper alloy is provided with a die pad 111 for mounting a semiconductor element and subjected to partial plating of a noble metal 150 for wire bonding or die bonding. The die pad 111 is subjected, at least on the rear side where the semiconductor element is not mounted, to electroless copper plating 140 at a surface roughness Ra of JIS B0601 in the range of 0.05-0.1μm.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、封止用樹脂との接合強
度を向上させた、銅合金を素材としたリードフレーム、
及びリードフレームを用いたリードフレーム部材に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame made of a copper alloy, which has improved bonding strength with a sealing resin.
And a lead frame member using the lead frame.

【０００２】[0002]

【従来の技術】従来より、半導体装置の組立部材として
用いられる（単層）リードフレームは、通常、コバー
ル、４２合金（４２％ニッケル−鉄合金）、銅系合金の
ような導電性に優れた金属から成り、プレス法もしくは
エッチング法により形成されていた。一般的なプラスチ
ックパッケージであるＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐ
ａｃｋａｇｅ）用のリードフレームは、図９（ｂ）
（イ）に示すように、半導体素子を搭載するためのダイ
パッド８２１と、ダイパッド８２１の周囲に設けられた
半導体素子と結線するためのインナーリード８２２と、
該インナーリード８２２に連続して外部回路との結線を
行うためのアウターリード８２３、樹脂封止する際のダ
ムとなるダムバー８２４、リードフレーム８２０全体を
支持するフレーム（枠）部８２５等を備えている。そし
て、リードフレーム８２０は、図９（ａ）に示すよう
に、ダイパッド部８２１をインナーリード８２２形成面
よりもダウンセットした状態でダイパッド８２１に半導
体素子８１０を搭載し、半導体素子８１０の端子（パッ
ド）８１１とインナーリード８２２の先端部とを金など
のワイヤ８３０で結線を行った後に、樹脂８４０にて封
止して、ダムバー８２４部の切断工程、アウターリード
８２３部のフオーミング工程を経て半導体装置８００を
作製していた。尚、図９（ｂ）（ロ）は、図９（ｂ）
（イ）のＦ１−Ｆ２における断面図である。2. Description of the Related Art Conventionally, a (single layer) lead frame used as an assembly member of a semiconductor device is usually excellent in conductivity such as Kovar, 42 alloy (42% nickel-iron alloy), and copper alloy. It was made of metal and formed by pressing or etching. QFP (Quad Flat P) which is a general plastic package
The lead frame for package) is shown in FIG. 9 (b).
As shown in (a), a die pad 821 for mounting a semiconductor element, an inner lead 822 for connecting to a semiconductor element provided around the die pad 821,
The inner lead 822 is provided with an outer lead 823 for connecting to an external circuit, a dam bar 824 serving as a dam for resin sealing, a frame portion 825 supporting the entire lead frame 820, and the like. There is. Then, as shown in FIG. 9A, in the lead frame 820, the semiconductor element 810 is mounted on the die pad 821 with the die pad portion 821 set down from the surface on which the inner leads 822 are formed. ) 811 and the tip of the inner lead 822 are connected by a wire 830 such as gold, and then sealed with a resin 840, and a dam bar 824 cutting process and an outer lead 823 forming process are performed. 800 was produced. 9 (b) and (b) are shown in FIG. 9 (b).
It is sectional drawing in F1-F2 of (a).

【０００３】このようなリードフレームは、半導体素子
８１０の端子（パッド）８１１とインナーリード８２２
の先端部とを金などのワイヤ８３０でワイヤボンディン
グ（結線）、半導体素子の搭載の際に、強い結合力と導
電性を確保するために、貴金属めっきを、少なくともイ
ンナーリード８２２先端部、ダイパッド８２１の半導体
搭載側の面に施していた。貴金属めっきとしては、銀め
っき処理が一般には採られていた。Such a lead frame has terminals (pads) 811 of a semiconductor element 810 and inner leads 822.
Of the inner lead 822 and the die pad 821 at least in order to secure a strong bonding force and conductivity at the time of wire bonding (connection) with a wire 830 such as gold for mounting the semiconductor element. Was applied to the surface of the semiconductor mounting side. As the noble metal plating, a silver plating treatment is generally adopted.

【０００４】従来のリードフレームにおいては、図８
（ａ）に示すように、ダイパッド１１１の半導体素子搭
載側とインナーリード１１２の先端部に、リードフレー
ム素材（銅合金）１２０上に、順に銅ストライクめっき
１３０、銀めっき１５０を形成しており、その銀めっき
工程は、図８（ｂ）に示すように、外形加工されたリー
ドフレーム素材１２０に対し、脱脂、酸洗い等の前処理
（図８（ｂ）（イ））を行ってから、一般に下地めっき
として０．１〜０．３μｍ厚程度の銅（Ｃｕ）ストライ
クめっきを施し（図８（ｂ）（ロ））、所望の領域に
１．５〜１０μｍ厚の銀めっきを施こした（図８（ｂ）
（ハ））後に、本来不要である部分に薄くついた銀（モ
レなど）を除去する電解剥離処理をしてから、ベンゾト
リアゾール系等の有機系薬品により被膜を作り、酸化、
水酸化による変色を防止する変色防止処理（図８（ｂ）
（ニ））を施すものであった。銀めっき方法としては、
マスキング治具を用いリードフレームの所定領域を覆い
露出部へ銀めっきを吹きかけて部分的に銀めっきを施す
方法や、リードフレームに電着レジストを塗膜した後、
電着レジストを製版して所定の部分のみ露出した状態で
めっき液に浸漬してめっきを施す方法等が用いられてい
る。このような処理が施された銅合金を素材としたリー
ドフレームにおいては、半導体装置の作製工程や半導体
装置の実装工程においても、下地めっきが通常剥離する
ことはなく、半導体装置に使用された場合にも、銅スト
ライク部の剥離はないとされていた。FIG. 8 shows a conventional lead frame.
As shown in (a), a copper strike plating 130 and a silver plating 150 are sequentially formed on a lead frame material (copper alloy) 120 at the semiconductor element mounting side of the die pad 111 and the tip of the inner lead 112. In the silver plating step, as shown in FIG. 8B, after pretreatment such as degreasing and pickling is performed on the externally processed lead frame material 120 (FIGS. 8B and 8A), Generally, copper (Cu) strike plating having a thickness of about 0.1 to 0.3 μm is applied as a base plating (FIGS. 8B and 8B), and silver plating having a thickness of 1.5 to 10 μm is applied to a desired region. (Fig. 8 (b)
(C)) After that, electrolytic stripping treatment is performed to remove thin silver (more) that is originally unnecessary, and then a film is formed with an organic chemical such as benzotriazole, and oxidation,
Discoloration prevention treatment to prevent discoloration due to hydroxylation (Fig. 8 (b))
(D)) was applied. As a silver plating method,
After covering a predetermined area of the lead frame with a masking jig and applying silver plating to the exposed part to partially silver plating, or after coating the lead frame with an electrodeposition resist,
There is used a method in which an electrodeposition resist is made into a plate and is immersed in a plating solution in a state where only a predetermined portion is exposed to perform plating. In the case of a lead frame made of a copper alloy that has been subjected to such a treatment, the base plating does not usually peel off even during the semiconductor device manufacturing process or the semiconductor device mounting process However, it was said that there was no peeling of the copper strike part.

【０００５】しかしながら、最近、このような処理が施
された銅合金を素材とするリードフレームを用いた場
合、リードフレームに起因したパッケージのデラミネー
ション（剥離）が半導体装置組み立て工程や実装工程で
生じていることが分かってきた。尚、パッケージのデラ
ミネーション（剥離）とは、ＩＣパッケージ内の各界
面、即ちＩＣチップ（半導体素子）と封止用樹脂との界
面、ダイボンディング剤とＩＣチップ（半導体素子）と
の界面等での剥離を言うが、リードフレームに起因する
デラミネーション（剥離）は封止用樹脂とダイパッド裏
面との界面での剥離等である。封止用樹脂とダイパッド
裏面との界面でのデラミネーション（剥離）の発生は、
銅合金を素材とするリードフレームの表面処理や組み立
て条件と密接な関係があることも次第に分かってきた。
銀めっきの下地めっきとして銅ストライクめっきが施こ
され、銀めっき後に電解剥離と変色防止が施された、銅
合金を素材とするリードフレームにおいては、ＩＣ（半
導体装置）組み立て工程中の加熱工程で、銅合金表面に
酸化膜が生じ、酸化膜と金属（銅合金）との間の密着強
度が不十分であることが、デラミネーション（剥離）発
生の原因と考えられている。However, recently, when a lead frame made of a copper alloy which has been subjected to such a treatment is used, delamination (peeling) of the package due to the lead frame occurs in a semiconductor device assembling process and a mounting process. I have come to understand that. The delamination of the package means each interface in the IC package, that is, the interface between the IC chip (semiconductor element) and the sealing resin, the interface between the die bonding agent and the IC chip (semiconductor element), and the like. The delamination caused by the lead frame is peeling at the interface between the sealing resin and the back surface of the die pad. The occurrence of delamination at the interface between the sealing resin and the back surface of the die pad
It has gradually become clear that there is a close relationship with the surface treatment and assembly conditions of lead frames made of copper alloy.
In a lead frame made of copper alloy, which has been subjected to copper strike plating as a base plating of silver plating, and electrolytic peeling and discoloration prevention have been applied after silver plating, the heating process during the IC (semiconductor device) assembly process It is considered that delamination occurs because an oxide film is formed on the surface of the copper alloy and the adhesion strength between the oxide film and the metal (copper alloy) is insufficient.

【０００６】このような状況のもと、封止用樹脂とダイ
パッド裏面との界面、さらには、封止用樹脂とリードフ
レーム全面との界面の発着強度を向上させ、デラミ発生
を防止するための方法として、特表平７−５０３１０３
号（特願平５−５１２６８８号）等が提案されている。
特表平７−５０３１０３号（特願平５−５１２６８８
号）では、クロムと亜鉛の混合体あるいはクロム、亜鉛
それぞれの単体からなる薄い被膜で全面を覆ったリード
フレームが開示されている。しかし、このリードフレー
ムは、銀めっき部分も他の金属被膜で覆われるため、金
ワイヤボンディング性が劣るという問題がある。Under these circumstances, the adhesion strength at the interface between the encapsulating resin and the back surface of the die pad, as well as the interface between the encapsulating resin and the entire surface of the lead frame, is improved to prevent the occurrence of delamination. As a method, the special table 7-503103
Japanese Patent Application No. 5-512688 is proposed.
Japanese Patent Publication No. 7-503103 (Japanese Patent Application No. 5-512688)
No.) discloses a lead frame whose entire surface is covered with a thin film made of a mixture of chromium and zinc or a simple substance of each of chromium and zinc. However, this lead frame has a problem that the gold wire bondability is poor because the silver-plated portion is also covered with another metal film.

【０００７】また、ＩＣ組み立て工程の条件は、組立を
実施するＩＣメーカーにより異なり、銅合金製リードフ
レームの表面酸化状態、酸化膜形成過程もメーカー毎に
異なる為、リードフレームに起因するデラミネーション
の発生状況がＩＣ組み立てメーカーによって異なってい
た。例えば、ベンゾトリアゾール系の被膜により、銅の
酸化、水酸化による変色を防止する処理方法では、ＩＣ
組み立て温度が低いメーカに対しては、デラミネーショ
ン防止効果が得られるが、ＩＣ組み立て温度が高いメー
カではデラミネーション防止効果が得られない。このた
め、従来はデラミネーションに対する対策をＩＣ組み立
て条件に合わせて各メーカ毎に行っていたのが実状で、
ＩＣの組み立て条件によらず、リードフレームに起因す
るデラミネーションに対応できる手段が求められてい
た。Further, the conditions of the IC assembling process differ depending on the IC maker who carries out the assembling, and the surface oxidation state of the copper alloy lead frame and the oxide film forming process also differ depending on the maker, so that delamination caused by the lead frame may occur. The occurrence situation was different depending on the IC assembly manufacturer. For example, in a treatment method for preventing discoloration due to copper oxidation or hydroxylation by a benzotriazole-based coating,
The delamination prevention effect can be obtained for a manufacturer whose assembly temperature is low, but the delamination prevention effect cannot be obtained for a manufacturer whose IC assembly temperature is high. For this reason, in the past, each manufacturer has taken measures against delamination according to the IC assembly conditions.
There has been a demand for means capable of coping with delamination caused by the lead frame, regardless of IC assembly conditions.

【０００８】[0008]

【発明が解決しようとする課題】このように、銅合金製
のリードフレームにおいては、リードフレーム表面の銅
酸化膜生成に起因した半導体装置（ＩＣ）におけるデラ
ミネーションを防止し、ＩＣの信頼性低下、ＩＣ組み立
て工程、実装工程における良品率の低下を防止すること
が望まれており、特に、ＩＣの組み立て条件によらず、
リードフレームに起因するデラミネーションの発生を防
止できるものが求められていた。本発明は、このような
状況のもと、ＩＣの組み立て条件によらず、リードフレ
ーム表面の銅酸化膜生成に起因したデラミネーションの
発生を防止でき、且つ、ボンディング性を損なわない、
銅合金製のリードフレーム、およびリードフレーム部材
を提供しようとするものである。As described above, in the copper alloy lead frame, delamination in the semiconductor device (IC) due to the formation of a copper oxide film on the surface of the lead frame is prevented, and the reliability of the IC is reduced. It is desired to prevent a reduction in the non-defective rate in the IC assembly process and the mounting process.
There has been a demand for a material that can prevent delamination caused by the lead frame. Under the circumstances, the present invention can prevent the occurrence of delamination due to the formation of a copper oxide film on the surface of the lead frame and does not impair the bondability, regardless of the assembly conditions of the IC.
An object of the present invention is to provide a lead frame made of a copper alloy and a lead frame member.

【０００９】[0009]

【課題を解決するための手段】本発明のリードフレーム
は、銅合金材からなり、半導体素子が搭載されるダイパ
ッドを備え、ワイヤボンディング用ないしダイボンディ
ング用の部分貴金属めっきが施された樹脂封止型の半導
体装置用リードフレームであって、少なくとも半導体素
子を搭載する側でないダイパッド裏面の表面に、ＪＩＳ
規格 Ｂ０６０１の表面の粗さＲａが０．０５〜０．１
μｍの粗さに無電解銅めっきを施してあることを特徴と
するものである。そして、上記における、無電解銅めっ
きが次亜リン酸塩を還元剤とするものである。本発明の
リードフレーム部材は、ワイヤボンディング用の部分貴
金属めっきが施されたリードフレームと、半導体搭載部
となる放熱板とを備えた樹脂封止型の半導体装置用リー
ドフレーム部材であって、少なくとも半導体素子が搭載
される放熱板の半導体素子を搭載する側でない面の表面
に、ＪＩＳ規格 Ｂ０６０１の表面の粗さＲａが０．０
５〜０．１μｍの粗さに無電解銅めっきを施してあるこ
とを特徴とするものである。そして、上記における、無
電解銅めっきが次亜リン酸塩を還元剤とするものであ
る。A lead frame of the present invention is made of a copper alloy material, has a die pad on which a semiconductor element is mounted, and is resin-sealed for wire bonding or partially noble metal plating for die bonding. Type semiconductor device lead frame, wherein at least the surface of the die pad rear surface not mounting the semiconductor element is JIS
The surface roughness Ra of the standard B0601 is 0.05 to 0.1.
It is characterized in that electroless copper plating is applied to a roughness of μm. The electroless copper plating described above uses hypophosphite as a reducing agent. The lead frame member of the present invention is a resin-sealed lead frame member for a semiconductor device, which is provided with a lead frame for wire bonding that is partially noble metal plated, and a heat dissipation plate that serves as a semiconductor mounting portion. The surface roughness Ra of JIS standard B0601 is 0.0 on the surface of the heat dissipation plate on which the semiconductor element is not mounted on the side on which the semiconductor element is mounted.
The electroless copper plating is applied to the roughness of 5 to 0.1 μm. The electroless copper plating described above uses hypophosphite as a reducing agent.

【００１０】本発明の樹脂封止型半導体装置は、銅合金
材からなり、半導体素子が搭載されるダイパッドを備
え、ワイヤボンディング用ないしダイボンディング用の
部分貴金属めっきが施されたリードフレームで、少なく
とも半導体素子を搭載する側でないダイパッド裏面の表
面に、ＪＩＳ規格 Ｂ０６０１の表面の粗さＲａが０．
０５〜０．１μｍの粗さに無電解銅めっきを施してある
リードフレームを用いたことを特徴とするものである。
また、本発明の樹脂封止型半導体装置は、ワイヤボンデ
ィング用の部分貴金属めっきが施されたリードフレーム
と、半導体搭載部となる放熱板とを備えたリードフレー
ム部材で、少なくとも半導体素子が搭載される放熱板の
半導体素子を搭載する側でない面の表面に、ＪＩＳ規格
Ｂ０６０１の表面の粗さＲａが０．０５〜０．１μｍ
の粗さに無電解銅めっきを施してあるリードフレーム部
材を用いたことを特徴とするものである。A resin-encapsulated semiconductor device of the present invention is a lead frame which is made of a copper alloy material and has a die pad on which a semiconductor element is mounted, and which is at least partially plated with a noble metal for wire bonding or die bonding. On the surface of the back surface of the die pad that is not the side on which the semiconductor element is mounted, the surface roughness Ra of JIS standard B0601 is 0.
It is characterized by using a lead frame having electroless copper plating with a roughness of 05 to 0.1 μm.
Further, the resin-sealed semiconductor device of the present invention is a lead frame member including a lead frame for wire bonding, which is plated with a partial noble metal, and a heat sink serving as a semiconductor mounting portion, and at least a semiconductor element is mounted on the lead frame member. The surface roughness Ra of JIS standard B0601 is 0.05 to 0.1 μm on the surface of the heat sink that is not the side on which the semiconductor element is mounted.
It is characterized in that a lead frame member having electroless copper plating applied to its roughness is used.

【００１１】[0011]

【作用】本発明のリードフレームは、上記のような構成
にすることにより、ＩＣの組み立て条件によらず、リー
ドフレームに起因する半導体装置における封止樹脂のデ
ラミネーションの発生を防止でき、且つ、ワイヤボンデ
イング性を損なわない銅合金製のリードフレームの提供
を可能としている。詳しくは、本発明のリードフレーム
は、銅合金材からなり、半導体素子が搭載されるダイパ
ッドを備え、ワイヤボンディング用ないしダイボンディ
ング用の部分貴金属めっきが施された樹脂封止型の半導
体装置用リードフレームで、封止用樹脂と接する側のワ
イヤボンディングないしダイボンディングに必要な銀め
っき等の貴金属めっきが施された領域以外の全面ないし
所定の部分の表面に、ＪＩＳ規格 Ｂ０６０１の表面の
粗さＲａが０．０５〜０．１μｍの粗さに無電解銅めっ
きを施してあることにより、半導体装置組立工程中に生
成される無電解銅めっきを施した部分の酸化膜が、母体
銅合金から剥離しにくくなり、これを達成している。特
に、少なくとも半導体素子を搭載するダイパッド裏面の
表面に上記無電解銅めっきを施してあることにより半導
体装置に用いられた際には、封止樹脂のデラミネーショ
ンの発生を有効に防止できるものとしている。With the lead frame of the present invention having the above-mentioned structure, it is possible to prevent the occurrence of delamination of the sealing resin in the semiconductor device due to the lead frame, regardless of the IC assembly conditions, and It is possible to provide a lead frame made of copper alloy that does not impair wire bondability. More specifically, the lead frame of the present invention is made of a copper alloy material, includes a die pad on which a semiconductor element is mounted, and is a resin-encapsulated semiconductor device lead that has been subjected to partial precious metal plating for wire bonding or die bonding. Roughness Ra of the surface of JIS standard B0601 is provided on the entire surface or a predetermined portion of the frame other than the area where the precious metal plating such as silver plating necessary for wire bonding or die bonding on the side in contact with the sealing resin is applied. Has a roughness of 0.05 to 0.1 μm, so that the oxide film of the electroless copper-plated portion generated during the semiconductor device assembly process is separated from the base copper alloy. It's harder to do and you've achieved this. In particular, at least the surface of the back surface of the die pad on which the semiconductor element is mounted is subjected to the electroless copper plating, so that when used in a semiconductor device, it is possible to effectively prevent the occurrence of delamination of the sealing resin. .

【００１２】本発明のリードフレーム部材は、上記のよ
うに構成することにより、特に、リードフレームとは別
体の放熱板に起因する半導体装置における封止樹脂のデ
ラミネーションの発生を防止でき、且つ、ワイヤボンデ
イング性を損なわない銅合金製のリードフレーム部材の
提供を可能としている。詳しくは、本発明のリードフレ
ーム部材は、ワイヤボンディング用の部分貴金属めっっ
きが施されたリードフレームと、半導体搭載部となる放
熱板とを備えた樹脂封止型の半導体装置用リードフレー
ム部材であって、リードフレームの封止用樹脂と接する
側のワイヤボンディングに必要な銀めっき等の貴金属め
っきが施された領域以外の全面ないし所定の部分の表
面、ないし、放熱板の全面ないし所定部分の表面に、Ｊ
ＩＳ規格 Ｂ０６０１の表面の粗さＲａが０．０５〜
０．１μｍの粗さに無電解銅めっきを施してあることに
より、半導体装置組立工程中に生成される無電解銅めっ
きを施した部分の酸化膜が、母体から剥離しにくくな
り、これを達成している。特に、少なくとも半導体素子
が搭載される放熱板の半導体素子を搭載する側でない面
の表面に、上記無電解銅めっきを施してあることにより
半導体装置に用いられた際には、封止樹脂のデラミネー
ションの発生を有効に防止できるものとしている。そし
て、上記無電解銅めっきが、次亜リン酸塩を還元剤とす
るものであることにより、無電解めっき工程を複雑にす
ることなく、別の粗面化処理を施す必要もなく、無電解
めっき部表面のＪＩＳ規格 Ｂ０６０１の表面の粗さＲ
ａを、比較的簡単に、０．０５〜０．１μｍの範囲の粗
さとすることを可能としている。また、半田のめっき性
についても、本発明のリードフレームおよびリードフレ
ーム部材は、従来と変わることはなく良好である。By configuring the lead frame member of the present invention as described above, in particular, it is possible to prevent the occurrence of delamination of the sealing resin in the semiconductor device due to the heat dissipation plate separate from the lead frame, and It is possible to provide a lead frame member made of a copper alloy that does not impair wire bondability. More specifically, the lead frame member of the present invention is a resin-encapsulated lead frame for a semiconductor device, which includes a lead frame to which a partial noble metal plating for wire bonding is applied, and a heat dissipation plate to be a semiconductor mounting portion. It is a member, the entire surface or a predetermined portion of the surface of the lead frame other than the area plated with a noble metal such as silver necessary for wire bonding on the side in contact with the encapsulating resin, or the entire surface of the heat sink or a predetermined area. J on the surface of the part
The surface roughness Ra of IS standard B0601 is 0.05 to
By electroless copper plating with a roughness of 0.1 μm, the oxide film on the electroless copper plated part that is generated during the semiconductor device assembly process is less likely to peel off from the base, and this is achieved. are doing. In particular, when the electroless copper plating is applied to at least the surface of the heat dissipation plate on which the semiconductor element is not mounted on the side on which the semiconductor element is mounted, when the semiconductor device is used, the sealing resin is not removed. It is supposed that the occurrence of lamination can be effectively prevented. Then, the electroless copper plating, by using the hypophosphite as a reducing agent, without complicating the electroless plating step, without the need for another roughening treatment, electroless Roughness of JIS standard B0601 surface of plated part
It is possible to make a relatively rough in the range of 0.05 to 0.1 μm. Further, the lead frame and the lead frame member of the present invention have good solder plating property as well as the conventional one.

【００１３】本発明の樹脂封止型半導体装置は、本発明
のリードフレームないし本発明のリードフレーム部材を
用いることにより、封止樹脂のデラミネーションの発生
を防止でき、ワイヤボンディング状態の良好な樹脂封止
型半導体装置の提供を可能とするものである。In the resin-sealed semiconductor device of the present invention, by using the lead frame of the present invention or the lead frame member of the present invention, it is possible to prevent the occurrence of delamination of the sealing resin and the resin in a good wire bonding state. It is possible to provide a sealed semiconductor device.

【００１４】尚、上記本発明のリードフレームにおいて
は、無電解銅めっきは、リードフレームの素材面の全面
に通常の電解銅めっきを施した後に、ワイヤボンディン
グやダイボンディング用の銀等の貴金属めっきを施した
後に施されるのが好ましい。また、上記本発明のリード
フレーム部材においては、放熱板への無電解めっきは、
リードフレームとは別に、放熱板単独で、全面に通常の
電解銅めっきを施した後に、必要な場合は、ダイボンデ
ィング用の銀等の貴金属めっきを施した後に施されるの
が好ましい。In the above-mentioned lead frame of the present invention, the electroless copper plating is carried out by subjecting the entire material surface of the lead frame to ordinary electrolytic copper plating, and then plating with noble metal such as silver for wire bonding or die bonding. It is preferable that the treatment is performed after the treatment. Further, in the lead frame member of the present invention, the electroless plating on the heat dissipation plate,
Separately from the lead frame, it is preferable that the heat radiating plate is applied to the entire surface after ordinary electrolytic copper plating, and if necessary, after noble metal plating such as silver for die bonding.

【００１５】[0015]

【実施例】本発明のリードフレームの実施例を挙げ、図
にそって説明する。図１は実施例のリードフレームのを
示したものであり、図１（ｂ）はその平面図であり、図
１（ａ）はＡ１−Ａ２における断面の要部拡大図であ
る。図１中、１１０はリードフレーム、１１１はダイパ
ッド、１１２はインナーリード、１１３はアウターリー
ド、１１４はダムバー、１１５はフレーム、１１６は吊
りバー、１２０はリードフレーム素材（銅合金）、１３
０は（電解）銅めっき、１４０は無電解銅めっき、１５
０は（部分）銀めっきである。本実施例のリードフレー
ム１１０は、厚さ０．１５ｍｍの銅合金材（古河電気工
業株式会社製ＥＦＴＥＣ６４Ｔ−１／２Ｈ材）からエッ
チング加工により図１（ｂ）のような形状に外形加工さ
れたリードフレーム素材１２０に対し、電解銅めっき１
３０（以下、電解銅めっきは単に銅めっきと言う）をリ
ードフレーム１１０の表面全面に施してから、この上に
所定の領域のみに部分銀めっき１５０を施し、更に所定
の部分に無電解銅めっき１４０を施したものであるが、
無電解銅めっき１４０を施す際の還元剤として次亜リン
酸塩を用いたことにより、無電解銅めっき１４０の表面
部の粗さをＪＩＳ規格 Ｂ０６０１のＲａを０．０７μ
ｍとし、半導体装置を作製する際、無電解銅めっき１４
０において封止用樹脂とのデラミネーション（剥離）が
おきずらいものとしている。Ｒａとしては０．０５〜
０．１０が好ましい。本実施例のリードフレームは、表
面部となる無電解銅めっき１４０の表面粗さＲａを所定
の範囲内に設定していることにより、母材金属（銅合
金）と酸化膜との密着性を向上させ、結果として、半導
体装置を作製する場合には封止樹脂とのデラミネーショ
ンの発生を抑えることができるものとしている。本実施
例では、ダイパッド１１１の裏面側以外にも、無電解銅
めっき１４０を設けているが、ダイパッド１１１の裏面
のみに設けても、その効果は大きいものである。EXAMPLE An example of the lead frame of the present invention will be given and described with reference to the drawings. FIG. 1 shows a lead frame of an embodiment, FIG. 1 (b) is a plan view thereof, and FIG. 1 (a) is an enlarged view of a main part of a cross section taken along line A1-A2. In FIG. 1, 110 is a lead frame, 111 is a die pad, 112 is an inner lead, 113 is an outer lead, 114 is a dam bar, 115 is a frame, 116 is a suspension bar, 120 is a lead frame material (copper alloy), 13
0 is (electrolytic) copper plating, 140 is electroless copper plating, 15
0 is (partial) silver plating. The lead frame 110 of the present embodiment was externally processed into a shape as shown in FIG. 1B by etching from a copper alloy material (EFTEC64T-1 / 2H material manufactured by Furukawa Electric Co., Ltd.) having a thickness of 0.15 mm. Electrolytic copper plating 1 for lead frame material 120
30 (hereinafter, electrolytic copper plating is simply referred to as copper plating) is applied to the entire surface of the lead frame 110, and then partial silver plating 150 is applied only to a predetermined area, and electroless copper plating is further applied to a predetermined area. Although 140 is applied,
By using hypophosphite as a reducing agent when the electroless copper plating 140 is applied, the roughness of the surface portion of the electroless copper plating 140 is 0.07 μ in Ra of JIS standard B0601.
m, and when manufacturing a semiconductor device, electroless copper plating 14
In No. 0, delamination (peeling) with the sealing resin is difficult to occur. Ra as 0.05-
0.10 is preferable. In the lead frame of the present embodiment, the surface roughness Ra of the electroless copper plating 140 serving as the surface portion is set within a predetermined range, so that the adhesion between the base metal (copper alloy) and the oxide film is improved. As a result, it is possible to suppress the occurrence of delamination with a sealing resin when manufacturing a semiconductor device. In this embodiment, the electroless copper plating 140 is provided in addition to the back surface side of the die pad 111, but the effect is large if it is provided only on the back surface of the die pad 111.

【００１６】また、本実施例においては、銅めっき１３
０を厚さ０．１μｍ、無電解銅めっき１４０の厚さを
０．５μｍ、銀めっき１５０を厚さ３μｍとしたが、銅
めっき１３０の厚さとしては、０．１〜０．３μｍ、銀
めっき１５０の厚さとしては１．５〜１０μｍ、無電解
銅めっき１４０の厚さとしては０．１μｍ以上、１．０
μｍ以下が好ましい。また、リードフレーム素材１２０
として古河電気工業株式会社製の銅合金ＥＦＴＥＣ６４
Ｔ−１／２Ｈ材を用いているが、本発明はこれに限定さ
れることはなく、他の銅合金でも良い。In this embodiment, the copper plating 13
0 was 0.1 μm thick, the electroless copper plating 140 was 0.5 μm thick, and the silver plating 150 was 3 μm thick, but the copper plating 130 has a thickness of 0.1 to 0.3 μm and silver. The thickness of the plating 150 is 1.5 to 10 μm, and the thickness of the electroless copper plating 140 is 0.1 μm or more, 1.0.
μm or less is preferable. In addition, the lead frame material 120
Copper alloy EFTEC64 manufactured by Furukawa Electric Co., Ltd.
Although the T-1 / 2H material is used, the present invention is not limited to this, and other copper alloys may be used.

【００１７】次に、本実施例のリードフレームのめっき
工程を図３に基づいて簡単に説明しておく。尚、図３図
は、図１（ａ）に相当する部分である。先ず、エッチン
グにて外形加工された銅合金からなるリードフレーム１
１０Ａの全面をアルカリ水溶液で電解脱脂し、純水で洗
浄した後、酸性液で表面に形成されている酸化膜を除去
する酸活性化処理を行い、リードフレーム素材１２０で
ある銅合金の表面を活性化して、再度純水で洗浄した。
（図３（ａ）） リードフレーム１１０Ａの表面全体に銅めっき施した。
（図３（ｂ）） 銅めっきは、液温５０°Ｃで２０秒程度、シアン化銅め
っきを行い、約０．１μｍの厚さに形成した。次いで、
銅めっき１３０が施されたリードフレーム１１０Ａ表面
の所定部分に、マスキング治具を用い、めっき液をリー
ドフレームに噴射する部分めっき方法により部分銀めっ
き１５０を３．０μｍの厚さで施した。（図３（ｃ）） この後、部分銀めっき１５０を施す際に、不要な銀めっ
き１５０Ａが形成されてしまうことがあるため、不要な
銀めっき１５０Ａを除去し、銀めっき１５０を均一とす
るため、電解剥離を行った。（図３（ｄ））Next, the lead frame plating process of this embodiment will be briefly described with reference to FIG. Note that FIG. 3 is a portion corresponding to FIG. First, a lead frame 1 made of a copper alloy that has been externally processed by etching.
The entire surface of 10A is electrolytically degreased with an alkaline aqueous solution, washed with pure water, and then acid activated to remove the oxide film formed on the surface with an acid solution to remove the surface of the copper alloy that is the lead frame material 120. It was activated and washed again with pure water.
(FIG. 3A) Copper plating was applied to the entire surface of the lead frame 110A.
(FIG. 3B) Copper plating was performed at a liquid temperature of 50 ° C. for about 20 seconds to form copper cyanide to a thickness of about 0.1 μm. Then
Partial silver plating 150 having a thickness of 3.0 μm was applied to a predetermined portion of the surface of the lead frame 110A on which the copper plating 130 was applied by a partial plating method in which a plating solution was sprayed onto the lead frame using a masking jig. (FIG. 3C) After that, when the partial silver plating 150 is applied, unnecessary silver plating 150A may be formed. Therefore, the unnecessary silver plating 150A is removed to make the silver plating 150 uniform. Therefore, electrolytic peeling was performed. (Fig. 3 (d))

【００１８】次に、このようにして部分めっき１５０が
施されたリードフレーム１１０Ａに対し、所定の部分に
無電解銅めっきを還元剤として次亜リン酸塩を用いて、
厚さ０．５μｍの厚さに施し、表面部の粗さがＲａを
０．０７とした。（図３（ｅ）） この無電解銅めっき工程は、先ず、図３（ｄ）のよう
に、銅電解剥離処理が行われたリードフレーム１１０Ａ
を、無電解銅めっきの前処理として、５０°Ｃの酸性の
水溶液（荏原ユージライト社製 ＰＢ−２４１）で洗浄
し、２５°Ｃの濃硫酸で表面を活性化し、２５°ＣのＰ
ｄ含有処理液（荏原ユージライト社製 ＰＢ−３００）
に５分間程度浸漬し、銅合金材の表面部に無電解銅めっ
きの触媒となるＰｄ（パラジウム）を付与し、その後酸
性水溶液（荏原ユージライト社製ＰＢ−２４１）にて再
度表面を活性化し、７０°Ｃの無電解銅めっき浴で１０
分間処理し、無電解銅めっき１４０を０．５μｍの厚さ
で、銀めっき部以外の表面全体に設けた後、純水で１０
分間、超音波洗浄した。尚、無電解銅めっきは前述の通
り、還元剤として次亜リン酸塩を用いており、針状の粗
い結晶形態を形成し易く、またホルマリンを還元剤とす
るものに比較して、析出速度が早いものである。上記無
電解銅めっき浴は、めっき浴１ｌ当たり、硫酸銅１０
ｇ、硫酸ニッケル１ｇ、次亜リン酸ナトリウム２０ｇを
含有するもので、ｐＨは９である。Next, with respect to the lead frame 110A thus partially plated 150, electroless copper plating is used as a reducing agent at a predetermined portion with hypophosphite,
The thickness was 0.5 μm, and the surface roughness Ra was 0.07. (FIG. 3 (e)) In this electroless copper plating step, first, as shown in FIG. 3 (d), the lead frame 110A subjected to the electrolytic copper stripping treatment is performed.
Was washed with an acidic aqueous solution at 50 ° C (PB-241 manufactured by Ebara-Udylite Co., Ltd.) as a pretreatment for electroless copper plating, and the surface was activated with concentrated sulfuric acid at 25 ° C to obtain P at 25 ° C.
d-containing treatment liquid (PB-300 manufactured by Ebara Eugelite Co., Ltd.)
For 5 minutes, apply Pd (palladium) as a catalyst for electroless copper plating to the surface of the copper alloy material, and then activate the surface again with an acidic aqueous solution (PB-241 manufactured by Ebara Eugelite Co., Ltd.). 10 at 70 ° C electroless copper plating bath
After processing for minutes, electroless copper plating 140 having a thickness of 0.5 μm is provided on the entire surface except the silver-plated portion, and then pure water is applied to 10 μm.
Ultrasonic cleaning was performed for a minute. Incidentally, as described above, the electroless copper plating uses hypophosphite as a reducing agent, easily forms a needle-like rough crystal morphology, and has a deposition rate higher than that using formalin as a reducing agent. Is fast. The electroless copper plating bath contains 10 parts of copper sulfate per liter of plating bath.
g, nickel sulfate 1 g, and sodium hypophosphite 20 g, and the pH is 9.

【００１９】次に、本発明のリードフレーム部材の実施
例を挙げ、図に基づいて説明する。図２は、本実施例の
リードフレーム部材を示したもので、図２（ｂ）はその
平面図で、図２（ａ）はＡ３−Ａ４に於ける断面の要部
拡大図である。図２中、２００はリードフレーム部材、
２１０はリードフレーム、２１２はインナーリード、２
１３はアウターリード、２１４はダムバー、２１５はフ
レーム、２１６は吊りバー、２２０はリードフレーム素
材（銅合金）、２３０は銅めっき、２４０は無電解銅め
っき、２５０は（部分）銀めっき、２６０は放熱板、２
７０は接着剤層である。本実施例のリードフレーム部材
２００は、リードフレーム２１０と放熱板２６０とを別
体とするもので、リードフレーム１１０にはダイパッド
を設けておらず、図２（ｂ）に示すように、放熱板２６
０を接着剤層２７０で固定したものであるが、放熱板の
全表面に、銅めっき２３０を介して無電解銅めっき２４
０を、その表面部の粗さをＪＩＳ規格 Ｂ０６０１のＲ
ａを０．０７μｍとし設けたものである。このため、半
導体装置を作製する際、無電解銅めっき２４０部におい
て封止用樹脂とのデラミネーション（剥離）がおきずら
いものとしている。尚、Ｒａとしては０．０５〜０．１
０が好ましい。本実施例は、リードフレーム材として、
厚さ０．１５ｍｍの銅合金材（古河電気工業株式会社製
ＥＦＴＥＣ６４Ｔ−１／２Ｈ材）からエッチング加工に
より図２（ｂ）のような形状に外形加工されたリードフ
レーム素材２２０と、銅合金からなる放熱板２６０とを
絶縁性の接着フィルムからなる接着材層２７０で貼り付
けたものである。絶縁性の接着フィルムは熱硬化型両面
接着フィルム（巴川製紙所製 ＵＸ１Ｗ）からなり、１
５０°Ｃのヒートブロックにてリードフレーム２１０に
放熱板２６０を熱圧着したものである。Next, an example of the lead frame member of the present invention will be given and described with reference to the drawings. 2A and 2B show a lead frame member of this embodiment, FIG. 2B is a plan view thereof, and FIG. 2A is an enlarged view of a main part of a cross section taken along A3-A4. In FIG. 2, 200 is a lead frame member,
210 is a lead frame, 212 is an inner lead, 2
13 is an outer lead, 214 is a dam bar, 215 is a frame, 216 is a hanging bar, 220 is a lead frame material (copper alloy), 230 is copper plating, 240 is electroless copper plating, 250 is (partial) silver plating, 260 is Heat sink, 2
70 is an adhesive layer. In the lead frame member 200 of this embodiment, the lead frame 210 and the heat radiating plate 260 are separately provided, and the lead frame 110 is not provided with a die pad. As shown in FIG. 26
0 is fixed by the adhesive layer 270, but the electroless copper plating 24 is provided on the entire surface of the heat dissipation plate via the copper plating 230.
0 is the surface roughness of JIS standard B0601 R
a is set to 0.07 μm. For this reason, when manufacturing a semiconductor device, delamination (peeling) from the encapsulating resin is difficult to occur in the 240 parts of the electroless copper plating. In addition, as Ra, 0.05 to 0.1
0 is preferred. In this embodiment, as a lead frame material,
A lead frame material 220 externally processed into a shape as shown in FIG. 2B by etching from a copper alloy material (EFTEC64T-1 / 2H material manufactured by Furukawa Electric Co., Ltd.) having a thickness of 0.15 mm and a copper alloy. The heat radiation plate 260 is adhered by an adhesive layer 270 made of an insulating adhesive film. The insulating adhesive film is a thermosetting double-sided adhesive film (UX1W made by Tomoegawa Paper Co., Ltd.).
A heat radiation plate 260 is thermocompression bonded to the lead frame 210 by a heat block at 50 ° C.

【００２０】次に、本実施例のリードフレーム部材２０
０の組立方法図４に基づいて簡単に説明しておく。先
ず、銅めっき１３０、部分銀めっき２５０が順次施され
たリードフレーム２１０（図４（ａ）に対し、インナー
リード２１２のワイヤボンディング面でない側の面に絶
縁性のフィルムからなる接着材層２７０を貼り付ける。
（図４（ｂ）） この後、１５０°Ｃのヒートブロックにて、無電解銅め
っき２４０をその表面全体に設けた放熱板２６０を熱圧
着する。（図４（ｃ））Next, the lead frame member 20 of the present embodiment.
Assembling method of 0 will be briefly described with reference to FIG. First, an adhesive layer 270 made of an insulating film is provided on the surface of the inner lead 212 other than the wire bonding surface with respect to the lead frame 210 (FIG. 4A) sequentially subjected to the copper plating 130 and the partial silver plating 250. paste.
(FIG. 4B) After that, a heat dissipation plate 260 having electroless copper plating 240 provided on the entire surface thereof is thermocompression bonded by a heat block at 150 ° C. (FIG. 4 (c))

【００２１】尚、銅合金材からなる放熱板２６０に対す
る無電解銅めっき２４０は、図３に示す本発明のリード
フレームのめっき方法と同じように、銅めっき２３０を
放熱板の全表面に０．１μｍの厚さで設けた後に、同様
にして無電解銅めっき２４０を０．５μｍの厚さに設
け、その表面の粗さＲａを０．０７とした。The electroless copper plating 240 on the heat dissipation plate 260 made of a copper alloy material is the same as in the lead frame plating method of the present invention shown in FIG. After being provided with a thickness of 1 μm, electroless copper plating 240 was similarly provided with a thickness of 0.5 μm, and the surface roughness Ra was 0.07.

【００２２】次に、本発明の樹封止型半導体装置の実施
例を挙げて図に基づいて説明する。図５は本発明の樹封
止型半導体装置の実施例１を示した断面図で、図６は本
発明の樹封止型半導体装置の実施例２を示した断面図で
ある。図５に示す実施例１は、図１に示す実施例１のリ
ードフレームを用いたもので、図６に示す実施例２は、
図２に示す実施例２のリードフレーム部材を用いたもの
である。図５、図６中、３００、３００Ａは半導体装
置、３１０は半導体素子、３１１は電極パッド（端
子）、３２０は銀ペースト、３３０はワイヤ、３４０は
封止用樹脂である。Next, an embodiment of the tree-sealed semiconductor device of the present invention will be described with reference to the drawings. 5 is a sectional view showing a first embodiment of the tree-sealed semiconductor device of the present invention, and FIG. 6 is a sectional view showing a second embodiment of the tree-sealed semiconductor device of the present invention. Example 1 shown in FIG. 5 uses the lead frame of Example 1 shown in FIG. 1, and Example 2 shown in FIG.
The lead frame member of Example 2 shown in FIG. 2 is used. 5 and 6, 300 and 300A are semiconductor devices, 310 is a semiconductor element, 311 is an electrode pad (terminal), 320 is silver paste, 330 is a wire, and 340 is a sealing resin.

【００２３】図５、図６に示す半導体装置は、いずれも
通常の工程にて作製されるものであり、念のため、簡単
に図５に示す半導体装置３００の製造方法を図７に基づ
いて説明しておく。先ず、図１に示す、リードフレーム
１１０のダイパッド１１１をダウンセット加工し（図７
（ａ））、ダイパッド１１１上に銀ペースト３２０を介
して、半導体素子３１０を接合する。（図７（ｂ）） 次いで、銀ペースト３２０を加熱キュア後、半導体素子
３１０の電極パッド（端子）３１１とリードフレーム１
１０の部分銀めっき１５０が施されたインナーリード１
１２の先端とをワイヤ３３０でワイヤボンディングして
電気的に結線する。（図７（ｃ）） 次いで、封止用樹脂３４０にて樹脂封止した後、ダムバ
ー１１４（図１（ｂ））の除去やアウターリード１１３
（図１（ｂ））のフオーミング処理、半田めっきを経
て、半導体装置３００を得る。（図７（ｄ）） 図６に示す半導体装置３００Ａの場合もほぼ同様にして
作製される。The semiconductor devices shown in FIGS. 5 and 6 are all manufactured in a normal process, and as a precaution, a method for manufacturing the semiconductor device 300 shown in FIG. 5 will be briefly described based on FIG. I will explain. First, the die pad 111 of the lead frame 110 shown in FIG. 1 is downset processed (see FIG.
(A)) The semiconductor element 310 is bonded onto the die pad 111 via the silver paste 320. (FIG. 7B) Next, after the silver paste 320 is heated and cured, the electrode pad (terminal) 311 of the semiconductor element 310 and the lead frame 1 are formed.
Inner lead 1 with 10 partial silver plating 150
The tip of the wire 12 is wire-bonded with a wire 330 to be electrically connected. (FIG. 7C) Next, after sealing with a sealing resin 340, the dam bar 114 (FIG. 1B) is removed and the outer leads 113 are removed.
The semiconductor device 300 is obtained through the forming process (FIG. 1B) and solder plating. (FIG. 7D) The semiconductor device 300A shown in FIG. 6 is also manufactured in substantially the same manner.

【００２４】次に、上記図５、図６に示す半導体装置３
００、３００Ａについて、温度８５°Ｃ、湿度８５％の
恒温槽で環境試験を実施した後、加熱炉によりリフロー
試験を行ってみた。結果は、４８時間の環境試験を実施
しても、図１に示すリードフレームを用いた図５に示す
半導体装置、図２に示すリードフレーム部材を用いた図
６に示す半導体装置３００Ａにパッケージクラックはみ
られなかった。Next, the semiconductor device 3 shown in FIGS.
For 00 and 300A, after performing an environmental test in a constant temperature bath at a temperature of 85 ° C. and a humidity of 85%, a reflow test was performed using a heating furnace. As a result, even after conducting the environmental test for 48 hours, the semiconductor device 300 shown in FIG. 5 using the lead frame shown in FIG. 1 and the semiconductor device 300A shown in FIG. 6 using the lead frame member shown in FIG. I couldn't see it.

【００２５】[0025]

【発明の効果】本発明は、上記のように、ＩＣの組み立
て条件によらず、リードフレーム表面の銅酸化膜生成に
起因するデラミネーションの発生を防止でき、且つ、ボ
ンディング性を損なわない銅合金製の樹脂封止型半導体
装置用のリードフレーム、およびリードフレーム部材の
提供を可能としており、これにより、デラミネーション
の発生を防止できる樹脂封止型半導体装置の提供も可能
としている。As described above, the present invention can prevent the occurrence of delamination due to the formation of a copper oxide film on the surface of a lead frame regardless of the IC assembly conditions, and does not impair the bondability of the copper alloy. It is possible to provide a lead frame and a lead frame member for a resin-encapsulated semiconductor device made of resin, and thus it is also possible to provide a resin-encapsulated semiconductor device that can prevent the occurrence of delamination.

【図面の簡単な説明】[Brief description of drawings]

【図１】実施例のリードフレームの概略図FIG. 1 is a schematic diagram of a lead frame according to an embodiment.

【図２】実施例のリードフレーム部材の概略図FIG. 2 is a schematic view of a lead frame member of the embodiment.

【図３】実施例のリードフレームのめっき工程図FIG. 3 is a process drawing of the lead frame plating of the embodiment.

【図４】実施例のリードフレーム部材の組立を説明する
ための図形FIG. 4 is a diagram for explaining assembly of the lead frame member of the embodiment.

【図５】実施例１の半導体装置の断面図FIG. 5 is a sectional view of the semiconductor device according to the first embodiment.

【図６】実施例２の半導体装置の断面図FIG. 6 is a sectional view of a semiconductor device according to a second embodiment.

【図７】半導体装置の製造工程図FIG. 7 is a manufacturing process diagram of a semiconductor device.

【図８】従来のリードフレームの部分銀めっきとめっき
工程を説明するための図FIG. 8 is a diagram for explaining a partial silver plating of a conventional lead frame and a plating process.

【図９】半導体装置とリードフレームを説明するための
図FIG. 9 is a diagram for explaining a semiconductor device and a lead frame.

【符号の説明】[Explanation of symbols]

１１０、２１０ リードフレーム １１１、２１１ ダイパッド １１２、２１２ インナーリード １１３、２１３ アウターリード １１４、２１４ ダムバー １１５、２１５ フレーム １１６、２１６ 吊りバー １２０、２２０ リードフレーム素材（銅合
金） １３０、２３０ 銅めっき １４０、２４０ 無電解銅めっき １５０、２５０ （部分）銀めっき ２００ リードフレーム部材 ２６０ 放熱板 ２７０ 接着剤層 ３００、３００Ａ 半導体装置 ３１０ 半導体素子 ３１１ 電極パッド（端子） ３２０ 銀ペースト ３３０ ワイヤ ３４０ 封止用樹脂 ８００ 半導体装置 ８１０ 半導体素子 ８１１ 端子（パッド） ８２０ リードフレーム ８２１ ダイパッド ８２２ インナーリード ８２３ アウターリード ８２４ ダムバー ８２５ フレーム（枠）部 ８３０ ワイヤ ８４０ 樹脂110, 210 Lead frame 111, 211 Die pad 112, 212 Inner lead 113, 213 Outer lead 114, 214 Dam bar 115, 215 Frame 116, 216 Hanging bar 120, 220 Lead frame material (copper alloy) 130, 230 Copper plating 140, 240 Electroless copper plating 150, 250 (partial) silver plating 200 lead frame member 260 heat dissipation plate 270 adhesive layer 300, 300A semiconductor device 310 semiconductor element 311 electrode pad (terminal) 320 silver paste 330 wire 340 sealing resin 800 semiconductor device 810 Semiconductor element 811 Terminal (pad) 820 Lead frame 821 Die pad 822 Inner lead 823 Outer lead 824 Dam bar 825 Frame portion 830 Layer 840 resin

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 銅合金材からなり、半導体素子が搭載さ
れるダイパッドを備え、ワイヤボンディング用ないしダ
イボンディング用の部分貴金属めっきが施された樹脂封
止型の半導体装置用リードフレームであって、少なくと
も半導体素子を搭載する側でないダイパッド裏面の表面
に、ＪＩＳ規格 Ｂ０６０１の表面の粗さＲａが０．０
５〜０．１μｍの粗さに無電解銅めっきを施してあるこ
とを特徴とするリードフレーム。1. A resin-encapsulated lead frame for a semiconductor device, which is made of a copper alloy material and has a die pad on which a semiconductor element is mounted, and which is subjected to partial precious metal plating for wire bonding or die bonding. At least the surface roughness Ra of JIS standard B0601 is 0.0 on the surface of the back surface of the die pad that is not the side on which the semiconductor element is mounted.
A lead frame characterized by having electroless copper plating with a roughness of 5 to 0.1 μm. 【請求項２】 請求項１における、無電解銅めっきが次
亜リン酸塩を還元剤とするものであることを特徴とする
リードフレーム。2. The lead frame according to claim 1, wherein the electroless copper plating uses hypophosphite as a reducing agent. 【請求項３】 ワイヤボンディング用の部分貴金属めっ
きが施されたリードフレームと、半導体搭載部となる放
熱板とを備えた樹脂封止型の半導体装置用リードフレー
ム部材であって、少なくとも半導体素子が搭載される放
熱板の半導体素子を搭載する側でない面の表面に、ＪＩ
Ｓ規格 Ｂ０６０１の表面の粗さＲａが０．０５〜０．
１μｍの粗さに無電解銅めっきを施してあることを特徴
とするリードフレーム部材。3. A resin-encapsulated lead frame member for a semiconductor device, comprising a lead frame for wire bonding, which is partially plated with a noble metal, and a heat sink serving as a semiconductor mounting portion, wherein at least a semiconductor element is provided. On the surface of the heat sink to be mounted, which is not the side on which the semiconductor element is mounted, JI
The surface roughness Ra of the S standard B0601 is 0.05 to 0.
A lead frame member having electroless copper plating with a roughness of 1 μm. 【請求項４】 請求項３における、無電解銅めっきが次
亜リン酸塩を還元剤とするものであることを特徴とする
リードフレーム部材。4. The lead frame member according to claim 3, wherein the electroless copper plating uses hypophosphite as a reducing agent. 【請求項５】 銅合金材からなり、半導体素子が搭載さ
れるダイパッドを備え、ワイヤボンディング用ないしダ
イボンディング用の部分貴金属めっきが施されたリード
フレームで、少なくとも半導体素子を搭載する側でない
ダイパッド裏面の表面に、ＪＩＳ規格 Ｂ０６０１の表
面の粗さＲａが０．０５〜０．１μｍの粗さに無電解銅
めっきを施してあるリードフレームを用いたことを特徴
とする樹脂封止型半導体装置。5. A back surface of a die pad, which is made of a copper alloy material and has a die pad on which a semiconductor element is mounted, and which is plated with a partial noble metal for wire bonding or die bonding, and at least not on the side on which the semiconductor element is mounted. A resin-encapsulated semiconductor device, characterized in that a lead frame having a surface roughness Ra of JIS standard B0601 plated with electroless copper to a roughness of 0.05 to 0.1 μm is used on the surface. 【請求項６】 ワイヤボンディング用の部分貴金属めっ
きが施されたリードフレームと、半導体搭載部となる放
熱板とを備えたリードフレーム部材で、少なくとも半導
体素子が搭載される放熱板の半導体素子を搭載する側で
ない面の表面に、ＪＩＳ規格 Ｂ０６０１の表面の粗さ
Ｒａが０．０５〜０．１μｍの粗さに無電解銅めっきを
施してあるリードフレーム部材を用いたことを特徴とす
る樹脂封止型半導体装置。6. A lead frame member comprising a lead frame for partially bonding a wire for wire bonding and a heat radiating plate serving as a semiconductor mounting portion, at least a semiconductor element of a heat radiating plate on which a semiconductor element is mounted is mounted. A resin encapsulation characterized by using a lead frame member having electroless copper plating with a surface roughness Ra of JIS standard B0601 of 0.05 to 0.1 μm on the surface not on the side to be treated. Static semiconductor device.
JP8168709A 1996-06-10 1996-06-10 Lead frame, lead frame member and resin sealed semiconductor device employing them Withdrawn JPH09331009A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8168709A JPH09331009A (en) 1996-06-10 1996-06-10 Lead frame, lead frame member and resin sealed semiconductor device employing them

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8168709A JPH09331009A (en) 1996-06-10 1996-06-10 Lead frame, lead frame member and resin sealed semiconductor device employing them

Publications (1)

Publication Number Publication Date
JPH09331009A true JPH09331009A (en) 1997-12-22

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JP8168709A Withdrawn JPH09331009A (en) 1996-06-10 1996-06-10 Lead frame, lead frame member and resin sealed semiconductor device employing them

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1480270A2 (en) 2003-05-22 2004-11-24 Shinko Electric Industries Co., Ltd. Packaging component and semiconductor package
JP2013016603A (en) * 2011-07-03 2013-01-24 Toyota Motor Corp Semiconductor device and manufacturing method of the same
JP2014099637A (en) * 2009-03-12 2014-05-29 Lg Innotek Co Ltd Lead frame and method for manufacturing the same
JP2014192202A (en) * 2013-03-26 2014-10-06 Toyota Motor Corp Semiconductor device and manufacturing method of the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1480270A2 (en) 2003-05-22 2004-11-24 Shinko Electric Industries Co., Ltd. Packaging component and semiconductor package
EP1480270A3 (en) * 2003-05-22 2005-07-13 Shinko Electric Industries Co., Ltd. Packaging component and semiconductor package
US7190057B2 (en) 2003-05-22 2007-03-13 Shinko Electric Industries Co., Ltd. Packaging component and semiconductor package
JP2014099637A (en) * 2009-03-12 2014-05-29 Lg Innotek Co Ltd Lead frame and method for manufacturing the same
JP2013016603A (en) * 2011-07-03 2013-01-24 Toyota Motor Corp Semiconductor device and manufacturing method of the same
JP2014192202A (en) * 2013-03-26 2014-10-06 Toyota Motor Corp Semiconductor device and manufacturing method of the same

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Effective date: 20030902