JPH06302756A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH06302756A JPH06302756A JP11369993A JP11369993A JPH06302756A JP H06302756 A JPH06302756 A JP H06302756A JP 11369993 A JP11369993 A JP 11369993A JP 11369993 A JP11369993 A JP 11369993A JP H06302756 A JPH06302756 A JP H06302756A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- plating layer
- core material
- plated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Chemically Coating (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に用いられ
るリードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame used for semiconductor devices.
【０００２】[0002]
【従来の技術】一般に半導体装置は、金属条材をプレス
加工あるいはエッチング等によって所定の形状に成形し
たリードフレームの半導体素子搭載部に、特定の半導体
素子を固定し、金属細線により半導体素子とインナーリ
ード端部をボンディングし、このボンディング部分及び
前記半導体素子を樹脂等により封止されていた。これに
使用される金属条材には、熱膨張係数の小さい鉄系合金
（ニッケル４２％、鉄５８％等）あるいは鉄系合金に比
べ加工性が良く、電気伝導及び熱伝導性に比較的優れた
銅合金からなる銅系合金が使用されていた。2. Description of the Related Art Generally, in a semiconductor device, a specific semiconductor element is fixed to a semiconductor element mounting portion of a lead frame formed by pressing a metal strip into a predetermined shape by etching or the like, and the semiconductor element and the inner portion are fixed with a thin metal wire. The ends of the leads are bonded, and the bonding portion and the semiconductor element are sealed with resin or the like. The metal strip used for this has better workability than iron-based alloys (42% nickel, 58% iron, etc.) or iron-based alloys with a small coefficient of thermal expansion, and has relatively excellent electrical and thermal conductivity. Copper-based alloys consisting of copper alloys were used.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、前記リ
ードフレームに使用する鉄系合金は、比較的に加工性が
悪く、高価であるという欠点がある。一方、銅系合金も
リードフレームに使用されているが、場合によって銅の
酸化物や硫化物、また他の反応生成物がリードフレーム
の表面に生じて、リードフレームの表面を褪色させてし
まい、そのはんだ性を低下させたりするという問題点が
ある。また、近年のように半導体素子の密度が上がる
と、小型化する場合には熱放散のよい銅系合金を使用す
ることが考えられるが、銅系合金を使用する場合にはマ
イグレーションが生じるので小型化が困難である。そこ
で本発明者は、リードフレームの他の素材として安価で
熱伝導がよいアルミまたはアルミ合金を使用することを
考え、リードフレームの適用性について鋭意研究し本発
明を完成した。本発明はこのような事情に鑑みてなされ
たもので、安価で加工性に優れ、しかも熱放散がよいア
ルミまたはアルミ合金を使用した半導体装置用リードフ
レームを提供することを目的とする。However, the iron-based alloy used for the lead frame has the drawbacks of relatively poor workability and high cost. On the other hand, copper-based alloys are also used for lead frames, but in some cases copper oxides and sulfides, and other reaction products are generated on the surface of the lead frame, causing the surface of the lead frame to fade, There is a problem that the solderability is lowered. In addition, as the density of semiconductor elements increases as in recent years, it is possible to use a copper-based alloy that has good heat dissipation in the case of miniaturization, but when using a copper-based alloy, migration occurs, so the size is reduced. Is difficult to convert. Therefore, the present inventor has considered the use of aluminum or an aluminum alloy, which is inexpensive and has good thermal conductivity, as another material for the lead frame, and has earnestly studied the applicability of the lead frame to complete the present invention. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a lead frame for a semiconductor device, which uses aluminum or an aluminum alloy, which is inexpensive, excellent in workability, and good in heat dissipation.
【０００４】[0004]
【課題を解決するための手段】前記目的に沿う請求項１
記載の半導体装置用リードフレームは、アルミまたはア
ルミ合金からなるリードフレーム芯材の表面の少なくと
もアウターリード部の外部回路端子に接続する領域に貴
金属めっきをしたことを特徴とする半導体装置用リード
フレーム。請求項２記載の半導体装置用リードフレーム
は、アルミまたはアルミ合金からなるリードフレーム芯
材の表面に下地めっきをした後、その表面の少なくとも
アウターリード部の外部回路端子に接続する領域に貴金
属めっきをして構成されている。請求項３記載の半導体
装置用リードフレームは、請求項１または２記載の半導
体装置用リードフレームにおいて、貴金属は、金、銀、
パラジウム、白金あるいはこれらの合金から構成されて
いる。請求項４記載の半導体装置用リードフレームは、
請求項１または２記載の半導体装置用リードフレームに
おいて、貴金属めっきは、０．１５μｍ以下の厚みで行
われるように構成されている。A method according to the above-mentioned object.
The lead frame for a semiconductor device described above is characterized in that at least a region of the surface of a lead frame core material made of aluminum or an aluminum alloy that is connected to an external circuit terminal of an outer lead portion is plated with a noble metal. In the lead frame for a semiconductor device according to claim 2, after plating the surface of the lead frame core material made of aluminum or aluminum alloy with the undercoat, at least a region of the surface to be connected to the external circuit terminal of the outer lead portion is plated with the noble metal. Is configured. The lead frame for a semiconductor device according to claim 3 is the lead frame for a semiconductor device according to claim 1 or 2, wherein the noble metal is gold, silver,
It is composed of palladium, platinum, or an alloy thereof. The lead frame for a semiconductor device according to claim 4,
In the lead frame for a semiconductor device according to claim 1 or 2, the noble metal plating is configured to have a thickness of 0.15 μm or less.
【０００５】[0005]
【作用】本発明に係る請求項１〜４記載の半導体装置用
リードフレームにおいては、リードフレーム芯材として
アルミまたはアルミ合金が用いられているので加工性が
極めてよく、また、熱伝導性もよい。そして、リードフ
レーム芯材の少なくともアウターリード部の外部回路端
子に接続する領域に貴金属めっきがなされ、必要に応じ
て下地めっきがなされているので、リードフレーム芯材
の腐食を防止できると共にはんだ付け性、ワイヤボンデ
ィング性を確保できる。In the lead frames for semiconductor devices according to the present invention according to the present invention, since aluminum or aluminum alloy is used as the core material of the lead frame, the workability is extremely good and the thermal conductivity is also good. . At least the area of the lead frame core material that connects to the external circuit terminals of the outer leads is plated with a noble metal, and if necessary, the underlying plating is applied, so corrosion of the lead frame core material can be prevented and solderability is improved. The wire bondability can be secured.
【０００６】[0006]
【実施例】続いて、添付した図面を参照しつつ、本発明
を具体化した実施例につき説明し、本発明の理解に供す
る。ここに、図１は本発明の第１の実施例に係る半導体
装置用リードフレームを用いた半導体装置の要部断面
図、図２は本発明の第２の実施例に係る半導体装置用リ
ードフレームを用いた半導体装置の要部断面図、図３は
本発明の第３の実施例に係る半導体装置用リードフレー
ムを用いた半導体装置の要部断面図である。Embodiments of the present invention will now be described with reference to the accompanying drawings to provide an understanding of the present invention. 1 is a cross-sectional view of a main portion of a semiconductor device using a semiconductor device lead frame according to a first embodiment of the present invention, and FIG. 2 is a semiconductor device lead frame according to a second embodiment of the present invention. FIG. 3 is a cross-sectional view of an essential part of a semiconductor device using a semiconductor device and FIG. 3 is a cross-sectional view of an essential part of a semiconductor device using a semiconductor device lead frame according to a third embodiment of the present invention.
【０００７】図１に示すように、本発明の第１の実施例
に係る半導体装置用リードフレーム１０は、先ず、比較
的に熱伝導性に優れたアルミまたはアルミ合金（以下、
単にアルミ合金という）の芯材をプレスにより半導体素
子搭載部１１、インナーリード部１２、アウターリード
部１３を備えた所定の形状に加工する。加工性は従来の
鉄系芯材、銅系芯材等よりも良く、かえり等が少ない。
このリードフレーム１０をアルカリ脱脂、電解脱脂等の
脱脂を行って、プレス工程で金属表面に付着している油
性の汚れをとり、次に、金属表面の酸化物、水酸化物お
よびその他の金属塩類を酸洗して除去する。As shown in FIG. 1, a lead frame 10 for a semiconductor device according to a first embodiment of the present invention is formed of aluminum or aluminum alloy (hereinafter,
A core material (simply referred to as an aluminum alloy) is processed into a predetermined shape including a semiconductor element mounting portion 11, an inner lead portion 12, and an outer lead portion 13 by pressing. Workability is better than conventional iron-based core materials, copper-based core materials, etc., with less burr.
The lead frame 10 is degreased by alkali degreasing, electrolytic degreasing, etc. to remove oily stains adhering to the metal surface in the pressing step, and then oxides, hydroxides and other metal salts on the metal surface. Is pickled and removed.
【０００８】そして、例えば、亜鉛置換法（ジンケート
法）により酸処理を完了したアルミ合金のリードフレー
ム１０を活性化し、その後、直ちに貴金属めっきの一例
である金めっきでリードフレーム１０の全表面にめっき
して、金めっき層１４を形成する。この場合の金めっき
は経済性を考慮すれば厚み０．１５μｍ以下の薄めっき
をするのが好ましいが、めっき条件あるいはアルミ合金
心材の材質によっては、金めっき層に生ずるピンホール
等が内部を腐食し易い場合には、一層の厚めっき、複数
層の金めっき、あるいは他の異種貴金属（例えば、パラ
ジウム、銀、白金）めっきを行うのが好ましい（以下の
実施例においても同様）。Then, for example, the lead frame 10 of the aluminum alloy that has been subjected to the acid treatment by the zinc substitution method (zincate method) is activated, and immediately thereafter, the entire surface of the lead frame 10 is plated with gold plating, which is an example of precious metal plating. Then, the gold plating layer 14 is formed. In consideration of economical efficiency, it is preferable that the gold plating in this case be a thin plating with a thickness of 0.15 μm or less. However, depending on the plating conditions or the material of the aluminum alloy core material, pinholes etc. generated in the gold plating layer corrode the inside. When it is easy to perform, it is preferable to perform one-layer thick plating, a plurality of layers of gold plating, or other different noble metal (for example, palladium, silver, platinum) plating (also in the following examples).
【０００９】そして、このリードフレーム１０を使用し
て半導体装置１５を完成する場合には、めっきが完了し
たリードフレーム１０の半導体素子搭載部１１に半導体
素子１６を接着剤１７で固定し、インナーリード部１２
端部と半導体素子１６の電極パッド１８とをアルミ線１
９の金属細線でボンディングし、エポキシ２０等の樹脂
で封止し、その後、必要によりアウターリード部１３を
はんだ浴に浸漬してはんだめっきをする。When the semiconductor device 15 is completed by using the lead frame 10, the semiconductor element 16 is fixed to the semiconductor element mounting portion 11 of the lead frame 10 on which the plating has been completed with the adhesive 17, and the inner lead is formed. Part 12
The end portion and the electrode pad 18 of the semiconductor element 16 are connected to the aluminum wire 1
Bonding is performed with a thin metal wire 9 and sealed with a resin such as epoxy 20. Thereafter, if necessary, the outer lead portion 13 is immersed in a solder bath for solder plating.
【００１０】次に、図２に示すように、本発明の第２の
実施例に係る半導体装置用リードフレーム２１は、第１
の実施例と同様に、アルミ合金の芯材がプレスにより所
定形状に加工される。そして脱脂、酸洗い等の処理が施
され、さらに、亜鉛置換法によりリードフレーム２１が
活性化され、その後、直ちにニッケル等のストライクめ
っきが施され、下地めっき層２２が形成される。そし
て、アウターリード部１３の少なくとも外部回路端子に
接続する領域（図２においてはアウターリード部１３全
体にめっきしている）の下地めっき層２２の上に貴金属
めっきの一例であるパラジュウム（Ｐｄ）でめっきし
て、パラジュウムめっき層２３を形成する。この場合、
パラジウムのめっき厚も経済性を考慮すれば、０．１５
μｍ以下であることが好ましいが、ピンホール等によっ
て内部のアルミ合金が腐食する場合には、厚めっき、多
層めっきを行うことは、前記第１の実施例と同様であ
る。そして、このリードフレーム２１を使用して半導体
装置２４を完成する場合には、第１の実施例の場合と同
様な方法でワイヤボンディング、樹脂封止及び必要によ
りはんだめっきを施して半導体装置２４を完成する。Next, as shown in FIG. 2, a semiconductor device lead frame 21 according to a second embodiment of the present invention is formed into a first lead frame 21.
In the same manner as in the above example, the aluminum alloy core material is processed into a predetermined shape by pressing. Then, treatments such as degreasing and pickling are performed, the lead frame 21 is activated by the zinc substitution method, and then strike plating of nickel or the like is immediately performed to form the base plating layer 22. Then, at least a region of the outer lead portion 13 that is connected to the external circuit terminal (in FIG. 2, the outer lead portion 13 is entirely plated) is coated with palladium (Pd), which is an example of precious metal plating, on the base plating layer 22. The palladium plating layer 23 is formed by plating. in this case,
Considering economic efficiency, the plating thickness of palladium is 0.15
The thickness is preferably not more than μm, but when the aluminum alloy inside is corroded by a pinhole or the like, thick plating and multilayer plating are performed as in the first embodiment. When the semiconductor device 24 is completed by using the lead frame 21, wire bonding, resin sealing, and solder plating if necessary are performed in the same manner as in the first embodiment to form the semiconductor device 24. Complete.
【００１１】更に、図３に示すように、本発明の第３の
実施例に係る半導体装置用リードフレーム２５は、第１
及び第２の実施例と同様に、アルミ合金の芯材がプレス
により所定形状に加工される。そして脱脂、酸洗い等の
処理が施され、例えば、亜鉛置換法により活性化され
て、その後、直ちにニッケル等のストライクめっきが行
われ、下地めっき層２６が形成される。前記下地めっき
層２６が形成されたリードフレーム２５の表面全面に金
の貴金属めっきを施して、金めっき層２７を形成する。
そして、このリードフレーム２５を使用して半導体装置
２８を完成する場合には、第１及び第２の実施例の場合
と同様な方法で行い半導体装置２８を完成する。以上の
ように、アルミ合金を芯材に使用しているので、熱伝導
性に優れた半導体装置用リードフレームが可能となり、
高密度の半導体素子あるいは熱を発散する半導体装置が
製作できる。Further, as shown in FIG. 3, a lead frame 25 for a semiconductor device according to a third embodiment of the present invention is a first lead frame 25.
Similarly to the second embodiment, the aluminum alloy core material is pressed into a predetermined shape. Then, treatments such as degreasing and pickling are performed, activated by, for example, a zinc substitution method, and then strike plating of nickel or the like is immediately performed to form the base plating layer 26. The entire surface of the lead frame 25 on which the base plating layer 26 is formed is plated with gold noble metal to form a gold plating layer 27.
Then, when the semiconductor device 28 is completed by using the lead frame 25, the semiconductor device 28 is completed by the same method as in the first and second embodiments. As described above, since the aluminum alloy is used as the core material, a lead frame for a semiconductor device having excellent thermal conductivity becomes possible,
A high-density semiconductor element or a semiconductor device that dissipates heat can be manufactured.
【００１２】なお、本実施例では貴金属めっきは金およ
びパラジュウムを使用したが、銀、白金あるいはこれら
の合金等であってもよい。本実施例では芯材としてアル
ミ合金を用いたが、アルミであってもよい。本実施例で
はアルミ合金の活性化の方法として亜鉛置換法を用いた
が、その外に亜鉛−ニッケル合金置換法、陽極酸化法、
化学めっき法等がある。本実施例ではワイヤボンディン
グ用の金属細線としてアルミ線を使用したが金線でもよ
く、また、樹脂封止の樹脂としてエポキシを用いたが、
セラミック等のように別の素材でも可能である。そし
て、リードフレームの成形はプレスによって行われた
が、エッチング等によっても成形可能である。Although gold and palladium are used for the precious metal plating in this embodiment, silver, platinum or alloys thereof may be used. Although an aluminum alloy is used as the core material in this embodiment, aluminum may be used. In this embodiment, the zinc substitution method was used as a method for activating the aluminum alloy, but in addition to this, a zinc-nickel alloy substitution method, an anodizing method,
There are chemical plating methods. Although an aluminum wire is used as the thin metal wire for wire bonding in this embodiment, a gold wire may be used, and epoxy is used as the resin for resin sealing.
Other materials such as ceramics are also possible. The lead frame is formed by pressing, but it can be formed by etching or the like.
【００１３】[0013]
【発明の効果】請求項１〜４記載の半導体装置用リード
フレームにおいては、リードフレーム芯材としてアルミ
またはアルミ合金を用いているので熱伝導がよい。従っ
て、高密度の半導体素子あるいはその他熱を発散する半
導体装置に使用できる。また、そのリードフレームの少
なくともアウターリード部の外部回路端子に接続する領
域に貴金属めっきをしているので、内部のアルミの腐食
が防止され、更には、はんだ付けが向上する。In the lead frame for a semiconductor device according to the first to fourth aspects, the heat conduction is good because aluminum or aluminum alloy is used as the lead frame core material. Therefore, it can be used for high-density semiconductor elements or other semiconductor devices that dissipate heat. Further, since at least the area of the outer lead portion of the lead frame, which is connected to the external circuit terminal, is plated with noble metal, corrosion of the internal aluminum is prevented, and furthermore, soldering is improved.
【図１】本発明の第１の実施例に係る半導体装置用リー
ドフレームを用いた半導体装置の要部断面図である。FIG. 1 is a cross-sectional view of essential parts of a semiconductor device using a semiconductor device lead frame according to a first embodiment of the present invention.
【図２】本発明の第２の実施例に係る半導体装置用リー
ドフレームを用いた半導体装置の要部断面図である。FIG. 2 is a cross-sectional view of essential parts of a semiconductor device using a lead frame for a semiconductor device according to a second embodiment of the present invention.
【図３】本発明の第３の実施例に係る半導体装置用リー
ドフレームを用いた半導体装置の要部断面図である。FIG. 3 is a cross-sectional view of essential parts of a semiconductor device using a lead frame for a semiconductor device according to a third embodiment of the present invention.
１０ リードフレーム １１ 半導体素子搭載部 １２ インナーリード部 １３ アウターリード部 １４ 金めっき層 １５ 半導体装置 １６ 半導体素子 １７ 接着剤 １８ 電極パッド １９ アルミ線 ２０ エポキシ ２１ リードフレーム ２２ 下地めっき層 ２３ パラジュウムめっき層 ２４ 半導体装置 ２５ リードフレーム ２６ 下地めっき層 ２７ 金めっき層 ２８ 半導体装置 10 Lead Frame 11 Semiconductor Element Mounting Part 12 Inner Lead Part 13 Outer Lead Part 14 Gold Plating Layer 15 Semiconductor Device 16 Semiconductor Element 17 Adhesive 18 Electrode Pad 19 Aluminum Wire 20 Epoxy 21 Lead Frame 22 Base Plating Layer 23 Palladium Plating Layer 24 Semiconductor Device 25 Lead frame 26 Base plating layer 27 Gold plating layer 28 Semiconductor device
Claims (4)
フレーム芯材の表面の少なくともアウターリード部の外
部回路接続端子に貴金属めっきをしたことを特徴とする
半導体装置用リードフレーム。1. A lead frame for a semiconductor device, wherein at least the outer circuit connecting terminal of the outer lead portion on the surface of a lead frame core material made of aluminum or aluminum alloy is plated with a noble metal.
フレーム芯材の表面に下地めっきをした後、その表面の
少なくともアウターリード部の外部回路端子に接続する
領域に貴金属めっきをしたことを特徴とする半導体装置
用リードフレーム。2. A semiconductor characterized in that a lead frame core material made of aluminum or an aluminum alloy is surface-plated, and then at least a region of the surface of the outer lead portion connected to an external circuit terminal is plated with a noble metal. Lead frame for equipment.
るいはこれらの合金からなる請求項１または２記載の半
導体装置用リードフレーム。3. The lead frame for a semiconductor device according to claim 1, wherein the noble metal is gold, silver, palladium, platinum, or an alloy thereof.
みで行われている請求項１または２記載の半導体装置用
リードフレーム。4. The lead frame for a semiconductor device according to claim 1, wherein the noble metal plating is performed with a thickness of 0.15 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11369993A JP2858196B2 (en) | 1993-04-17 | 1993-04-17 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11369993A JP2858196B2 (en) | 1993-04-17 | 1993-04-17 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06302756A true JPH06302756A (en) | 1994-10-28 |
| JP2858196B2 JP2858196B2 (en) | 1999-02-17 |
Family
ID=14618940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11369993A Expired - Fee Related JP2858196B2 (en) | 1993-04-17 | 1993-04-17 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2858196B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1037277A2 (en) | 1999-03-15 | 2000-09-20 | Texas Instruments Incorporated | Lead frame |
| US6747343B2 (en) | 2000-03-08 | 2004-06-08 | Texas Instruments Incorporated | Aluminum leadframes with two nickel layers |
| JP2006202938A (en) * | 2005-01-20 | 2006-08-03 | Kojiro Kobayashi | Semiconductor device and its manufacturing method |
| EP1992011A2 (en) * | 2006-02-02 | 2008-11-19 | Texas Instruments Incorporated | Aluminum leadframes for semiconductor qfn/son devices |
| KR20210008804A (en) * | 2019-07-15 | 2021-01-25 | 제엠제코(주) | Semiconductor package |
-
1993
- 1993-04-17 JP JP11369993A patent/JP2858196B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1037277A2 (en) | 1999-03-15 | 2000-09-20 | Texas Instruments Incorporated | Lead frame |
| US6518647B1 (en) * | 1999-03-15 | 2003-02-11 | Texas Instruments Incorporated | Plated aluminum leadframes for semiconductor devices, including two nickel layers, and method of fabrication |
| US6933177B2 (en) | 1999-03-15 | 2005-08-23 | Texas Instruments Incorporated | Aluminum leadframes for semiconductor devices and method of fabrication |
| KR100710090B1 (en) * | 1999-03-15 | 2007-04-25 | 텍사스 인스트루먼츠 인코포레이티드 | Aluminum leadframes for semiconductor devices and method of fabrication |
| US6747343B2 (en) | 2000-03-08 | 2004-06-08 | Texas Instruments Incorporated | Aluminum leadframes with two nickel layers |
| JP2006202938A (en) * | 2005-01-20 | 2006-08-03 | Kojiro Kobayashi | Semiconductor device and its manufacturing method |
| EP1992011A2 (en) * | 2006-02-02 | 2008-11-19 | Texas Instruments Incorporated | Aluminum leadframes for semiconductor qfn/son devices |
| EP1992011A4 (en) * | 2006-02-02 | 2011-08-31 | Texas Instruments Inc | Aluminum leadframes for semiconductor qfn/son devices |
| KR20210008804A (en) * | 2019-07-15 | 2021-01-25 | 제엠제코(주) | Semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2858196B2 (en) | 1999-02-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3760075B2 (en) | Lead frame for semiconductor packages | |
| EP1351295A2 (en) | Preplated stamped small outline no-lead leadframes having etched profiles | |
| US6664136B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2009526381A (en) | Aluminum lead frame for semiconductor QFN / SON devices | |
| JPH10237691A (en) | Multilayer plated lead frame | |
| JP2000277672A (en) | Lead frame, manufacture thereof, and semiconductor device | |
| JPS5948546B2 (en) | Metal strip for lead frame and its manufacturing method | |
| JP2000269398A (en) | Aluminum lead frame for semiconductor device and manufacture thereof | |
| US6853056B2 (en) | Semiconductor device having a base metal lead frame | |
| KR100702956B1 (en) | Lead frame for semiconductor package and the method for manufacturing the same | |
| JP2019041108A (en) | Substrate for power module and power module | |
| JP5069485B2 (en) | Metal base circuit board | |
| JP2858196B2 (en) | Lead frame for semiconductor device | |
| JPS6050343B2 (en) | Lead frame for semiconductor device manufacturing | |
| JP2005051084A (en) | Semiconductor chip and semiconductor device using this | |
| JPS59161850A (en) | Resin sealed type semiconductor device and lead frame used therefor | |
| JPH10284667A (en) | Material for electric electronic device component having superior corrosion resistance and oxidation resistance | |
| JPH07326701A (en) | Conductive material for electric-electronic part, lead frame and semiconductor integrated circuit using the same | |
| JPH01257356A (en) | Lead frame for semiconductor | |
| JP2002064173A (en) | Preplating of small-sized no-lead frame for semiconductors | |
| JPH0590465A (en) | Semiconductor device | |
| JP3402228B2 (en) | Semiconductor device having lead-free tin-based solder coating | |
| JPH10313087A (en) | Electronic part lead material | |
| TWI497670B (en) | Semiconductor devices based on aluminumalloy lead frame and fabricating method thereof | |
| JPH04137552A (en) | Lead frame |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20071204 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 10 Free format text: PAYMENT UNTIL: 20081204 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 10 Free format text: PAYMENT UNTIL: 20081204 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091204 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 12 Free format text: PAYMENT UNTIL: 20101204 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101204 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 13 Free format text: PAYMENT UNTIL: 20111204 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 13 Free format text: PAYMENT UNTIL: 20111204 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 14 Free format text: PAYMENT UNTIL: 20121204 |
|
| LAPS | Cancellation because of no payment of annual fees |