JP2004343136A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2004343136A
JP2004343136A JP2004199764A JP2004199764A JP2004343136A JP 2004343136 A JP2004343136 A JP 2004343136A JP 2004199764 A JP2004199764 A JP 2004199764A JP 2004199764 A JP2004199764 A JP 2004199764A JP 2004343136 A JP2004343136 A JP 2004343136A
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JP
Japan
Prior art keywords
plating
lead frame
copper
silver
noble metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004199764A
Other languages
Japanese (ja)
Inventor
Hideo Hotta
日出男 堀田
Chiaki Hatsuda
千秋 初田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP2004199764A priority Critical patent/JP2004343136A/en
Publication of JP2004343136A publication Critical patent/JP2004343136A/en
Pending legal-status Critical Current

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent delamination caused by lead frame from being generated, without being based on assembly condition of IC (integrated circuit), and which uses a lead frame made from copper alloy will does not impair bonding properties. <P>SOLUTION: The semiconductor device comprises the lead frame for a semiconductor device 200 of resin sealing type, consisting of a copper alloy material, and is treated by partial noble metal solder plating 140 consisting of at least one metal from among silver, gold or palladium for wire bonding or die bonding; and it is treated by a thin noble metal solder plating 150, consisting of at least one metal from among silver, gold or platinum on at least all or the designated portion of copper member surface of a side contacting with a sealing resin 190. In the semiconductor device, the density of the noble metal, which is measured by X-ray photoelectron spectroscopy, is higher than 0.1 atom% and lower than 20 atom%, in at least all or a forming region of a copper oxide film 130A of the prescribed 200 portions of a lead frame surface contacting with the resin for sealing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、封止樹脂とリードフレームとの密着性を向上させた樹脂封止型の半導体装置に関する。   The present invention relates to a resin-encapsulated semiconductor device having improved adhesion between a sealing resin and a lead frame.

従来より用いられている樹脂封止型の半導体装置（プラスチックリードフレームパッケージ）は、一般に図１０（ａ）に示されるような構造であり、半導体素子１０２０を搭載するダイパッド部１０１１や周囲の回路との電気的接続を行うためのアウターリード部１０１３、アウターリード部１０１３に一体となったインナーリード部１０１２、該インナーリード部１０１２の先端部と半導体素子１０２０の電極パッド（端子）１０２１とを電気的に接続するためのワイヤ１０３０、半導体素子１０２０を封止して外界からの応力、汚染から守る樹脂１０４０等からなっており、半導体素子１０２０をリードフレーム１０１０のダイパッド１０１１部等に搭載した後に、樹脂１０４０により封止してパッケージとしたもので、半導体素子１０２０の電極パッド１０２１に対応できる数のインナーリード１０１２を必要とするものである。
そして、このような樹脂封止型の半導体装置の組立部材として用いられる（単層）リードフレーム１０１０は、一般には図１０（ｂ）に示すような構造のもので、半導体素子を搭載するためのダイパッド１０１１と、ダイパッド１０１１の周囲に設けられた半導体素子と結線するためのインナーリード１０１２、該インナーリード１０１２に連続して外部回路との結線を行うためのアウターリード１０１３、樹脂封止する際のダムとなるダムバー１０１４、リードフレーム１０１０全体を支持するフレーム（枠）部１０１５等を備えており、通常、コバール、４２合金（４２％ニッケル−鉄合金）、銅系合金のような導電性に優れた金属を用い、プレス法もしくはエッチング法により外形加工されていた。
半導体素子と結線するためのインナーリード１０１２のワイヤボンディング領域には、銀めっきが必要とされ、一般には、外形加工後に、必要部のみに銀めっきを部分的に施していた。
また、銀ペースト等を介して半導体素子をダイボンディングする側のダイパッド１０１１表面にも銀めっきを必要とし、銀めっきを施していた。
特に、インナーリード１０１２のワイヤボンデイング領域やダイパッド１０１１のダイボンディング領域等の銀めっきが必要な領域のみへの銀めっきを、部分銀めっきと言っている。
尚、図１０（ｂ）（イ）はリードフレーム１０１０の平面図で、図１０（ｂ）（ロ）は、図１０（ｂ）（イ）のＦ１−Ｆ２における断面図である。 A resin-encapsulated semiconductor device (plastic lead frame package) conventionally used generally has a structure as shown in FIG. 10A, and includes a die pad 1011 on which a semiconductor element 1020 is mounted and a peripheral circuit. An outer lead portion 1013 for making electrical connection with the inner lead portion 1012, an inner lead portion 1012 integrated with the outer lead portion 1013, and a tip end of the inner lead portion 1012 and an electrode pad (terminal) 1021 of the semiconductor element 1020 are electrically connected. And a resin 1040 for sealing the semiconductor element 1020 to protect the semiconductor element 1020 from external stress and contamination. After the semiconductor element 1020 is mounted on the die pad 1011 portion of the lead frame 1010, the resin The package is sealed with 1040, and the semiconductor element 10 Those requiring the number of inner leads 1012 capable of handling 0 of the electrode pad 1021.
A (single-layer) lead frame 1010 used as an assembly member of such a resin-sealed semiconductor device generally has a structure as shown in FIG. 10B, and is used for mounting a semiconductor element. An inner lead 1012 for connecting the die pad 1011 to a semiconductor element provided around the die pad 1011; an outer lead 1013 for connecting the inner lead 1012 to an external circuit; A dam bar 1014 serving as a dam, a frame (frame) portion 1015 for supporting the entire lead frame 1010, and the like are provided, and are generally excellent in conductivity such as Kovar, 42 alloy (42% nickel-iron alloy), and copper alloy. The outer shape was processed by a pressing method or an etching method using the metal.
Silver plating is required in the wire bonding area of the inner lead 1012 for connection with the semiconductor element, and generally, only the necessary portions are partially plated after the external processing.
Further, the surface of the die pad 1011 on the side where the semiconductor element is die-bonded via a silver paste or the like also needs silver plating, and is silver-plated.
In particular, silver plating only in a region requiring silver plating such as a wire bonding region of the inner lead 1012 and a die bonding region of the die pad 1011 is referred to as partial silver plating.
10B and 10A are plan views of the lead frame 1010, and FIGS. 10B and 10B are cross-sectional views taken along line F1-F2 of FIGS.

銅合金で形成され、必要部分に銀めっきが施される半導体装置用リードフレームにおいては、従来、図９に示すように部分銀めっきの下地めっきとして、０．１〜０．３μｍ程度の厚さの銅（Ｃｕ）めっきを施した後に部分銀めっきが行われている。
そして、この部分銀めっきの際に、必要部以外に薄くついた銀をとる為に、電解剥離をし、次いで、銅部分の表面酸化、水酸化等による変色を防止する変色防止処理を行っていた。
銅合金製リードフレームの、このようにして設けられた銅下地めっきは、４２合金（４２％ニッケル−鉄合金）等鉄系のリードフレームの表面に銀めっきの下地めっきとして銅めっきを施した場合とは異なり、通常剥離作業は行うことはなく、リードフレームの表面に形成したまま使用していた。
しかしながら、このように処理された銅合金製リードフレームに対しても、最近、半導体装置組み立て工程及び実装工程で生じるパッケージのデラミネーションが問題視されるようになってきた。
そして、銅合金製リードフレームを用いた場合に発生する封止樹脂とダイパッド裏面間で生じるデラミネーションは、リードフレームの表面処理方法、組み立て条件等と密接な関係があることが分かってきた。
尚、一般に、デラミネーションとは、ＩＣパッケージ内の界面、ＩＣチップと封止樹脂間、タイボンディング剤とＩＣチップ間、ダイパッド表面とダンボンディング剤間、封止樹脂とダイパッド裏面間等で生じる剥離を言うが、リードフレームが原因となるデラミネーションは、封止樹脂とダイパッド裏面間で生じるものであり、ＩＣの信頼性を低下させ、ＩＣ組み立て工程や実装工程における良品率を低下させるため問題となっいた。
上記処理による銅合金製のリードフレームのデラミネーションは、ＩＣ組み立て工程中の加熱処理（工程）で銅合金表面に酸化膜が生じ、酸化膜と金属の間の密着強度が不十分であることが発生の原因と考えられている。 Conventionally, a lead frame for a semiconductor device formed of a copper alloy and having a required portion plated with silver has a thickness of about 0.1 to 0.3 μm as a base plating for partial silver plating as shown in FIG. Partial silver plating is performed after copper (Cu) plating is performed.
At the time of this partial silver plating, in order to remove the thinned silver other than the necessary parts, electrolytic peeling is performed, and then a discoloration preventing treatment for preventing discoloration due to surface oxidation, hydroxylation, etc. of the copper part is performed. Was.
The copper base plating provided in this manner on a copper alloy lead frame is obtained by applying copper plating as a silver plating base plating on the surface of an iron-based lead frame such as 42 alloy (42% nickel-iron alloy). Unlike this, the peeling operation was not usually performed, and the lead frame was used as it was formed on the surface of the lead frame.
However, even for the copper alloy lead frame treated in this manner, delamination of the package that occurs in the semiconductor device assembling step and the mounting step has recently been regarded as a problem.
It has been found that delamination between the sealing resin and the rear surface of the die pad, which occurs when a copper alloy lead frame is used, has a close relationship with the lead frame surface treatment method, assembling conditions, and the like.
Generally, delamination refers to delamination occurring at an interface within an IC package, between an IC chip and a sealing resin, between a tie bonding agent and an IC chip, between a die pad surface and a dam bonding agent, between a sealing resin and a die pad back surface, and the like. However, the delamination caused by the lead frame is generated between the sealing resin and the back surface of the die pad, which lowers the reliability of the IC, and lowers the yield rate in the IC assembling process and the mounting process. It has become.
The delamination of the lead frame made of a copper alloy by the above-mentioned process may be caused by an oxide film being formed on the surface of the copper alloy by a heat treatment (step) during the IC assembling process, and the adhesion strength between the oxide film and the metal may be insufficient. It is considered the cause of the outbreak.

一方、封止樹脂とダイパッド裏面間、さらには封止樹脂とリードフレーム全面の間の密着強度を向上させ、デラミネーション発生を防止するためのリードフレームとして、特表平７−５０３１０３には、接着性を改善するためにクロムと亜鉛の混合体あるいはそれぞれの単体からなる薄い被膜で全面を被膜されたリードフレームが開示されている。
しかし、このリードフレームでは銀めっき部分も他の金属被膜で覆われるため、金ワイヤボンディングの安定性が劣るという問題があった。 On the other hand, as a lead frame for improving the adhesion strength between the sealing resin and the back surface of the die pad, and further between the sealing resin and the entire surface of the lead frame, and preventing the occurrence of delamination, it is adhered to JP-T-Hei 7-503103. A lead frame which is entirely coated with a thin coating of a mixture of chromium and zinc or each of them alone to improve the properties is disclosed.
However, in this lead frame, since the silver-plated portion is also covered with another metal coating, there is a problem that the stability of gold wire bonding is inferior.

また、ＩＣ組み立て工程の条件は、組立を実施するＩＣメーカーにより異なり、銅合金製リードフレームの表面酸化状態、酸化膜形成過程もメーカー毎に異なる為、リードフレームに起因するデラミネーションの発生状況がＩＣ組み立てメーカーによって異なっていた。例えば、ベンゾトリアゾール系の被膜により、銅の酸化、水酸化による変色を防止する処理方法では、ＩＣ組み立て温度が低いメーカに対しては、デラミネーション防止効果が得られるが、ＩＣ組み立て温度が高いメーカではデラミネーション防止効果が得られない。このため、従来はデラミネーションに対する対策をＩＣ組み立て条件に合わせて各メーカ毎に行っていたのが実状で、ＩＣの組み立て条件によらず、リードフレームに起因するデラミネーションに対応できる手段が求められていた。   In addition, the conditions of the IC assembling process vary depending on the IC maker performing the assembly, and the surface oxidation state of the copper alloy lead frame and the process of forming the oxide film also vary from manufacturer to maker. It was different depending on the IC assembly manufacturer. For example, in a treatment method in which discoloration due to oxidation and hydroxylation of copper is prevented by using a benzotriazole-based coating, a delamination prevention effect can be obtained for a manufacturer having a low IC assembly temperature, but a manufacturer having a high IC assembly temperature. In this case, the effect of preventing delamination cannot be obtained. For this reason, conventionally, measures against delamination have been taken for each manufacturer in accordance with the IC assembly conditions, and a means capable of coping with delamination caused by the lead frame is required regardless of the IC assembly conditions. I was

このように、銅合金製のリードフレームにおいては、リードフレームに起因した半導体装置（ＩＣ）におけるデラミネーションを防止し、ＩＣの信頼性低下、ＩＣ組み立て工程、実装工程における良品率の低下を防止することが望まれており、特に、ＩＣの組み立て条件によらず、リードフレームに起因するデラミネーションの発生を防止できるものが求められていた。
本発明は、このような状況のもと、ＩＣの組み立て条件によらず、リードフレームに起因するデラミネーションの発生を防止でき、且つ、ボンディング性を損なわない銅合金製のリードフレームを用いた半導体装置を提供しようとするものである。 As described above, in the lead frame made of a copper alloy, delamination in a semiconductor device (IC) caused by the lead frame is prevented, and a decrease in the reliability of the IC and a decrease in the non-defective rate in the IC assembling process and the mounting process are prevented. In particular, there has been a demand for a device that can prevent the occurrence of delamination due to a lead frame regardless of the IC assembly conditions.
The present invention provides a semiconductor device using a lead frame made of a copper alloy which can prevent delamination caused by the lead frame and does not impair the bonding property regardless of the IC assembling conditions. It is intended to provide a device.

本発明の半導体装置に供されるリードフレームとしては、銅合金材からなり、ワイヤボンディング用ないしダイボンディング用の、銀、金、パラジウムの少なくとも１つからなる部分貴金属めっきが施された樹脂封止型の半導体装置用リードフレームであって、少なくとも封止樹脂と接する側の銅部表面の全部ないし所定の部分に銀、金、白金、パラジウムの少なくとも１つからなる薄い貴金属めっきが施されていることを特徴とするものが挙げられる。
そして、上記において、薄い貴金属めっきの厚みが０．５μｍ以下、０．００１μｍ以上であることを特徴とするものが挙げられる。
そしてまた、上記における部分貴金属めっきは部分銀めっきであり、且つ、薄い貴金属めっきが薄い銀めっきであることを特徴とするものが挙げられる。
尚、銅合金を素材とするリードフレームにおいては、部分銀めっきの下地めっきとして０．１〜０．３μｍ程度の厚さの銅めっきを形成した上に、部分銀めっきを施すのが一般的である。 The lead frame provided in the semiconductor device of the present invention is made of a copper alloy material and is resin-encapsulated for partial or noble metal plating of at least one of silver, gold and palladium for wire bonding or die bonding. Type semiconductor device lead frame, wherein at least the entire surface or a predetermined portion of the surface of the copper portion on the side in contact with the sealing resin is provided with a thin noble metal plating made of at least one of silver, gold, platinum and palladium. It is characterized by the following.
Further, in the above, there is provided one in which the thickness of the thin noble metal plating is 0.5 μm or less, and 0.001 μm or more.
The partial noble metal plating described above is a partial silver plating, and the thin noble metal plating is a thin silver plating.
In a lead frame made of a copper alloy, it is common to form a copper plating having a thickness of about 0.1 to 0.3 μm as a base plating for the partial silver plating and then apply a partial silver plating. is there.

上記リードフレームの部分貴金属めっき方法としては、銅合金材からなり、ワイヤボンディング用ないしダイボンディング用の、銀、金、パラジウムの少なくとも１つからなる部分貴金属めっきが施され、且つ、少なくとも封止樹脂と接する側の銅部表面の全部ないし所定の部分に、銀、金、白金、パラジウムの少なくとも１つからなる薄い貴金属めっきが施されている樹脂封止型の半導体装置用リードフレームの部分貴金属めっき法であって、少なくとも、部分貴金属めっきを施し、貴金属モレ部を除去するための電解剥離処理を施した後に、薄い貴金属めっきを施すことを特徴とするものが挙げられる。
そして、上記において、部分貴金属めっきは、外形加工された銅合金からなるリードフレーム素材の表面に銅めっきを施した後に施されることを特徴とするものが挙げられる。 そしてまた、上記において、薄い貴金属めっきは、電解めっきないし無電解めっきにより施されることを特徴とするものが挙げられる。
また、上記リードフレームの部分貴金属めっき方法としては、銅合金材からなり、ワイヤボンディング用ないしダイボンディング用の、銀、金、パラジウムの少なくとも１つからなる部分貴金属めっきが施され、且つ、少なくとも封止樹脂と接する側の銅部表面の全部ないし所定の部分に、銀、金、白金、パラジウムの少なくとも１つからなる薄い貴金属めっきが施されている樹脂封止型の半導体装置用リードフレームの部分貴金属めっき法であって、少なくとも、順に、（Ａ）外形加工された銅合金からなるリードフレーム素材の表面に銅めっきを施す工程と、（Ｂ）銅めっきが施されたリードフレームの表面の全部ないし所定の部分に薄い貴金属めっきを施す工程と、（Ｃ）部分貴金属めっきを施す工程とを有することを特徴とするものが挙げられる。
そして、上記において、薄い貴金属めっきは、電解めっきないし無電解めっきにより施されることを特徴とするものが挙げられる。
そしてまた、上記において、部分貴金属めっきは部分銀めっきであり、且つ、薄い貴金属めっきが薄い銀めっきであることを特徴とするものが挙げられる。 As a method of plating the partial noble metal of the lead frame, a partial noble metal plating made of a copper alloy material and made of at least one of silver, gold and palladium for wire bonding or die bonding is applied, and at least a sealing resin Partial noble metal plating of a resin-encapsulated semiconductor device lead frame in which a thin noble metal plating made of at least one of silver, gold, platinum, and palladium is applied to all or a predetermined portion of the surface of the copper part on the side in contact with The method is characterized in that at least partial noble metal plating is performed, electrolytic stripping treatment for removing noble metal leaks is performed, and then thin noble metal plating is performed.
In the above, the partial noble metal plating is characterized in that it is performed after copper plating is performed on the surface of a lead frame material made of a copper alloy whose outer shape has been processed. Further, in the above, there is a method in which the thin noble metal plating is applied by electrolytic plating or electroless plating.
In addition, as the method of plating the partial noble metal of the lead frame, a partial noble metal plating made of a copper alloy material and made of at least one of silver, gold, and palladium for wire bonding or die bonding is applied, and at least sealing is performed. A portion of a resin-encapsulated semiconductor device lead frame in which a thin noble metal plating made of at least one of silver, gold, platinum, and palladium is applied to all or a predetermined portion of the surface of the copper portion on the side in contact with the sealing resin. A noble metal plating method, in which, at least in order, (A) a step of applying copper plating to a surface of a lead frame material made of a copper alloy whose outer shape is processed; and (B) a whole of the surface of the copper-plated lead frame. Or a step of applying a thin noble metal plating to a predetermined portion, and (C) a step of applying a partial noble metal plating. And the like.
In the above, the thin noble metal plating is characterized by being applied by electrolytic plating or electroless plating.
In the above, the partial noble metal plating is partial silver plating, and the thin noble metal plating is thin silver plating.

本発明の半導体装置は、銅合金材からなり、ワイヤボンディング用ないしダイボンディング用の、銀、金、パラジウムの少なくとも１つからなる部分貴金属めっきが施された樹脂封止型の半導体装置用リードフレームで、且つ、少なくとも封止樹脂と接する側の銅部表面の全部ないし所定の部分に銀、金、白金、パラジウムの少なくとも１つからなる薄い貴金属めっきが施されているリードフレームを、用いた半導体装置であって、少なくとも封止用樹脂と接するリードフレーム表面の全部ないし所定の部分の銅酸化膜形成領域において、貴金属の濃度が、Ｘ線光電子分光による測定で、０．１原子％以上〜２０原子％未満であることを特徴とするものである。   The semiconductor device of the present invention is a resin-sealed semiconductor device lead frame which is made of a copper alloy material and partially plated with at least one of silver, gold and palladium for wire bonding or die bonding. And a lead frame in which a thin noble metal plating made of at least one of silver, gold, platinum, and palladium is applied to at least all or a predetermined portion of the surface of the copper portion on the side in contact with the sealing resin. In the apparatus, the concentration of the noble metal is at least 0.1 atomic% to 20 atomic% as measured by X-ray photoelectron spectroscopy in at least the entire or predetermined portion of the lead oxide surface in contact with the sealing resin in the copper oxide film forming region. It is characterized by being less than atomic%.

（作用）
本発明の半導体装置に供されるリードフレームは、上記のような構成にすることにより、ＩＣの組み立て条件によらず、リードフレームに起因する半導体装置における封止樹脂のデラミネーションの発生を防止でき、且つ、ボンデイング性を損なわない銅合金製のリードフレームの提供を可能としている。
詳しくは、少なくとも封止樹脂と接する側の銅部表面の全部ないし所定の部分に銀、金、白金、パラジウムの少なくとも１つからなる薄い貴金属めっきが施されていることにより、薄い貴金属めっきが施された箇所においては、銅の表面に施された薄い貴金属めっきは銅の酸化を抑えて、酸化膜厚を低減するとともに、酸化膜生成の際にはＣｕＯよりＣｕ2 Ｏの生成を優先させるため、酸化膜自体が破壊されにくくなり、封止樹脂とのデラミネーションの発生を抑えることができるのである。
特に、半導体素子を搭載するダイバッドの裏面の銅部表面にのみ貴金属の薄いめっきを施してもその効果は大きい。
薄い貴金属めっきが銅表面に施されると、該貴金属はＩＣ組み立て工程中における加熱により銅酸化膜内部に拡散するため、銅の酸化膜破壊強度を向上させるとともに、本来、封止樹脂との密着性が劣る貴金属の特質をカバーすることができる。
そして、薄い貴金属めっきの厚みを０．５μｍ以下、０．００１μｍ以上としていることにより、適切な厚みとしている。薄い貴金属めっきの厚みが０．００１μｍより薄いと上記効果が得られず、厚みを０．５μｍより厚くするとめっき時間と費用がかかるばかりでなく、ＩＣ組み立て工程で貴金属が銅酸化膜内部に十分に拡散しないため封止樹脂との密着強度が劣化すると考えられる。
また、このようなリードフレームにおいては、構造上金ワイボンディング性に悪影響を与えることはない。
本発明の半導体装置に供されるリードフレームのはんだめっき性については、はんだめっきの前処理として行われる酸洗浄や化学研磨処理によって銅酸化膜が除去されるため、従来のリードフレームと変わることはなく、良好となる。
また、部分貴金属めっきは、部分銀めっきであり、且つ、薄い貴金属めっきが薄い銀めっきであることにより、従来使用されている電解めっき方法や無電解めっき方法により、比較的簡単にめっきを安定的に行うことができ、生産コストを下げることができる。 (Action)
The lead frame provided for the semiconductor device of the present invention can be configured as described above to prevent the occurrence of delamination of the sealing resin in the semiconductor device due to the lead frame regardless of the IC assembling conditions. Further, it is possible to provide a lead frame made of a copper alloy which does not impair the bonding property.
More specifically, a thin noble metal plating made of at least one of silver, gold, platinum, and palladium is applied to at least all or a predetermined portion of the surface of the copper portion on the side in contact with the sealing resin, so that the thin noble metal plating is applied. Where the thin noble metal plating applied to the surface of copper suppresses the oxidation of copper to reduce the oxide film thickness, and to prioritize the generation of Cu 2 O over CuO when forming the oxide film. In addition, the oxide film itself is less likely to be broken, and the occurrence of delamination with the sealing resin can be suppressed.
In particular, even if a thin plating of noble metal is applied only to the surface of the copper portion on the back surface of the die pad on which the semiconductor element is mounted, the effect is large.
When a thin noble metal plating is applied to the copper surface, the noble metal diffuses into the copper oxide film due to heating during the IC assembling process, so that the copper oxide film breaking strength is improved and the adhesion to the sealing resin is originally required. It can cover the characteristics of noble metals with poor properties.
The thickness of the thin noble metal plating is 0.5 μm or less and 0.001 μm or more, so that the thickness is appropriate. If the thickness of the thin noble metal plating is less than 0.001 μm, the above effect cannot be obtained, and if the thickness is more than 0.5 μm, not only the plating time and cost are increased, but also the noble metal is sufficiently embedded in the copper oxide film in the IC assembling process. It is considered that the adhesive strength with the sealing resin is deteriorated because of no diffusion.
Also, in such a lead frame, there is no adverse effect on the gold-wipe bonding property in terms of structure.
Regarding the solder plating property of the lead frame provided for the semiconductor device of the present invention, since the copper oxide film is removed by acid cleaning or chemical polishing performed as a pretreatment of the solder plating, there is no difference from the conventional lead frame. Not good.
In addition, the partial noble metal plating is a partial silver plating, and the thin noble metal plating is a thin silver plating, so that the plating can be performed relatively easily and stably by a conventional electrolytic plating method or electroless plating method. And production costs can be reduced.

本発明の半導体装置に供されるリードフレームの部分貴金属めっき方法は、上記のような構成にすることにより、上記のような、ＩＣの組み立て条件によらず、リードフレームに起因する半導体装置における封止樹脂のデラミネーションの発生を防止でき、且つ、ボンデイング性を損なわない銅合金製のリードフレームを製造する、製造方法の提供を可能とするものである。
具体的には、少なくとも、部分貴金属めっきを施し、貴金属モレ部を除去するための電解剥離処理を施した後に、薄い貴金属を施すことにより、即ち、部分貴金属めっき部を形成する際に薄くついた部分貴金属めっきのモレ部を除去するための電解剥離処理を施した後に、薄い貴金属めっきを形成するため、薄い貴金属の膜を同一面内においてバラツキの少ないものとしている。
そして、電解めっきないし無電解めっきにより、薄い貴金属めっきを施すことにより、薄い貴金属めっきの膜厚の制御を簡単なものとしている。
また、少なくとも、順に、（Ａ）外形加工された銅合金からなるリードフレーム素材の表面に銅めっきを施す工程と、（Ｂ）銅めっきが施されたリードフレームの表面の全部ないし所定の部分に薄い貴金属めっきを施す工程と、（Ｃ）部分貴金属めっきを施す工程とを有することにより、薄い貴金属めっきを部分貴金属めっきに影響されずに銅めっき表面に形成することを可能としている。
そして、電解めっきないし無電解めっきにより、薄い貴金属めっきを施すことにより、薄い貴金属めっきの膜厚の制御を簡単なものとしている。
尚、上記において、薄い貴金属めっきを、リードフレームの部分貴金属めっきが施される領域を含め、リードフレーム全体に施す場合には、薄い貴金属めっきの被膜生成作業を簡単なものとできる。
そしてまた、部分貴金属めっきとして部分銀めっきを用い、且つ、薄い貴金属めっきとして薄い銀めっきを施すことにより、従来使用されている電解めっき方法や無電解めっき方法により、比較的簡単にめっきを安定的に行うことができるものとしている。
同時に、金めっきや白金めっきに比べ生産コストを下げることができる。 The method for partially precious metal plating of a lead frame provided in the semiconductor device of the present invention has the above-described configuration, and thus, the sealing in the semiconductor device caused by the lead frame can be performed regardless of the IC assembling conditions as described above. An object of the present invention is to provide a manufacturing method for manufacturing a lead frame made of a copper alloy, which can prevent delamination of a resin and can prevent a bondability from being deteriorated.
Specifically, at least, after applying a partial noble metal plating, and after performing an electrolytic peeling treatment for removing a noble metal leakage portion, by applying a thin noble metal, that is, when forming a partial noble metal plating portion, it became thin. In order to form a thin noble metal plating after performing an electrolytic peeling treatment for removing a leak portion of the partial noble metal plating, a thin noble metal film is made to have a small variation in the same plane.
And, by applying a thin noble metal plating by electrolytic plating or electroless plating, the thickness of the thin noble metal plating can be easily controlled.
Further, at least, in order, (A) a step of applying copper plating to a surface of a lead frame material made of a copper alloy whose outer shape is processed; and (B) a step of applying copper plating to all or a predetermined portion of the surface of the lead frame provided with copper plating. By having a step of applying a thin noble metal plating and (C) a step of applying a partial noble metal plating, it is possible to form a thin noble metal plating on the copper plating surface without being affected by the partial noble metal plating.
And, by applying a thin noble metal plating by electrolytic plating or electroless plating, the thickness of the thin noble metal plating can be easily controlled.
In the above, when the thin noble metal plating is applied to the entire lead frame including the region of the lead frame to which the partial noble metal plating is applied, the work of forming a thin noble metal plating film can be simplified.
Also, by using partial silver plating as the partial noble metal plating and applying thin silver plating as the thin noble metal plating, the plating can be relatively easily stabilized by the conventionally used electrolytic plating method or electroless plating method. That can be done.
At the same time, the production cost can be reduced as compared with gold plating or platinum plating.

本発明の半導体装置は、上記のリードフレームを用いることにより、ワイヤボンディング工程における熱処理等を経て、封止用樹脂と接するリードフレーム表面の全部ないし所定の部分に、銀、金、パラジウム、白金の少なくとも１つと銅酸化膜からなる領域をもつ表面部を形成でき、これにより、封止樹脂と接する部分の剥離を防止できるものとしている。
そして、封止用樹脂と接するリードフレーム表面の全部ないし所定の部分の銅酸化膜形成領域において、貴金属の濃度が、Ｘ線光電子分光による測定で、０．１原子％以上であることにより、銅酸化膜のないし銅酸化膜と銅合金との境での破壊強度を充分なものとでき、２０原子％未満であることにより、封止樹脂との密着性が劣る貴金属の特質をカバーすることができ、銅酸化膜と封止樹脂との密着性を充分なものとできる。 The semiconductor device of the present invention, by using the above-described lead frame, undergoes heat treatment or the like in a wire bonding step, and all or a predetermined portion of the surface of the lead frame in contact with the sealing resin includes silver, gold, palladium, and platinum. A surface portion having at least one region composed of a copper oxide film can be formed, thereby preventing peeling of a portion in contact with the sealing resin.
When the concentration of the noble metal is 0.1 atomic% or more as measured by X-ray photoelectron spectroscopy in the entire or predetermined portion of the copper oxide film forming region of the lead frame surface in contact with the sealing resin, A sufficient breaking strength of the oxide film or the boundary between the copper oxide film and the copper alloy can be obtained, and if it is less than 20 atomic%, it is possible to cover the characteristics of the noble metal having poor adhesion to the sealing resin. As a result, the adhesion between the copper oxide film and the sealing resin can be made sufficient.

本発明は、上記のように、ＩＣの組み立て条件によらず、リードフレームに起因するデラミネーションの発生を防止でき、且つ、ボンディング性を損なわない、銅合金製のリードフレームを用いた半導体装置の提供を可能としている。
The present invention, as described above, can prevent the occurrence of delamination caused by a lead frame regardless of the IC assembly conditions, and does not impair the bonding property. It is possible to provide.

本発明の実施の形態例を以下、図にそって説明する。
先ず、本発明の半導体装置に供されるリードフレームの参考実施例１を挙げる。
図１は参考実施例１のリードフレームを示したもので、図１（ｂ）はその平面図を、図１（ａ）はＡ１−Ａ２における断面の要部拡大図である。
図１中、１１０はリードフレーム、１１１はダイパッド、１１２はインナーリード、１１３はアウターリード、１１４はダムバー、１１５はフレーム、１１６は吊りバー、１２０はリードフレーム素材（銅合金）、１３０は銅めっき、１４０は部分銀めっき、１５０は薄い銀めっきである。
本参考実施例のリードフレーム１１０は、厚さ０．１５ｍｍの銅合金材（古河電気工業株式会社製ＥＦＴＥＣ６４Ｔ−１／２Ｈ材）からエッチング加工により図１（ｂ）のような形状に外形加工
されたリードフレーム素材１２０に対し、銅めっき１３０を全面に施してから、この上に所定の領域にのみに部分銀めっき１４０を施し、さらに全面に薄い銀めっき１５０を施したものである。
本参考実施例においては、銅めっき厚を０．１μｍ、部分銀めっき厚を３μｍ、薄い銀めっき厚を０．０１μｍとしたが、銅めっき厚としては、０．１〜０．３μｍ、部分めっき厚としては１．５〜１０μｍ、薄いめっき厚としては０．００１〜０．５μｍが好ましい。また、リードフレーム素材として古河電気工業株式会社製の銅合金ＥＦＴＥＣ６４Ｔ−１／２Ｈ材を用いているが、本発明はこれに限定されることはなく、他の銅合金でも良い。 An embodiment of the present invention will be described below with reference to the drawings.
First, a first embodiment of a lead frame provided for the semiconductor device of the present invention will be described.
FIG. 1 shows a lead frame of a first embodiment. FIG. 1B is a plan view of the lead frame, and FIG. 1A is an enlarged view of a main part of a cross section along A1-A2.
In FIG. 1, 110 is a lead frame, 111 is a die pad, 112 is an inner lead, 113 is an outer lead, 114 is a dam bar, 115 is a frame, 116 is a hanging bar, 120 is a lead frame material (copper alloy), and 130 is copper plating. , 140 are partial silver plating and 150 is thin silver plating.
The lead frame 110 of the present embodiment is formed by etching from a copper alloy material having a thickness of 0.15 mm (EFTEC64T-1 / 2H manufactured by Furukawa Electric Co., Ltd.) into a shape as shown in FIG. 1B. A copper plating 130 is applied to the entire surface of the lead frame material 120, a partial silver plating 140 is applied only to a predetermined region, and a thin silver plating 150 is applied to the entire surface.
In the present embodiment, the thickness of the copper plating is 0.1 μm, the thickness of the partial silver plating is 3 μm, and the thickness of the thin silver plating is 0.01 μm. The thickness is preferably 1.5 to 10 μm, and the thin plating thickness is preferably 0.001 to 0.5 μm. Further, although a copper alloy EFTEC64T-1 / 2H manufactured by Furukawa Electric Co., Ltd. is used as a lead frame material, the present invention is not limited to this, and other copper alloys may be used.

本参考実施例のリードフレームは、図９に示す従来のリードフレームのように、外形加工されたリードフレーム素材１２０に対し、銅めっき１３０を全面に施してから、この上に所定の領域にのみに部分銀めっき１４０を施しただけのものとは異なり、薄い銀めっき１５０を設けているものであり、薄い銀めっき１５０設けていることにより、銅めっき１３０の酸化を抑えて、酸化膜厚を低減するとともに、酸化の際にはＣｕＯよりＣｕ2 Ｏの生成を優先させるため、酸化膜自体が破壊されにくくなり、半導体装置を作製した場合には封止樹脂とのデラミネーションの発生を抑えることができるものとしている。 The lead frame of the present embodiment is formed by applying a copper plating 130 to the entire surface of a lead frame material 120 whose outer shape is processed as in the conventional lead frame shown in FIG. Unlike the case where only the partial silver plating 140 is applied, the thin silver plating 150 is provided. By providing the thin silver plating 150, the oxidation of the copper plating 130 is suppressed, and the oxide film thickness is reduced. In addition to the reduction, the generation of Cu 2 O is prioritized over CuO during oxidation, so that the oxide film itself is less likely to be broken, and when a semiconductor device is manufactured, the occurrence of delamination with the sealing resin is suppressed. Can be done.

本参考実施例のリードフレームを用いて半導体装置（ＩＣパッケージ）を作製する工程を図５を用いて簡単に説明しておく。
先ず、図１に示す本参考実施例のリードフレーム１１０のダイパッド１１１を、ダウンセット加工し（図５（ａ））、ダイパッド１１１上に銀ペースト１７０を介して半導体素子１６０を接合する。（図５（ｂ））
次いで、銀ペースト１７０を加熱キュアした後、半導体素子１６０の電極パッド（端子）１６１とリードフレーム１１０の部分銀めっき１４０が施されたインナーリード１１２の先端とをワイヤ（金線）１８０でワイヤボンディングして電気的に結線する。（図５（ｃ））
次いで、樹脂封止、ダムバーの除去、アウターリードのフォーミング処理、半田めっきを経て、半導体装置２００を得る。（図５（ｄ））
以上の工程を経て、図１に示すリードフレーム１１０表面の銅めっき１３０、ないしリードフレーム素材（銅合金）１２０の一部は酸化され、図５（ｃ）に示す銅酸化膜１３０Ａを形成する。
これと同時に、図１に示す銅めっき１３０上の薄い銀めっき１５０は、銅酸化膜１３０Ａおよびリードフレーム素材（銅合金）１２０中へ拡散される。 A process of manufacturing a semiconductor device (IC package) using the lead frame of the present embodiment will be briefly described with reference to FIGS.
First, the die pad 111 of the lead frame 110 of the present embodiment shown in FIG. 1 is downset (FIG. 5A), and the semiconductor element 160 is bonded on the die pad 111 via the silver paste 170. (FIG. 5 (b))
Next, after the silver paste 170 is cured by heating, the electrode pads (terminals) 161 of the semiconductor element 160 and the tips of the inner leads 112 on the partial silver plating 140 of the lead frame 110 are wire-bonded with wires (gold wires) 180. And electrically connect them. (FIG. 5 (c))
Next, the semiconductor device 200 is obtained through resin sealing, removal of a dam bar, forming processing of an outer lead, and solder plating. (FIG. 5 (d))
Through the above steps, the copper plating 130 on the surface of the lead frame 110 shown in FIG. 1 or a part of the lead frame material (copper alloy) 120 is oxidized to form a copper oxide film 130A shown in FIG. 5C.
At the same time, the thin silver plating 150 on the copper plating 130 shown in FIG. 1 is diffused into the copper oxide film 130A and the lead frame material (copper alloy) 120.

上記本参考実施例のリードフレームを用いた半導体装置２００の作製方法においては、図５（ｃ）の段階で、加熱されたことによってダイパッド１１１における銅の表面では、Ｘ線光電子分光（ＥＳＣＡ）で観察すると、図６（ａ）ないし図６（ｂ）に示すようになっている。
尚、図６中、１３０Ａは銅酸化膜、１５０Ａは拡散された銀の存在領域、１２０はリードフレーム素材、１２０ａは銅合金を示している。
図１に示す薄い銀めっき１５０の銀は、銅酸化膜１３０Ａ及び銅リードフレーム素材（銅合金）中に拡散され、図６（ａ）に示すように、銅酸化膜領域１３０Ａ全体と銅合金１２０ａの一部にＡｇが拡散される。銅酸化膜領域１３０Ａは、ＣｕＯ１３０Ａｂを表面側にして、ＣｕＯ１３０ＡｂとＣｕ2 Ｏ１３０Ａａを形成する。
更に、Ａｇの拡散を進めると、Ａｇは銅合金の内側へ移動し、図６（ｂ）に示すように、拡散されたＡｇは表面部にはほとんど無い状態となる。
薄い銀膜１５０の厚さ、加熱条件を変えることにより、銅酸化膜の内側に銀が拡散している状態が異なり、薄い銀膜１５０の厚さがある程度厚く、加熱条件が温和である場合には酸化膜のほぼ全面までに銀が拡散する傾向にあって、銀めっきが薄く、加熱条件が厳しい場合には、銅酸化膜の内部深くに銀が拡散している状態となり易い。銀の拡散は酸化膜のみならずリードフレーム素材（銅合金）１２０まで及ぶ場合もあるまた、薄い銀めっき１５０の厚さと加熱条件が適当である場合には、ＥＳＣＡ等による表面観察によると、銅酸化膜の成分がその表面においても亜酸化銅Ｃｕ2 Ｏである状態が得られる。 In the method of manufacturing the semiconductor device 200 using the lead frame of the present embodiment, the copper surface of the die pad 111 is heated by X-ray photoelectron spectroscopy (ESCA) at the stage of FIG. When observed, the results are as shown in FIGS. 6A and 6B.
In FIG. 6, 130A is a copper oxide film, 150A is a region where diffused silver is present, 120 is a lead frame material, and 120a is a copper alloy.
The silver of the thin silver plating 150 shown in FIG. 1 is diffused into the copper oxide film 130A and the copper lead frame material (copper alloy), and as shown in FIG. 6A, the entire copper oxide film region 130A and the copper alloy 120a Ag is diffused in a part of. Copper oxide region 130A is the CuO130Ab on the surface side, to form a CuO130Ab and Cu 2 O130Aa.
Further, as the diffusion of Ag proceeds, the Ag moves to the inside of the copper alloy, and as shown in FIG. 6B, the diffused Ag hardly exists on the surface.
By changing the thickness of the thin silver film 150 and the heating conditions, the state where silver is diffused inside the copper oxide film is different, and when the thickness of the thin silver film 150 is somewhat thick and the heating condition is mild, Silver tends to diffuse to almost the entire surface of the oxide film, and when the silver plating is thin and the heating conditions are severe, silver tends to diffuse deep inside the copper oxide film. The diffusion of silver may extend not only to the oxide film but also to the lead frame material (copper alloy) 120. When the thickness of the thin silver plating 150 and the heating conditions are appropriate, according to the surface observation by ESCA or the like, A state is obtained in which the component of the oxide film is cuprous oxide Cu 2 O also on the surface.

これに対し、図５に示す工程と同じ工程にて、従来の図９に示す、銅めっきと部分銀めっきのみを施したリードフレームを用い、半導体装置を作製した場合には、図５（ｃ）に相当する工程での銅の酸化状態は図６（ｃ）のようになる。
従来の図９に示すリードフレームの場合には、銅表面に薄い銀めっきが施されていないため、銅の酸化は速く、結果的に酸化膜厚は、本実例の場合と比べ、厚くなり、且つ、銀の拡散が無いため、本実施例のリードフレームを用いた場合に比べ、ＣｕＯよりＣｕ2 Ｏの生成が優先されることはない。 On the other hand, when a semiconductor device is manufactured in the same process as that shown in FIG. 5 using a lead frame which is only subjected to copper plating and partial silver plating as shown in FIG. The oxidation state of copper in the process corresponding to ()) is as shown in FIG.
In the case of the conventional lead frame shown in FIG. 9, since the copper surface is not plated with thin silver, the copper is oxidized quickly, and as a result, the oxide film thickness becomes thicker than in the case of this example. Further, since there is no diffusion of silver, generation of Cu 2 O is not given priority over CuO as compared with the case where the lead frame of this embodiment is used.

図６より、本参考実施例のリードフレーム１１０は、薄い銀めっき１４０を設けたことにより、図５（ｃ）の工程における、酸化膜の形成を抑えており、薄い銀めっき１４０を設けていない従来の場合に比べ、酸化膜厚を低減していることが分かる。
また、本参考実施例のリードフレーム１１０の場合、酸化膜生成の際、ＣｕＯよりＣｕ2 Ｏの生成を優先させるため、酸化膜自体が破壊されにくくしており、結果として、樹脂封止した際には、封止樹脂とのデラミネーションの発生を抑えることができるものとしている。 As shown in FIG. 6, the lead frame 110 of the present embodiment is provided with the thin silver plating 140, so that the formation of the oxide film in the step of FIG. 5C is suppressed, and the thin silver plating 140 is not provided. It can be seen that the oxide film thickness is reduced as compared with the conventional case.
In addition, in the case of the lead frame 110 of the present embodiment, when the oxide film is formed, the generation of Cu 2 O is prioritized over the CuO, so that the oxide film itself is hard to be destroyed. It is assumed that the occurrence of delamination with the sealing resin can be suppressed.

別に、参考実施例１の変形例として、薄い銀めっきの厚さをそれぞれ、０．００１μｍ、０．０１μｍ、０．５μｍとしたものを作製したが、参考実施例１と合わせ、以下の表１のように、これらのリードフレームのダイパッド裏面の銅酸化膜の密着性、封止樹脂密着強度は評価された。
尚、ダイパッド裏面の銅酸化膜の密着性は、リードフレームをワイヤボンディング想定加熱条件２８０°Ｃ、３分間にて加熱し、ダイパッド裏面の酸化膜密着強度をテープピーリング法により調べ、剥離なしを可（○）とし、剥離ありを不可（×）とした。
封止樹脂密着強度は、封止樹脂密着強度評価用の専用フレーム（ベタ状板）に実施例１、各変形例と同じ表面処理を施したものと、従来と同じ表面処理を施したものを比較テストした。但し、両者とも部分銀めっき処理は施していない。
これらの専用フレームをワイヤボンディング想定加熱条件２８０°Ｃ、３分間の条件で加熱した後、銅合金材面に一定面積の封止樹脂を成形し、シエア法により密着強度を測定した。
判定は、２．０Ｎ／ｍｍ2 以上を可（○）とし、２．０Ｎ／ｍｍ2 未満を不可（×）とした。
尚、比較例としては、本参考実施例における薄い銀めっきの厚さを１．０μｍとしたものを挙げた。
従来例は、本参考実施例において薄い銀めっきを施さないものである。
(表１）
┌───────────────┬─────────────────┐
│ │薄い銀めっき厚 │ダイパッド裏面の│ 封止樹脂密着性│
│ │ 〔μｍ〕 │銅酸化膜密着性 │ │
├──────┼────────┼────────┼────────┤
│ 変形例１ │ ０．００１ │ ○ │ ○ │
├──────┼────────┼────────┼────────┤
│参考実施例１│ ０．０１ │ ○ │ ○ │
├──────┼────────┼────────┼────────┤
│ 変形例２ │ ０．１ │ ○ │ ○ │
├──────┼────────┼────────┼────────┤
│ 変形例３ │ ０．５ │ ○ │ ○ │
├──────┼────────┼────────┼────────┤
│ 比較例１ │ １．０ │ ○ │ × │
├──────┼────────┼────────┼────────┤
│ 比較例２ │薄い銀めっきなし│ × │ × │
│ （従来例）│ │ │ │
└──────┴────────┴────────┴────────┘ Separately, as a modified example of Reference Example 1, thin silver platings having thicknesses of 0.001 μm, 0.01 μm, and 0.5 μm were produced. As described above, the adhesiveness of the copper oxide film on the back surface of the die pad of these lead frames and the adhesive strength of the sealing resin were evaluated.
The adhesiveness of the copper oxide film on the back of the die pad was determined by heating the lead frame at 280 ° C for 3 minutes under the assumed heating conditions of wire bonding, and examining the adhesive strength of the oxide film on the back of the die pad by a tape peeling method. (○) and no peeling (×).
The sealing resin adhesion strength was determined by applying the same surface treatment as in Example 1 and each modified example to a special frame (solid plate) for evaluating the sealing resin adhesion strength, and the same surface treatment as before. A comparative test was performed. However, in both cases, the partial silver plating treatment was not performed.
After heating these dedicated frames under the assumed heating conditions of wire bonding at 280 ° C. for 3 minutes, a sealing resin having a fixed area was molded on the surface of the copper alloy material, and the adhesion strength was measured by the shear method.
In the judgment, 2.0 N / mm2 or more was judged as acceptable (o), and less than 2.0 N / mm2 was judged as unacceptable (x).
As a comparative example, a thin silver plating having a thickness of 1.0 μm in the present reference example was mentioned.
In the conventional example, thin silver plating is not applied in the present embodiment.
(Table 1)
┌───────────────┬─────────────────┐
│ │ Thin silver plating thickness │ Back side of die pad │ Sealing resin adhesion │
│ │ (μm) │ Copper oxide film adhesion │ │
├──────┼────────┼────────┼────────┤
│ Modification 1 │ 0.001 │ ○ │ ○ │
├──────┼────────┼────────┼────────┤
│Reference Example 1│ 0.01 │ ○ │ ○ │
├──────┼────────┼────────┼────────┤
│ Modification 2 │ 0.1 │ ○ │ ○ │
├──────┼────────┼────────┼────────┤
│ Modification 3 │ 0.5 │ ○ │ ○ │
├──────┼────────┼────────┼────────┤
│ Comparative Example 1 │ 1.0 │ ○ │ × │
├──────┼────────┼────────┼────────┤
│ Comparative Example 2 │ No thin silver plating │ × │ × │
│ (conventional example) │ │ │ │
└──────┴────────┴────────┴────────┘

参考実施例では薄い銀めっきは所定の部分銀めっき後に全面に施している例を示したが、ＩＣパッケージのデラミネーション防止には効果的な部分、例えば、ダイパッド裏面への薄い部分銀めっきのみでもデラミネーション防止（酸化剥離防止）に対して効果を示すことは言うまでもない。   Although the reference example shows an example in which the thin silver plating is applied to the entire surface after the predetermined partial silver plating, an effective portion for preventing delamination of the IC package, for example, only the thin partial silver plating on the back surface of the die pad is used. Needless to say, it is effective for prevention of delamination (prevention of oxidative peeling).

次に参考実施例２のリードフレームを挙げる。
図２は参考実施例２のリードフレームを示したもので、図２（ｂ）はその平面図を、図２（ａ）はＢ１−Ｂ２における断面の要部拡大図である。
図２中、１１０はリードフレーム、１１１はダイパッド、１１２はインナーリード、１１３はアウターリード、１１４はダムバー、１１５はフレーム、１２０はリードフレーム素材（銅合金）、１３０は銅めっき、１４０は部分銀めっき、１５０は薄い銀めっきである。
本参考実施例のリードフレーム１１０は、厚さ０．１５ｍｍの銅合金材（古河電気工業株式会社製ＥＦＴＥＣ６４Ｔ−１／２Ｈ材）からエッチング加工により図１（ｂ）のような形状に外形加工されたリードフレーム素材１２０に対し、銅めっき１３０を全面に施し、この上全面に薄い銀めっき１５０を施し、更にこの上に所定の領域にのみに部分銀めっき１４０を施したものである。
本参考実施例においては、銅めっき厚を０．１μｍ、薄い銀めっき厚を０．０１μｍ、部分銀めっき厚を３μｍ、としたが、実施例１のリードフレームと同様、銅めっき厚としては、０．１〜０．３μｍ、部分めっき厚としては１．５〜１０μｍ、薄いめっき厚としては０．００１〜０．５μｍが好ましい。
また、参考実施例１と同様に、リードフレーム素材として古河電気工業株式会社製の銅合金ＥＦＴＥＣ６４Ｔ−１／２Ｈ材を用いているが、これに限定されることはなく、他の銅合金でも良い。
尚、薄い銀めっきを設けたことによる、ダイパッド裏面の銅酸化膜の密着性、封止樹脂密着強度の評価による結果は、実施例１の場合と同様であった。 Next, a lead frame of Reference Example 2 will be described.
2A and 2B show a lead frame according to a second embodiment of the present invention. FIG. 2B is a plan view of the lead frame, and FIG.
In FIG. 2, 110 is a lead frame, 111 is a die pad, 112 is an inner lead, 113 is an outer lead, 114 is a dam bar, 115 is a frame, 120 is a lead frame material (copper alloy), 130 is copper plating, and 140 is silver. The plating 150 is thin silver plating.
The lead frame 110 of the present embodiment is formed by etching from a copper alloy material having a thickness of 0.15 mm (EFTEC64T-1 / 2H manufactured by Furukawa Electric Co., Ltd.) into a shape as shown in FIG. 1B. A copper plating 130 is applied to the entire surface of the lead frame material 120, a thin silver plating 150 is applied to the entire upper surface thereof, and a partial silver plating 140 is applied only to a predetermined region thereon.
In the present reference example, the copper plating thickness was 0.1 μm, the thin silver plating thickness was 0.01 μm, and the partial silver plating thickness was 3 μm. However, as in the lead frame of Example 1, the copper plating thickness was Preferably, the plating thickness is 0.1 to 0.3 μm, the partial plating thickness is 1.5 to 10 μm, and the thin plating thickness is 0.001 to 0.5 μm.
Further, as in the first embodiment, a copper alloy EFTEC64T-1 / 2H manufactured by Furukawa Electric Co., Ltd. is used as a lead frame material, but the invention is not limited to this, and other copper alloys may be used. .
The results of evaluation of the adhesion of the copper oxide film on the back surface of the die pad and the adhesion strength of the sealing resin due to the provision of the thin silver plating were the same as those in Example 1.

次に、上記参考実施例１のリードフレームに対する部分貴金属めっき方法を説明する。 リードフレームの部分貴金属めっき方法の参考実施例１を挙げ、図３に基づいて説明する。
本参考実施例は、前記参考実施例１のリードフレームを作製する製造方法である。
先ず、外形加工された銅合金からなるリードフレーム１１０Ａに対し、めっき前処理を施したものを用意し（図３（ａ））、この表面全体に銅めっき１３０を０．１μｍの厚さで施した。（図３（ｂ））
めっき前処理としては、エッチングにて外形加工された銅合金からなるリードフレーム１１０Ａの全面をアルカリ水溶液で電解脱脂し、純水で洗浄した後、酸性液で表面に形成されている酸化膜を除去する酸活性化処理を行い、リードフレーム素材１２０である銅合金の表面を活性化して、再度純水で洗浄した。
銅めっきは、液温５０°Ｃで２０秒程度シアン化銅めっきを行い、約０．１μｍの厚さに形成した。
次いで、銅めっき１３０が施されたリードフレーム１１０の所定の部分にのみ部分銀めっき１４０を３．０μｍ厚さで施した。（図３（ｃ））
部分銀めっき１４０は、通常、リードフレームの半導体素子を搭載する側のダイパッド部、半導体素子とワイヤボンディングするインナーリード先端領域のみを露出させるようにマスキング治具で覆い、リードフレームを陰極として、めっき液をノズルより噴射により吹きかける方式の部分めっきにより行うが、この際、所定の部分以外の部分に不要な薄い銀めっきが形成されてしまうことが多々ある。
この不要な薄い銀めっき部分を銀モレ部１４０Ａと言っている。この為、後述する薄い銀めっき１５０を均一に形成するために、銀モレ部１４０Ａ部を電解剥離により除去した。（図３（ｄ））
電解剥離により銀モレ部１４０Ａを除去した後、リードフレームの露出している銅めっき表面、部分銀めっき表面全体に、更に薄い銀めっき１５０を０．０１の厚さで形成した。（図３（ｅ））
このようにして、上記参考実施例１のリードフレームが形成できる。 Next, a method of plating a partial noble metal on a lead frame according to the first embodiment will be described. A first embodiment of a method for partially precious metal plating of a lead frame will be described with reference to FIG.
The present embodiment is a method of manufacturing the lead frame of the first embodiment.
First, a lead frame 110A made of an externally processed copper alloy is prepared by performing a pre-plating treatment (FIG. 3A), and copper plating 130 is applied to the entire surface to a thickness of 0.1 μm. did. (FIG. 3 (b))
As a pre-plating treatment, the entire surface of the lead frame 110A made of a copper alloy whose outer shape has been processed by etching is electrolytically degreased with an alkaline aqueous solution, washed with pure water, and then the oxide film formed on the surface is removed with an acidic solution. The surface of the copper alloy, which is the lead frame material 120, was activated by an acid activation treatment, and was washed again with pure water.
The copper plating was carried out at a liquid temperature of 50 ° C. for about 20 seconds by copper cyanide plating to a thickness of about 0.1 μm.
Next, partial silver plating 140 was applied to a predetermined portion of the lead frame 110 to which the copper plating 130 was applied, with a thickness of 3.0 μm. (FIG. 3 (c))
The partial silver plating 140 is usually covered with a masking jig so as to expose only the die pad portion on the side on which the semiconductor element of the lead frame is mounted, and the tip region of the inner lead for wire bonding with the semiconductor element. The plating is performed by partial plating in which a liquid is sprayed from a nozzle by spraying. In this case, unnecessary thin silver plating is often formed on a portion other than a predetermined portion.
This unnecessary thin silver-plated portion is called a silver leakage portion 140A. Therefore, in order to uniformly form a thin silver plating 150 described later, the silver leakage portion 140A was removed by electrolytic peeling. (FIG. 3 (d))
After removing the silver leakage portion 140A by electrolytic peeling, a thinner silver plating 150 having a thickness of 0.01 was formed on the entire exposed copper plating surface and partial silver plating surface of the lead frame. (FIG. 3 (e))
Thus, the lead frame of the first embodiment can be formed.

次に、上記参考実施例２のリードフレームに対する部分貴金属めっき方法の参考実施例を、図４に基づいて簡単に説明する。
本実施例は、前記参考実施例２のリードフレームを作製する製造方法であり、実施例１のリードフレームの部分めっき方法と異なり、銀めっきを施す前に薄い銀めっきを施すものである。
先ず、外形加工された銅合金からなるリードフレーム１１０Ａに対し、めっき前処理を施したものを用意し（図４（ａ））、この表面全体に銅めっき１３０を０．１μｍの厚さで施した。（図４（ｂ））
次いで、銅めっき１３０が施されたリードフレーム１１０Ａ全面に薄い銀めっき１５０を０．０１μｍの厚さで施した。（図４（ｃ））
この後、薄い銀めっき１５０が施されたリードフレーム１１０Ａの所定の部分にのみ部分銀めっき１４０を３．０μｍ厚さで施した。（図３（ｃ））
めっき前処理、銅めっき、銀めっき等は参考実施例１の方法と同様にして行った。 Next, a reference example of the partial noble metal plating method for the lead frame according to the reference example 2 will be briefly described with reference to FIG.
The present embodiment is a manufacturing method for manufacturing the lead frame of the second embodiment, and is different from the partial plating method of the lead frame of the first embodiment in that thin silver plating is performed before silver plating.
First, a lead frame 110A made of an externally processed copper alloy is prepared by performing a plating pretreatment (FIG. 4A), and a copper plating 130 is applied to the entire surface to a thickness of 0.1 μm. did. (FIG. 4 (b))
Next, thin silver plating 150 was applied to a thickness of 0.01 μm on the entire surface of the lead frame 110A on which the copper plating 130 was applied. (FIG. 4 (c))
Thereafter, only a predetermined portion of the lead frame 110A to which the thin silver plating 150 was applied was subjected to partial silver plating 140 to a thickness of 3.0 μm. (FIG. 3 (c))
The plating pretreatment, copper plating, silver plating and the like were performed in the same manner as in the method of Reference Example 1.

次に、本発明の半導体装置の実施例を挙げ、図にそって説明する。
実施例１の半導体装置は、上記参考実施例１のリードフレームを用いたもので、図５に示すように、ワイヤボンディング工程、樹脂封止工程を経て作製されたものである。 図７はその概略断面図である。
実施例２の半導体装置は、上記参考実施例２のリードフレームを用いたもので、実施例１と同様に、ワイヤボンディング工程、樹脂封止工程を経て作製されたものであるが、外見上は、図７に示す実施例１と同じであるが、表面の銅酸化膜１３０Ａの厚さや、拡散された銀の存在する領域が異なる。
実施例１、実施例２の半導体装置とも、デラミネーションの発生は見られなかった。 Next, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.
The semiconductor device of the first embodiment uses the lead frame of the first embodiment, and is manufactured through a wire bonding step and a resin sealing step as shown in FIG. FIG. 7 is a schematic sectional view thereof.
The semiconductor device of Example 2 uses the lead frame of Reference Example 2 described above, and is manufactured through a wire bonding step and a resin sealing step, as in Example 1. 7 except that the thickness of the copper oxide film 130A on the surface and the region where the diffused silver is present are different.
No delamination occurred in the semiconductor devices of Example 1 and Example 2.

このようにして作製される実施例の半導体装置のデラミネーションの発生防止の信頼性を確認するため、更に以下のテストを行った。
前述の封止樹脂密着強度評価用の専用フレーム（ベタ状板）に実施例１、実施例２に示す半導体装置のリードフレームと同じ表面処を施したものと、従来と同じ表面処理を施したリードフレームを用い、各加熱条件にて銅酸化膜の厚さとＡｇ存在領域をＸ線光電子分光分析法（ＥＳＣＡ）により調べた。
そして、各条件における樹脂の密着強度を前述と同様にして測定した。
図８（ａ）は各処理にて作製したリードフレームに対して、加熱条件を変えたときの表面からの酸化膜厚およびＡｇ存在領域を表面からの距離で示したものである。
また、図８（ｂ）は、各加熱処理後の樹脂密着強度を示したものである。
加熱条件Ｌは、１５０°Ｃ１時間、Ｈは２８０°Ｃ３分間、Ｎは加熱なしを表している。
リードフレームの表面処理条件は、（１）は実施例１に使用したリードフレームと同じ条件、（２）は実施例２で使用したリードフレーム同じ条件、（３）は薄い銀めっきを施さない、銅ストライクめっきのみを施した場合の条件、（４）は銅素材上に銅−銀合金めっきを施した場合のものである。 The following test was further performed to confirm the reliability of preventing delamination of the semiconductor device of the example manufactured as described above.
The above-described dedicated frame (solid plate) for evaluating the adhesion strength of the sealing resin was subjected to the same surface treatment as the lead frame of the semiconductor device shown in the first and second embodiments and the same surface treatment as the conventional one. Using a lead frame, under each heating condition, the thickness of the copper oxide film and the region where Ag was present were examined by X-ray photoelectron spectroscopy (ESCA).
Then, the adhesion strength of the resin under each condition was measured in the same manner as described above.
FIG. 8A shows the thickness of the oxide film from the surface and the region where Ag is present as a distance from the surface when the heating conditions are changed for the lead frame manufactured in each process.
FIG. 8B shows the resin adhesion strength after each heat treatment.
The heating conditions L represent 150 ° C. for 1 hour, H represents 280 ° C. for 3 minutes, and N represents no heating.
The surface treatment conditions of the lead frame are as follows: (1) is the same condition as the lead frame used in Example 1, (2) is the same condition as the lead frame used in Example 2, (3) is not subjected to thin silver plating, The condition when only copper strike plating is applied, (4) is the case when copper-silver alloy plating is applied on a copper material.

図８（ｂ）より、ワイヤボンディングに相当する加熱処理（２８０°Ｃ、３分間）後では、銅酸化膜領域全体にＡｇを含む（１）、（２）が、銅酸化膜領域全体にはＡｇを含まない（３）、（４）に比べ樹脂密着強度が優れていることが分かる。
そして、Ａｇを含まない銅酸化膜のみが形成される（３）が、（４）に比べて樹脂密着強度が劣っていることが分かる。
これより、実施例１、実施例２の半導体装置に使用されたリードフレームをワイヤボンディングに相当する加熱処理（２８０°Ｃ、３分間）にて処理したものの方が樹脂密着強度が優れていることが分かり、実施例１、実施例２の半導体装置は、デラミネーションの発生しずらいものと判断できる。 From FIG. 8B, after heat treatment (280 ° C., 3 minutes) corresponding to wire bonding, Ag is contained in the entire copper oxide film region (1) and (2), but not in the entire copper oxide film region. It can be seen that the resin adhesion strength is superior to (3) and (4) that do not contain Ag.
It can be seen that only the copper oxide film containing no Ag is formed (3), but the resin adhesion strength is inferior to (4).
Thus, the lead frame used in the semiconductor devices of Examples 1 and 2 was subjected to a heat treatment (280 ° C., 3 minutes) corresponding to wire bonding, and the resin adhesion strength was superior. Thus, it can be determined that the semiconductor devices according to the first and second embodiments hardly cause delamination.

又、（４）が、（３）に比べ、リードフレームをワイヤボンディングに相当する加熱処理（２８０°Ｃ、３分間）後、比較的良好な樹脂密着強度を得ることができたのは、表面から離れてはいるが銅酸化膜中に、Ａｇが存在しているためと思われる。   In addition, (4) can obtain relatively good resin adhesion strength after heating treatment (280 ° C., 3 minutes) corresponding to wire bonding of the lead frame as compared with (3), This is probably because Ag is present in the copper oxide film, although it is far from the copper oxide film.

また、（１）、（２）については、薄い銀めっき条件等を変え、酸化膜とＡｇの存在する層の厚さ、Ａｇの濃度を変えたものを幾つか作製し、調べてみたが、Ａｇ濃度はＸ線光電子分光分析法による分析で２０原子％未満が樹脂密着強度の点で適当と判断された。また、この場合、ワイヤボンディングに相当する加熱処理（２８０°Ｃ、３分間）においては、酸化膜とＡｇの存在する膜厚は２０００Å以上となることが分かった。   Regarding (1) and (2), some silver oxide conditions were changed and the thickness of the oxide film and the layer in which Ag was present, and the concentration of Ag were changed. Analysis of the Ag concentration by X-ray photoelectron spectroscopy revealed that an Ag concentration of less than 20 atomic% was appropriate in terms of resin adhesion strength. Further, in this case, it was found that the thickness of the oxide film and the Ag in the heat treatment (280 ° C., 3 minutes) corresponding to the wire bonding was 2000 ° or more.

また、別に上記（１）〜（４）の各条件に対応する半導体装置を作製して、デラミネーションの発生を調べてみたが、デラミネーションの発生に対しては、リードフレームをワイヤボンディングに相当する加熱処理（２８０°Ｃ、３分間）後の脂密着強度は、（３）の２００Ｎは不充分であるが、（４）でもかなりその発生は抑えられ実用レベルとなることも分かった。
（１）、（２）のように、樹脂密着強度が４００Ｎ以上あれば、デラミネーションの発生がほぼ防止できることも分かった。 In addition, a semiconductor device corresponding to each of the above conditions (1) to (4) was separately manufactured, and the occurrence of delamination was examined. For the occurrence of delamination, the lead frame was equivalent to wire bonding. It was also found that 200N of (3) was insufficient for the adhesive strength after the heat treatment (280 ° C., 3 minutes), but the occurrence was considerably suppressed even in (4), and it became a practical level.
As shown in (1) and (2), it was also found that when the resin adhesion strength was 400 N or more, the occurrence of delamination could be substantially prevented.

また、別に、参考実施例１のリードフレームにおいて、薄い銀めっきに代え、薄いパラジウムメッキ（以下、薄いＰｄめっきとも言う）を０．００１μｍ、０．０１μｍ、０、１μｍ、０．５μｍの厚さで設けたもの、および、銅合金上にＰｄめっきを１．０μｍの厚さで設けたもの、従来の薄いめっきを設けないものについて、ダイパッド裏面酸化膜の密着性、封止樹脂の密着強度を評価したが、以下の表２に示すように、表１に示す薄い銀めっきを設けた場合と、薄いＰｄめっきを設けた場合についても、ほぼ同じ結果が得られた。
尚、評価方法、条件は表１に示す薄い銀めっきを設けた場合と同じである。
（表２）
┌──────────┬────────┬────────┬───────┐
│ │薄いＰｄめっき厚│ダイパッド裏面の│封止樹脂密着性│
│ │ ［μｍ］│銅酸化膜密着性│ │
├──────────┼────────┼────────┼───────┤
│（１）全面Ｐｄめっき│ ０．００１ │ ○ │ ○ │
├──────────┼────────┼────────┼───────┤
│（２）全面Ｐｄめっき│ ０．０１ │ ○ │ ○ │
├──────────┼────────┼────────┼───────┤
│（３）全面Ｐｄめっき│ ０．１ │ ○ │ ○ │
├──────────┼────────┼────────┼───────┤
│（４）全面Ｐｄめっき│ ０．５ │ ○ │ ○ │
├──────────┼────────┼────────┼───────┤
│（５）全面Ｐｄめっき│ １．０ │ ○ │ × │
├──────────┼────────┼────────┼───────┤
│ Ｐｄめっきなし │薄いＰｄめっき │ │ │
│ （従来例） │無し │ × │ × │
└──────────┴────────┴────────┴───────┘ Separately, in the lead frame of Reference Example 1, instead of thin silver plating, thin palladium plating (hereinafter also referred to as thin Pd plating) has a thickness of 0.001 μm, 0.01 μm, 0, 1 μm, and 0.5 μm. The adhesion of the oxide film on the back surface of the die pad and the adhesion strength of the sealing resin were evaluated for those provided in the above, those provided with Pd plating on the copper alloy to a thickness of 1.0 μm, and those not provided with the conventional thin plating. As shown in Table 2, almost the same results were obtained when the thin silver plating shown in Table 1 was provided and when the thin Pd plating was provided, as shown in Table 2 below.
The evaluation method and conditions are the same as those in the case where the thin silver plating shown in Table 1 is provided.
(Table 2)
┌──────────┬────────┬────────┬───────┐
│ │ Thin Pd plating thickness │ Back side of die pad │ Sealing resin adhesion │
│ │ [μm] │Copper oxide film adhesion│ │
├──────────┼────────┼────────┼───────┤
│ (1) Pd plating on the entire surface│ 0.001 │ ○ │ ○ │
├──────────┼────────┼────────┼───────┤
│ (2) Pd plating on entire surface│ 0.01 │ ○ │ ○ │
├──────────┼────────┼────────┼───────┤
│ (3) Pd plating on entire surface│ 0.1 │ ○ │ ○ │
├──────────┼────────┼────────┼───────┤
│ (4) Pd plating on entire surface│ 0.5 │ ○ │ ○ │
├──────────┼────────┼────────┼───────┤
│ (5) Pd plating on the entire surface│ 1.0 │ ○ │ × │
├──────────┼────────┼────────┼───────┤
│ No Pd plating │ Thin Pd plating │ │ │
│ (conventional example) │ none │ × │ × │
└──────────┴────────┴────────┴───────┘

上記においては、リードフレームに薄い銀めっき、薄いＰｄめっきを施した場合について説明したが、薄い銀めっき、薄いＰｄめっきに代え、薄い金めっき、薄い白金めっきを施した場合や、これらの銀、Ｐｄ（パラジウム）、金、白金からなる薄いめっきも同様の作用効果が得られると判断される。
これらのリードフレームを用いた半導体装置についても、上記実施例と同様、同じ作用効果が得られると判断される。
また、部分銀めっきに代え、部分金めっき、部分パラジウムめっきとした場合にも、上記薄いめっきを設けることが有効であることは言うまでもない。 In the above, the case where the thin silver plating and the thin Pd plating are applied to the lead frame has been described, but instead of the thin silver plating and the thin Pd plating, the thin gold plating and the thin platinum plating are applied. It is determined that a similar plating effect can be obtained with a thin plating made of Pd (palladium), gold, and platinum.
It is determined that the same operation and effect can be obtained in the semiconductor device using these lead frames as in the above embodiment.
It is needless to say that the provision of the above-mentioned thin plating is also effective when partial gold plating or partial palladium plating is used instead of partial silver plating.

参考実施例１のリードフレームの概略図Schematic diagram of the lead frame of Reference Example 1 参考実施例２のリードフレームの概略図Schematic diagram of the lead frame of Reference Example 2 参考実施例のリードフレームの部分貴金属めっき方法の実施例１の工程概略図Process schematic diagram of Example 1 of partial noble metal plating method for lead frame of Reference Example 参考実施例の部分貴金属めっき方法の工程概略図Schematic diagram of the process of the partial noble metal plating method of the reference example 参考実施例のリードフレームを用いた半導体装置の製作工程を説明するための図FIG. 7 is a diagram for explaining a manufacturing process of a semiconductor device using the lead frame of the reference example. 銅酸化膜の状態を説明するための図Diagram for explaining the state of the copper oxide film 実施例の半導体装置の断面図Sectional view of a semiconductor device of an embodiment 実施例の半導体装置に用いたリードフレームの加熱処理と樹脂密着強度を説明するための図FIG. 6 is a view for explaining heat treatment and resin adhesion strength of a lead frame used in the semiconductor device of the example. 従来のリードフレームの概略図Schematic diagram of conventional lead frame 従来の半導体装置とリードフレームを説明するための図Diagram for explaining a conventional semiconductor device and a lead frame

符号の説明Explanation of reference numerals

１１０ リードフレーム
１１１ ダイパッド
１１２ インナーリード
１１３ アウターリード
１１４ ダムバー
１１５ 枠（フレーム）部
１１６ 吊りバー
１１０Ａ 外形加工されたリードフレーム
１２０ リードフレーム素材（銅合金）
１２０ａ 銅合金
１３０ 銅めっき
１３０Ａ 銅酸化膜
１３０Ａａ Ｃｕ2 Ｏ
１３０Ａｂ ＣｕＯ
１４０ 部分銀めっき
１４０Ａ 銀モレ部
１５０ 薄い銀めっき
１５０Ａ 拡散された銀の存在領域
１６０ 半導体素子
１６１ 電極パッド（端子）
１７０ 銀ペースト
１８０ ワイヤ（金線）
１９０ 封止用樹脂
２００ 半導体装置
１０００ 樹脂封止型半導体装置
１０１０ リードフレーム
１０１１ ダイパッド
１０１２ インナリード
１０１３ アウターリード
１０１４ ダムバー
１０１５ フレーム（枠）部
１０２０ 半導体素子
１０２１ 電極パッド（端子）
１０３０ ワイヤ
１０４０ 樹脂

110 Lead frame 111 Die pad 112 Inner lead 113 Outer lead 114 Dam bar 115 Frame (frame) part 116 Hanging bar 110A Lead frame 120 with external shape processed Lead frame material (copper alloy)
120a Copper alloy 130 Copper plating 130A Copper oxide film 130Aa Cu 2 O
130Ab CuO
140 Partial silver plating 140A Silver leakage part 150 Thin silver plating 150A Area where diffused silver exists 160 Semiconductor element 161 Electrode pad (terminal)
170 silver paste 180 wire (gold wire)
190 Sealing resin 200 Semiconductor device 1000 Resin-sealed semiconductor device 1010 Lead frame 1011 Die pad 1012 Inner lead 1013 Outer lead 1014 Dam bar 1015 Frame (frame) portion 1020 Semiconductor element 1021 Electrode pad (terminal)
1030 Wire 1040 Resin

Claims (1)

銅合金材からなり、ワイヤボンディング用ないしダイボンディング用の、銀、金、パラジウムの少なくとも１つからなる部分貴金属めっきが施された樹脂封止型の半導体装置用リードフレームで、且つ、少なくとも封止樹脂と接する側の銅部表面の全部ないし所定の部分に銀、金、白金、パラジウムの少なくとも１つからなる薄い貴金属めっきが施されているリードフレームを、用いた半導体装置であって、少なくとも封止用樹脂と接するリードフレーム表面の全部ないし所定の部分の銅酸化膜形成領域において、貴金属の濃度が、Ｘ線光電子分光による測定で、０．１原子％以上〜２０原子％未満であることを特徴とする半導体装置。

A resin-encapsulated lead frame for a semiconductor device made of a copper alloy material and partially plated with noble metal made of at least one of silver, gold and palladium for wire bonding or die bonding, and at least sealing A semiconductor device using a lead frame in which a thin noble metal plating made of at least one of silver, gold, platinum, and palladium is applied to all or a predetermined portion of a surface of a copper portion on a side in contact with a resin, The concentration of the noble metal in the entire or predetermined portion of the copper oxide film forming region of the lead frame surface in contact with the stopping resin is 0.1 atomic% or more and less than 20 atomic% as measured by X-ray photoelectron spectroscopy. Characteristic semiconductor device.

JP2004199764A 1995-09-29 2004-07-06 Semiconductor device Pending JP2004343136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004199764A JP2004343136A (en) 1995-09-29 2004-07-06 Semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP27507695 1995-09-29
JP32252395 1995-11-17
JP2004199764A JP2004343136A (en) 1995-09-29 2004-07-06 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP5531596A Division JP3594724B2 (en) 1995-09-29 1996-02-20 Partial precious metal plating method for lead frame

Publications (1)

Publication Number Publication Date
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235868B2 (en) * 2001-07-09 2007-06-26 Sumitomo Metal Mining Co., Ltd. Lead frame and its manufacturing method
JP2007180247A (en) * 2005-12-27 2007-07-12 Dainippon Printing Co Ltd Circuit member manufacturing method
JP2014110302A (en) * 2012-11-30 2014-06-12 Sumitomo Metal Mining Co Ltd Method for manufacturing lead frame
JP2015195389A (en) * 2015-06-17 2015-11-05 大日本印刷株式会社 Semiconductor device and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235868B2 (en) * 2001-07-09 2007-06-26 Sumitomo Metal Mining Co., Ltd. Lead frame and its manufacturing method
JP2007180247A (en) * 2005-12-27 2007-07-12 Dainippon Printing Co Ltd Circuit member manufacturing method
JP4620584B2 (en) * 2005-12-27 2011-01-26 大日本印刷株式会社 Circuit member manufacturing method
JP2014110302A (en) * 2012-11-30 2014-06-12 Sumitomo Metal Mining Co Ltd Method for manufacturing lead frame
JP2015195389A (en) * 2015-06-17 2015-11-05 大日本印刷株式会社 Semiconductor device and manufacturing method thereof

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