JP3701373B2 - Lead frame, lead frame partial noble metal plating method, and semiconductor device using the lead frame - Google Patents

Lead frame, lead frame partial noble metal plating method, and semiconductor device using the lead frame Download PDF

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Publication number
JP3701373B2
JP3701373B2 JP05531696A JP5531696A JP3701373B2 JP 3701373 B2 JP3701373 B2 JP 3701373B2 JP 05531696 A JP05531696 A JP 05531696A JP 5531696 A JP5531696 A JP 5531696A JP 3701373 B2 JP3701373 B2 JP 3701373B2
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Japan
Prior art keywords
lead frame
plating
noble metal
copper
thin
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Expired - Fee Related
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JP05531696A
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Japanese (ja)
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JPH09195068A (en
Inventor
日出男 堀田
千秋 初田
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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Priority to JP05531696A priority Critical patent/JP3701373B2/en
Priority to KR1019960043408A priority patent/KR100266726B1/en
Priority to US08/721,265 priority patent/US6034422A/en
Priority to CA002186695A priority patent/CA2186695C/en
Priority to DE19640256A priority patent/DE19640256B4/en
Priority to SG1996010754A priority patent/SG60018A1/en
Publication of JPH09195068A publication Critical patent/JPH09195068A/en
Priority to KR1020000009734A priority patent/KR100271424B1/en
Application granted granted Critical
Publication of JP3701373B2 publication Critical patent/JP3701373B2/en
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Description

【０００１】
【産業上の利用分野】
本発明は，封止樹脂とリードフレームとの密着性を向上させた半導体装置と、それに用いられるリードフレームに関する。
【０００２】
【従来の技術】
従来より、半導体装置の組立部材として用いられる（単層）リードフレームは、通常、コバール、４２合金（４２％ニッケル−鉄合金）、銅系合金のような金属から成り、プレス法もしくはエッチング法により形成されていた。
一般的なプラスチックパッケージであるＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）用のリードフレームは、図７（ｂ）（イ）に示すように、半導体素子を搭載するためのダイパッド７１１と、ダイパッド７１１の周囲に設けられた半導体素子と結線するためのインナーリード７１２と、該インナーリード７１２に連続して外部回路との結線を行うためのアウターリード７１３、樹脂封止する際のダムとなるダムバー７１４、リードフレーム７１０全体を支持するフレーム（枠）部７１５等を備えている。
そして、リードフレーム７１０は、図７（ａ）に示すように、ダイパッド部７１１をインナーリード７１２形成面よりもダウンセットした状態でダイパッド７１１に半導体素子７２０を搭載し、半導体素子７２０の電極パッド（端子）７２１とインナーリード７１２の先端部とを金などのワイヤ７３０で結線を行った後に、樹脂７４０にて封止して、ダムバー７１４部の切断工程、アウターリード７１３部のフオーミング工程を経て半導体装置７００を作製していた。
尚、図７（ｂ）（ロ）は、図７（ｂ）（イ）のＦ１−Ｆ２における断面図である。
【０００３】
このようなリードフレームは、半導体素子７２０の電極パッド（端子）７２１とインナーリード７１２の先端部とを金などのワイヤ７３０でワイヤボンディング（結線）、半導体素子の搭載の際に、強い結合力と導電性を確保するために、貴金属めっきを、少なくともインナーリード７１２先端部、ダイパッド７１１の半導体搭載側の面に施していた。貴金属めっきとしては、銀めっき処理が一般には採られていた。
【０００４】
従来のリードフレームにおいては、図６（ａ）に示すように、ダイパッド１１１の半導体素子搭載側とインナーリード１１２の先端部に、リードフレーム素材（銅合金）１２０上に、順に銅ストライクめっき１４０、銀めっき１５０を形成しており、その部分銀めっき工程は、図６（ｂ）に示すように、外形加工されたリードフレーム素材１２０に対し、脱脂、酸洗い等の前処理（図６（ｂ）（イ））を行ってから、一般に下地めっきとして０．１〜０．３μｍ厚程度の銅（Ｃｕ）ストライクめっきを施し（図６（ｂ）（ロ））、所望の領域に１．５〜１０μｍ厚の銀めっきが施こした（図６（ｂ）（ハ））後に、必要に応じて本来不要である部分に薄くついた銀（モレなど）を除去する電解剥離処理をしてから、ベンゾトリアゾール系等の有機系薬品により被膜を作り、酸化、水酸化による変色を防止する変色防止処理（図６（ｂ）（ニ））を施すものであった。
銀めっき方法としては、マスキング治具を用いリードフレームの所定領域を覆い露出部へ銀めっき液を吹きかけて部分的に銀めっきを施す方法や、リードフレームに電着レジストを塗膜した後、電着レジストを製版して所定の部分のみ露出した状態でめっき液に浸漬してめっきを施す方法等が用いられている。
このように、マスキング治具や電着レジストをマスクとしてリードフレームの所望の部分にのみめっきを施すことを部分めっきと言っており、図６に示す銀めっきのことを以下部分銀めっきと言う。
このような処理が施された銅合金を素材としたリードフレームにおいては、半導体装置の作製工程や半導体装置の実装工程においても、下地めっきが通常剥離することはなく、半導体装置に使用された場合にも、銅ストライク部の剥離はないとされていた。
【０００５】
しかしながら、最近、このような処理が施された銅合金を素材とするリードフレームを用いた場合、リードフレームに起因したパッケージのデラミネーション（剥離）が半導体装置組み立て工程や実装工程で生じていることが分かってきた。
尚、パッケージのデラミネーション（剥離）とは、ＩＣパッケージ内の各界面、即ちＩＣチップ（半導体素子）と封止用樹脂との界面、ダイボンディング剤とＩＣチップ（半導体素子）との界面等での剥離を言うが、リードフレームに起因するデラミネーション（剥離）は封止用樹脂とダイパッド裏面との界面での剥離等である。
封止用樹脂とダイパッド裏面との界面でのデラミネーション（剥離）の発生は、銅合金を素材とするリードフレームの表面処理や組み立て条件と密接な関係があることも次第に分かってきた。
銀めっきの下地めっきとして銅ストライクめっきが施こされ、銀めっき後に電解剥離と変色防止が施された、銅合金を素材とするリードフレームにおいては、ＩＣ（半導体装置）組み立て工程中の加熱工程で、銅合金表面に酸化膜が生じ、酸化膜と金属（銅合金）との間の密着強度が不十分であることが、デラミネーション（剥離）発生の原因と考えられている。
【０００６】
このような状況のもと、封止用樹脂とダイパッド裏面との界面、さらには、封止用樹脂とリードフレーム全面との界面の接着強度を向上させ、デラミ発生を防止するための方法として、特表平７−５０３１０３号（特願平５−５１２６８８号）等が提案されている。
特表平７−５０３１０３号（特願平５−５１２６８８号）では、クロムと亜鉛の混合体あるいはそれぞれの単体からなる薄い被膜で全面を覆ったリードフレームが開示されている。しかし、このリードフレームは、銀めっき部分も他の金属被膜で覆われるため、金ワイヤボンディング性が劣るという問題がある。
【０００７】
また、ＩＣ組み立て工程の条件は、組立を実施するＩＣメーカーにより異なり、銅合金製リードフレームの表面酸化状態、酸化膜形成過程もメーカー毎に異なる為、リードフレームに起因するデラミネーションの発生状況がＩＣ組み立てメーカーによって異なっていた。
例えば、ベンゾトリアゾール系の被膜により、銅の酸化、水酸化による変色を防止する処理方法では、ＩＣ組み立て温度が低いメーカに対しては、デラミネーション防止効果が得られるが、ＩＣ組み立て温度が高いメーカではデラミネーション防止効果が得られない。
このため、従来はデラミネーションに対する対策をＩＣ組み立て条件に合わせて各メーカ毎に行っていたのか実状で、ＩＣの組み立て条件によらず、リードフレームに起因するデラミネーションに対応できる手段が求められていた。
【０００８】
【発明が解決しようとする課題】
このように、銅合金製のリードフレームにおいては、リードフレーム表面の銅酸化膜生成に起因した半導体装置（ＩＣ）におけるデラミネーションを防止し、ＩＣの信頼性低下、ＩＣ組み立て工程、実装工程における良品率の低下を防止することが望まれており、特に、ＩＣの組み立て条件によらず、リードフレームに起因するデラミネーションの発生を防止できるものが求められていた。
本発明は、このような状況のもと、ＩＣの組み立て条件によらず、リードフレーム表面の銅酸化膜生成に起因したデラミネーションの発生を防止でき、且つ、ボンディング性を損なわない銅合金製のリードフレームを提供しようとするものである。
【０００９】
【課題を解決するための手段】
本発明のリードフレームは、銅合金材を母材とし、ワイヤボンディング用ないしダイボンディング用の、銀からなる部分貴金属めっきが施され、且つ、該部分貴金属めっきの下地めっきとして銅ストライクめっきを施してある樹脂封止型の半導体装置用リードフレームであって、銅合金材表面の全部に、銀からなる薄い貴金属めっきが施され、該薄い貴金属めっき上に銅めっきが形成されており、且つ、銅めっき上の所定の領域に前記部分貴金属めっきが形成されており、前記薄い貴金属めっきの厚みが０．５μｍ未満、０．００１μｍ以上であることを特徴とするものである。
本発明の半導体装置は、本発明のリードフレームを用いたことを特徴とするものであり、少なくとも封止用樹脂と接するリードフレーム表面の全部の銅酸化膜形成領域において、前記薄い貴金属の濃度が、Ｘ線光電子分光による測定で、０．１原子％以上〜２０原子％未満であることを特徴とするものである。
尚、上記において、部分貴金属めっきとは、リードフレームを用いて半導体装置を作製する際のワイヤボンディング用ないしダイボンディング用に、リードフレームのインナーリード先端部やダイバッド部の表面に貴金属めっきを施すもので、上記における所定の領域とは、このインナーリード先端部やダイバッド部の表面領域を言う。
一般には、マスキング治具を用い、リードフレームの所定の領域にのみめっき液を吹きつけて、または電着レジスト等により所定の領域のみをめっき液に接するようにしてリードフレーム全体をめっき液に浸しながら、リードフレームの所定領域にのみめっきを施す。
【００１０】
【作用】
本発明のリードフレームは、上記のような構成にすることにより、ＩＣの組み立て条件によらず、リードフレームに起因する半導体装置における封止樹脂のデラミネーションの発生を防止でき、且つ、ボンディング性を損なわない銅合金製のリードフレームの提供を可能としている。
詳しくは、少なくとも封止樹脂と接する側の銅合金材表面の全部ないし所定の部分に薄い貴金属めっきが施され、該薄い貴金属めっき上に銅めっきが形成されており、且つ、銅めっき上の所定の領域に部分貴金属めっきが形成されていることにより、リードフレーム表面の銅酸化膜に起因したデラミネーション（剥離）を防止できるものとしている。
即ち、薄い貴金属めっきが銅合金材の表面に施された箇所においては、貴金属はＩＣ組み立て工程中における加熱により銅酸化膜内部に拡散するため、銅合金材の表面に施された薄い貴金属めっきは銅めっき部および銅合金材の酸化を抑えて、酸化膜厚を低減するとともに、酸化膜生成の際にはＣｕＯよりＣＵ２Ｏの生成を優先させ、酸化膜自体が破壊されにくくなり、封止樹脂とのデラミネーションの発生を抑えることができるのである。
特に、半導体素子を搭載する側でないダイパッド裏面の銅部表面に、薄い貴金属めっき、銅めっきを順次施してある場合には、少なくとも、ダイパッド裏面でのリードフレーム表面の銅酸化膜に起因したデラミネーション（剥離）を効果的に防止できるものとしている。
また、薄い貴金属めっき、銅めっきが、リードフレーム表面全体に施した場合には、ダイパッド裏面を含みリードフレームと封止用樹脂との全ての界面でのリードフレーム表面の銅酸化膜に起因したデラミネーション（剥離）を防止できるものとしており、且つ、ダイパッドの裏面のみに部分的にめっきを施す場合と異なり、めっき用治具等を必要としないものとしている。
そして、薄い貴金属めっきの厚みを０．５μｍ以下、０．００１μｍ以上としていることにより、デラミネーション（剥離）の防止の効果が得られる適切な膜厚としている。
即ち、薄い貴金属めっきの厚みが０．００１μｍより薄い場合には、銅ストライクめっき中に拡散する銀の濃度が小さく、上記効果が得られず、厚みを０．５μｍより厚くするとめっき時間と費用がかかるばかりでなく、ＩＣ組み立て工程で貴金属が銅酸化膜内部に十分に拡散しないため封止樹脂との密着強度が劣化すると考えられる。
また、薄い貴金属めっきが銅めっきの下に施されているため、その後の貴金属めっき工程、ワイヤボンディング工程は、従来の処理と同様の工程にて処理でき、貴金属めっきの密着性も問題なく、ワイヤボンディング適性も問題がない。
また、半田めっき性に関しては、半田めっきの前処理として行われる酸洗浄や化学研磨処理によって銅酸化膜が除去される為、従来の図６（ａ）に示すリードフレームとかわらず良好である。
更に、部分貴金属めっきを施す際に、不要部分に貴金属モレが生じることが多々あり、これを電解剥離により除去をすることがあるが、薄い貴金属めっきが銅めっきの下に施されているため、薄い貴金属めっき部への影響を与えずに貴金属モレ部のみを除去することができる。
また、薄い貴金属めっきが銅めっきの下に施されているため、図６（ａ）に示す従来のものと同じ外観を確保できる。
また、部分貴金属めっきは部分銀めっきであり、且つ、薄い貴金属めっきが、薄い銀めっきであることにより、従来使用されている電解めっき方法や無電解めっき方法により、比較的簡単にめっきを安定的に行うことができ、生産コストを下げることができる。
【００１１】
本発明のリードフレームに係わるリードフレームの部分貴金属めっき方法としては、少なくとも、順に、（Ａ）外形加工された銅合金材からなるリードフレーム素材の表面の全部ないし所定の部分に、厚みが０．００１〜０．５μｍの銀、金、白金、パラジウムの少なくとも１つからなる薄い貴金属めっきを施す工程と、（Ｂ）薄い貴金属めっきが施されたリードフレームの表面の全部ないし少なくとも前記部分貴金属めっき領域を含む部分に銅めっきを施す工程と、（Ｃ）銅めっきが施されたリードフレームの表面の所定領域に部分貴金属めっきを施す工程とを有する、リードフレームの部分貴金属めっき方法が挙げられる。
ここにおいて、薄い貴金属めっきを、電解めっきないし無電解めっきにより施すものが挙げられ、更に、部分貴金属めっきは部分銀めっきであり、且つ、薄い貴金属めっきが薄い銀めっきであるものが挙げられる。
このような構成にすることにより、本発明のリードフレームの製造を可能とするものである。
そして、電解めっきないし無電解めっきにより薄い貴金属めっきを施すことにより、薄い貴金属めっきの膜厚の制御を簡単なものとしている。
特に、上記において、薄い貴金属めっき、銅めっきをリードフレーム全体に施す場合には、マスキング治具を必要とせず各めっきの被膜生成作業を簡単なものとできる。
尚、薄い貴金属めっきを施す方法としては、電解めっき、無電解めっきいずれも使用できるが、めっき速度を速くして、めっき厚を精度良く制御するためには電解めっき法が適し、複雑な形状であるリードフレームに対するめっきのつきまわり性を求める場合には無電解めっき法が適している。
上記において、部分貴金属めっきは部分銀めっきであり、且つ、薄い貴金属めっきが薄い銀めっきであることにより、従来使用の電解めっき方法や無電解めっき方法により比較的簡単に、めっきを安定的に行うことができるものとしている。同時に、金めっきや白金めっきに比べ生産コストを下げることができる。
【００１２】
本発明の半導体装置は、上記本発明のリードフレームを用いることにより、ワイヤボンディング工程における熱処理等を経て、封止樹脂と接するリードフレーム表面の全部ないし所定の部分に、金、銀、白金、パラジウムの少なくとも１つと銅酸化膜からなる領域をもつ表面部を形成でき、これにより、封止樹脂と接する部分の剥離を防止できるものとしている。
そして、封止樹脂と接するリードフレーム表面の全部ないし所定の部分の銅酸化膜形成領域において、貴金属の濃度が、Ｘ線光電子分光による測定で、０．１原子％以上であることにより、銅酸化膜ないし銅酸化膜と銅合金との境での破壊強度を充分なものとでき、２０原子％未満であることにより、封止樹脂との密着性が劣る銀の特質をカバーすることができ、銅酸化膜と封止樹脂との密着性を充分なものとしている。
【００１３】
【実施例】
本発明のリードフレームの実施例を以下、図にそって説明する。
先ず、実施例１のリードフレームを挙げて説明する。
図１は本発明のリードフレームの実施例１を示したもので、図１（ｂ）はその平面図を、図１（ａ）はＡ１−Ａ２における断面の要部拡大図である。
図１中、１１０はリードフレーム、１１１はダイパッド、１１２はインナーリード、１１３はアウターリード、１１４はダムバー、１１５はフレーム、１１６は吊りバー、１２０はリードフレーム素材（銅合金）、１３０は薄い銀めっき、１４０は銅めっき、１５０は部分銀めっきである。
本実施例のリードフレーム１１０は、厚さ０．１５ｍｍの銅合金材（古河電気工業株式会社製ＥＦＴＥＣ６４Ｔ−１／２Ｈ材）からエッチング加工により図１（ｂ）のような形状に外形加工されたリードフレーム素材１２０に対し、薄い銀めっき１３０、銅めっき１４０を順次、リードフレームの表面全面に施してから、この上に所定の領域にのみに部分銀めっき１５０を施したものである。
本実施例においては、薄い銀めっきを厚さ０．０１μｍ、銅めっきを厚さ０．１μｍ、部分銀めっきを厚さ３μｍとしたが、銅めっきの厚さとしては、０．１〜０．３μｍ、部分銀めっきの厚さとしては１．５〜１０μｍ、薄い銀めっき１３０の厚さとしては０．００１μｍ以上、０．５μｍ以下が好ましい。
また、リードフレーム素材１２０として古河電気工業株式会社製の銅合金ＥＦＴＥＣ６４Ｔ−１／２Ｈ材を用いているが、本発明はこれに限定されることはなく、他の銅合金でも良い。
【００１４】
本実施例のリードフレームは、図１（ａ）に示すように、外形加工されたリードフレーム素材１２０に対し、薄い銀めっき１３０、銅１４０を順次、全面に施してから、この上に所定の領域にのみに部分銀めっき１５０を施したものであり、薄い銀めっき１３０を設けていることにより、母材金属（銅合金材）と酸化膜との密着性が向上し、結果として、半導体装置を作製する場合には封止樹脂とのデラミネーションの発生を抑えることができるものとしている。
【００１５】
次に、実施例２のリードフレームを挙げて説明する。
図２は本発明のリードフレームの実施例２を示したもので、図２（ｂ）はその下面図を、図２（ａ）はＡ３−Ａ４における断面の要部拡大図である。
図２中、１１０はリードフレーム、１１１はダイパッド、１１２はインナーリード、１１３はアウターリード、１１４はダムバー、１１５はフレーム、１２０はリードフレーム素材（銅合金）、１３０は薄い銀めっき、１４０は銅めっき、１５０は部分銀めっきである。
本実施例のリードフレームが、実施例１と異なるのは、薄い銀めっき１３０を半導体素子を搭載する側でないダイパッド１１１の裏面にのみ施した点のみで、他は実施例１と同じである。
【００１６】
次に、実施例１、実施例２と併せ、変形例と比較例についての封止樹脂密着強度、酸化膜剥れ状態を評価した。
変形例１、変形例２、変形例３は、それぞれ実施例１と同じ構成のもので薄い銀めっきの厚さを０．１μｍ、０．５μｍ、１．０μｍとしたものである。
また、比較例１としては、図６に示す従来例で変色防止処理を施したものを、比較例２としては、従来例において変色防止処理を施して無い、ものを用いた。尚、上記実施例１、実施例２、変形例、比較例とも、銅めっきの厚さは０．１μｍ、部分銀めっきの厚さ３μｍとした。
封止樹脂密着強度は、封止樹脂密着強度評価用の専用フレーム（ベタ状板）に実施例１、各変形例および比較例と同じ表面処理を施し、ワイヤボンディング想定加熱条件、２８０°Ｃ、３分間の条件で加熱した後、銅合金材面に一定面積の封止樹脂を成形し、シエア法により密着強度を測定した。
さらに、試験後の封止樹脂への酸化膜の付着状態を観察し、母材からの酸化膜剥がれを評価した。
シエア法による密着強度の判定、酸化膜剥れの判定は、２．０Ｎ／ｍｍ２以上を可（○）とし、２．０Ｎ／ｍｍ２未満を不可（×）とした。

Figure 0003701373
Figure 0003701373
【００１７】
表１に示すように、薄い銀めっきを行った、実施例１、実施例２、変形例１、変形例２は、封止樹脂密着強度、酸化膜剥れの点において、図６に示す方法により部分銀めっきが施された比較例１よりも優れていることが分かった。また、比較例２は、酸化膜剥れの評価において、実施例１、実施例２、変形例１、変形例２に劣ることが分かった。
また、変形例３は封止樹脂密着強度の点で実施例１、実施例２、変形例１、変形例２に劣り、薄い銀めっきの厚さが厚過ぎても薄い銀めっきを設けることの効果がなくなることも分かる。
これより、上記本発明の実施例１、実施例２、変形例１、変形例２リードフレームが、図６（ｂ）に示す工程にてめっきされた従来のリードフレームに比べ、半導体装置に用いられた際には、銅酸化膜生成に起因するＩＣパッケージのデラミネーションの発生を効果的に抑えることができると判断される。
【００１８】
次に、本発明のリードフレームに係わるリードフレームの貴金属部分めっき方法の参考実施例を挙げ、図３に基づいて簡単に説明する。
本参考実施例のリードフレームの貴金属部分めっき方法は、上記本発明のリードフレームの実施例１を作製するためのめっき方法である。
尚、図３図は、図１（ａ）に相当する部分である。
先ず、エッチングにて外形加工された銅合金からなるリードフレーム１１０Ａの全面をアルカリ水溶液で電解脱脂し、純水で洗浄した後、酸性液で表面に形成されている酸化膜を除去する酸活性化処理を行い、リードフレーム素材１２０である銅合金の表面を活性化して、再度純水で洗浄した。（図３（ａ））
次いで、薄い銀めっき１３０をリードフレーム１１０Ａの全面に、厚さ０．０１μｍの厚さで形成した。（図３（ｂ））
尚、この薄い銀めっきは、シアン化銀水溶液中に浸漬して電解めっきにて行った。本発明のリードフレームの実施例２を作製する場合には、薄い銀めっきをダイパッド部のみに施すため、所定の部分をマスキングしてめっきを行う必要がある。
次いで、アルカリ中和処理、酸活性化処理を経て、純水でリードフレーム表面を洗浄した後、銀めっきが施されたリードフレーム１１０Ａの全面に、液温５０°Ｃで約２０秒間シアン化銅めっきを行い、０．１μｍの厚さで銅めっき１４０を施した。（図３（ｃ））
次いで、純水で銅めっき１４０が施されたリードフレーム１１０Ａ表面を洗浄した後、銀めっき処理時に不要な部分に銀が析出しないように、全面に銀の置換防止処理を行なった。
置換防止処理は、室温で有機硫黄系の溶液に浸し薄い被膜を形成したものである。次いで、リードフレームの半導体素子を搭載する側のダイバッド部、インナーリード先端領域のみを露出させるようにマスキング治具で覆い、リードフレームを陰極として、めっき液をノズルより噴射により吹きかける方式の部分めっきにより、厚さ３μｍの銀めっきをードフレームの所定の領域に施した後、純水でリードフレームを洗浄し、温風で乾燥して、実施例のリードフレームを得た。（図３（ｄ））
【００１９】
次に、本発明の半導体装置の実施例を挙げ、図にそって説明する。
実施例１の半導体装置は、上記本発明のリードフレームの実施例１を用いたもので、図４（ａ）はその概略断面図であり、図４（ｂ）は図４（ａ）のＢ１、Ｂ２における断面の状態を拡大して示したものである。
尚、説明を分かり易くするため、図６（ａ）に示す従来のリードフレームを用い、本実施例の半導体装置と同じ条件にて作製した半導体装置におけるＢ１、Ｂ２に相当する位置の状態を拡大して図４（ｃ）に示しておく。
本実施例の半導体装置は、図５（ｃ）に示すワイヤボンディング工程、図５（ｄ）に示す樹脂封止工程を経て作製されたものである。
【００２０】
実施例２の半導体装置は、上記本発明のリードフレームの実施例２を用いたもので、実施例１と同様、ワイヤボンディング工程、樹脂封止工程を経て作製されたものであるが、外見上は、図４に示す実施例１と同じであるが、表面の銅酸化膜の厚さや、拡散された銀の存在する領域が異なる。
実施例１、実施例２の半導体装置とも、デラミネーションの発生は見られなかった。
【００２１】
前述の実施例のリードフレームを用いて半導体装置（ＩＣパッケージ）を作製する工程を図５を用いて簡単に説明しておく。
先ず、図１に示す実施例のリードフレーム１１０のダイパッド１１１を、ダウンセット加工し（図５（ａ））、ダイパッド１１１上に銀ペースト１７０を介して半導体素子１６０を接合する。（図５（ｂ））
次いで、銀ペースト１７０を加熱キュアした後、半導体素子１６０の電極パッド（端子）１６１とリードフレーム１１０の部分銀めっき１４０が施されたインナーリード１１２の先端とをワイヤ（金線）１８０でワイヤボンディングして電気的に結線する。（図５（ｃ））
次いで、樹脂封止、ダムバーの除去、アウターリードのフォーミング処理、半田めっきを経て、半導体装置２００を得る。（図５（ｄ））
以上の工程を経て、図１に示すリードフレーム１１０表面の銅めっき１４０、ないしリードフレーム素材（銅合金）１２０の一部は酸化され、図５（ｃ）に示す銅酸化膜１９０を形成する。これと同時に、図１に示す銅めっき１４０下の薄い銀めっき１３０は、銅酸化膜１９０およびリードフレーム素材（銅合金）１２０中へ拡散される。
【００２２】
上記実施例のリードフレームを用いた半導体装置２００の作製方法においては、図５（ｃ）の段階で、加熱されたことによってダイパッド１１１における銅の表面では、Ｘ線光電子分光分析（ＥＳＣＡ）で観察すると、図４（ｂ）に示すようになっていた。
尚、図４（ｂ）中、２２０は銅酸化膜、２３０は拡散された銀の存在領域、１２０はリードフレーム素材（銅合金）を示している。
図１に示す薄い銀めっき１３０の銀は、銅酸化膜２２０及びリードフレーム素材（銅合金）２２０中に拡散され、拡散された銀の存在領域２３０は、図４（ｂ）に示すよう、銅酸化膜領域２２０とリードフレーム素材（銅合金）２１０の一部に跨がる。銅酸化膜領域２２０は、ＣｕＯ２２０Ｂを表面側にして、ＣｕＯ２２０ＢとＣｕ２Ｏ２２０Ａを形成する。
薄い銀めっき１３０の膜厚さ、加熱条件を変えることにより、銅酸化膜の内側に銀が拡散している状態が異なる。銀の拡散は銅酸化膜２２０のみならずリードフレーム素材（銅合金）１２０まで及ぶ。
【００２３】
これに対し、図５に示す工程と同じ工程にて、従来の図６（ａ）に示す、銅めっきと部分銀めっきのみを施したリードフレームを用い、半導体装置を作製した場合には、図５（ｃ）に相当する工程での銅の酸化状態は図４（ｃ）のようになる。
従来の図６（ａ）に示すリードフレームの場合には、銅表面に薄い銀めっきが施されていないため、銅の酸化は速く、結果的に酸化膜厚は、本実例の場合と比べ、厚くなり、且つ、銀の拡散が無いため、実施例のリードフレームを用いた場合に比べ、ＣｕＯよりＣｕ２Ｏの生成が優先されることはない。
【００２４】
図１、図２に示す実施例のリードフレーム１１０は、薄い銀めっき１３０を設けていることにより、図５（ｃ）の工程において、銅酸化膜２２０の形成を抑えている。即ち、図４（ｂ）、図４（ｃ）に示すように、実施例のリードフレームを用いて半導体装置を作製した場合には、薄い銀めっきを設けていない従来のリードフレームを用いた場合に比べ、銅酸化膜２２０の膜厚を低減していることが分かる。
また、実施例のリードフレーム１１０を用いた場合、銅酸化膜２２０生成の際、ＣｕＯよりＣｕ２Ｏの生成を優先させるため、銅酸化膜自体を破壊されにくくしており、結果として、樹脂封止した際には、封止樹脂とのデラミネーションの発生を抑えることかできるものとしている。
【００２５】
また、別に、本発明のリードフレームの実施例１において、薄い銀めっきに代え、薄いパラジウムめっき（以下Ｐｄめっきとも表現する。）を０．００１μｍ、０．０１μｍ、０、１μｍ、０．５μｍの厚さで設けたもの、および、リードフレーム素材（銅合金）上にＰｄめっきを１．０μｍの厚さで設けたもの、従来の薄いめっきを設けないものについて、ダイパッド裏面酸化膜の密着性、封止樹脂の密着強度を評価したが、以下の表２に示すように、表１に示す薄い銀めっきを設けた場合と、薄いＰｄめっきを設けた場合についても、ほぼ同じ結果が得られた。
尚、評価方法、条件は表１に示す薄い銀めっきを設けた場合と同じである。
Figure 0003701373
Figure 0003701373
【００２６】
上記においては、リードフレームに薄い銀めっき、薄いＰｄめっきを施した場合について説明したが、薄い銀めっき、薄いＰｄめっきに代え、薄い金めっき、薄い白金めっきを施した場合も同様の作用効果が得られると判断される。更に、これらの銀、Ｐｄ（パラジウム）、金、白金の複数種類からなる薄いめっきを施した場合も同様の作用効果が得られると判断される。
これらのリードフレームを用いた半導体装置についても、上記実施例と同様、同じ作用効果が得られると判断される。
また、部分銀めっきに代え、部分金めっき、部分Ｐｄめっきとした場合にも、上記薄いめっきを設けることが有効であることは言うまでもない。
【００２７】
【発明の効果】
本発明は、上記のように、ＩＣの組み立て条件によらず、リードフレームに起因するデラミネーションの発生を防止でき、且つ、ボンディング性を損なわない、銅合金製のリードフレームを用いた半導体装置の提供を可能としており、同時に、本発明の半導体装置に用いられるリードフレームと、その製造方法の提供を可能としている。
そしてまた、本発明のリードフレームの部分貴金属めっき方法は、本発明のリードフレームの製造を可能とするものであるが、特に、薄い貴金属めっきを均一性良く所定の厚さに形成できるものとしている。そして、薄い貴金属めっき、銅めっきをリードフレーム全体に施す場合には、マスキング治具を必要とせず各めっきの被膜生成作業を簡単なものとできる。
【図面の簡単な説明】
【図１】本発明のリードフレームの実施例１の概略図
【図２】本発明のリードフレームの実施例２の概略図
【図３】本発明のリードフレームの部分めっき方法の実施例工程図
【図４】本発明の半導体装置の概略図
【図５】本発明の半導体装置の製造製作工程図
【図６】従来のリードフレームの部分銀めっきとめっき工程を説明するための図
【図７】半導体装置とリードフレームを説明するための図
【符号の説明】
１１０ リードフレーム
１１０Ａ 外形加工された銅合金からなるリードフレーム
１１１ ダイパッド
１１２ インナーリード
１１３ アウターリード
１１４ ダムバー
１１５ フレーム
１１６ 吊りバー
１２０ リードフレーム素材（銅合金）
１３０ 薄い銀めっき
１４０ 銅めっき
１５０ 部分銀めっき
１６０ 半導体素子
１６１ 電極パッド（端子）
１７０ 銀ペースト
１８０ ワイヤ（金線）
１９０、２２０ 銅酸化膜
２００ 半導体装置
２１０ 封止樹脂
２２０Ａ Ｃｕ2 Ｏ
２２０Ｂ ＣｕＯ
２３０ 拡散された銀の存在領域
７００ 樹脂封止型半導体装置
７１０ リードフレーム
７１１ ダンパッド
７１２ インナリード
７１３ アウターリード
７１４ ダムバー
７１５ フレーム（枠）部
７２０ 半導体素子
７２１ 電極パッド（端子）
７３０ ワイヤ
７４０ 樹脂[0001]
[Industrial application fields]
The present invention relates to a semiconductor device having improved adhesion between a sealing resin and a lead frame, and a lead frame used therefor.
[0002]
[Prior art]
Conventionally, a (single layer) lead frame used as an assembly member of a semiconductor device is usually made of a metal such as Kovar, 42 alloy (42% nickel-iron alloy), or a copper alloy, by a pressing method or an etching method. Was formed.
A lead frame for QFP (Quad Flat Package), which is a general plastic package, is provided around a die pad 711 for mounting a semiconductor element and a die pad 711 as shown in FIGS. An inner lead 712 for connecting to the semiconductor element, an outer lead 713 for connecting to the external circuit continuously to the inner lead 712, a dam bar 714 serving as a dam for resin sealing, and the entire lead frame 710 Frame (frame) portion 715 and the like are provided.
Then, as shown in FIG. 7A, the lead frame 710 mounts the semiconductor element 720 on the die pad 711 in a state where the die pad portion 711 is down-set from the inner lead 712 formation surface, and the electrode pad ( The terminal 721 and the inner lead 712 are connected to each other with a wire 730 such as gold, and then sealed with a resin 740, followed by a cutting process for the dam bar 714 and a forming process for the outer lead 713. The device 700 was manufactured.
7B and 7B are cross-sectional views taken along line F1-F2 in FIGS. 7B and 7A.
[0003]
In such a lead frame, the electrode pad (terminal) 721 of the semiconductor element 720 and the tip of the inner lead 712 are wire-bonded (wired) with a wire 730 such as gold, and a strong bonding force is obtained when the semiconductor element is mounted. In order to ensure conductivity, noble metal plating is applied to at least the tip of the inner lead 712 and the surface of the die pad 711 on the semiconductor mounting side. As the noble metal plating, a silver plating process is generally adopted.
[0004]
In the conventional lead frame, as shown in FIG. 6 (a), the copper strike plating 140, in order, on the lead frame material (copper alloy) 120, on the semiconductor element mounting side of the die pad 111 and the tip of the inner lead 112, Silver plating 150 is formed, and the partial silver plating process is performed as shown in FIG. 6 (b) by performing preprocessing such as degreasing and pickling on the outer-shaped lead frame material 120 (FIG. 6 (b)). ) (A)), and then, generally, copper (Cu) strike plating with a thickness of about 0.1 to 0.3 μm is applied as a base plating (FIG. 6B (B)), and 1.5 to a desired region. After applying silver plating with a thickness of 10 μm (Fig. 6 (b) (c)), if necessary, after electrolytic stripping to remove silver (such as moles) thinly on the parts that are originally unnecessary , Benzotriazole, etc. A film was formed with mechanical chemicals, and a discoloration prevention treatment (FIG. 6B, (D)) for preventing discoloration due to oxidation and hydroxylation was performed.
Silver plating methods include a method in which a masking jig is used to cover a predetermined area of the lead frame and a silver plating solution is sprayed onto the exposed portion to apply silver plating partially. For example, a method of performing plating by immersing a plating resist in a plating solution in a state where only a predetermined portion is exposed is used.
In this way, plating only on a desired portion of the lead frame using a masking jig or an electrodeposition resist as a mask is referred to as partial plating, and the silver plating shown in FIG. 6 is hereinafter referred to as partial silver plating.
In lead frames made of copper alloys that have been treated in this way, the base plating does not usually peel off in the manufacturing process of semiconductor devices and the mounting process of semiconductor devices, and when used in semiconductor devices Moreover, it was supposed that there was no peeling of the copper strike part.
[0005]
However, recently, when using a lead frame made of a copper alloy that has been subjected to such treatment, package delamination due to the lead frame has occurred in the semiconductor device assembly process and mounting process. I understand.
Package delamination means each interface in an IC package, that is, an interface between an IC chip (semiconductor element) and a sealing resin, an interface between a die bonding agent and an IC chip (semiconductor element), and the like. The delamination (peeling) caused by the lead frame is a peeling at the interface between the sealing resin and the back surface of the die pad.
It has been gradually found that the occurrence of delamination (peeling) at the interface between the sealing resin and the back surface of the die pad is closely related to the surface treatment and assembly conditions of the lead frame made of copper alloy.
In a lead frame made of copper alloy that has been subjected to copper strike plating as a base plating for silver plating, and has undergone electrolytic peeling and discoloration prevention after silver plating, the heating process during the IC (semiconductor device) assembly process It is considered that an oxide film is formed on the surface of the copper alloy and the adhesion strength between the oxide film and the metal (copper alloy) is insufficient, which causes delamination.
[0006]
Under such circumstances, as a method for preventing the occurrence of delamination by improving the adhesive strength of the interface between the sealing resin and the back surface of the die pad, and further the interface between the sealing resin and the entire lead frame, Japanese Patent Application Laid-Open No. 7-503103 (Japanese Patent Application No. 5-512688) has been proposed.
Japanese Patent Application Laid-Open No. 7-503103 (Japanese Patent Application No. 5-512688) discloses a lead frame that covers the entire surface with a thin film made of a mixture of chromium and zinc or a single element of each. However, this lead frame has a problem that the gold wire bonding property is inferior because the silver-plated portion is also covered with another metal film.
[0007]
Also, the conditions of the IC assembly process vary depending on the IC manufacturer that performs the assembly, and the surface oxidation state of the copper alloy lead frame and the oxide film formation process also vary from manufacturer to manufacturer, so there is a situation where delamination occurs due to the lead frame. It was different depending on the IC assembly manufacturer.
For example, a treatment method that prevents discoloration due to copper oxidation and hydroxylation with a benzotriazole-based coating can provide a delamination prevention effect for manufacturers with low IC assembly temperatures, but manufacturers with high IC assembly temperatures. However, the delamination prevention effect cannot be obtained.
For this reason, whether measures against delamination have conventionally been taken for each manufacturer in accordance with the IC assembly conditions, there is a need for means capable of dealing with delamination caused by lead frames regardless of the IC assembly conditions. It was.
[0008]
[Problems to be solved by the invention]
As described above, in the lead frame made of copper alloy, delamination in the semiconductor device (IC) due to the formation of the copper oxide film on the surface of the lead frame is prevented, and the reliability of the IC is reduced, and the non-defective product in the IC assembly process and the mounting process. It has been desired to prevent a reduction in the rate, and in particular, a device capable of preventing the occurrence of delamination caused by the lead frame is required regardless of the assembly conditions of the IC.
Under such circumstances, the present invention is made of a copper alloy that can prevent the occurrence of delamination due to the formation of a copper oxide film on the lead frame surface and does not impair the bondability, regardless of the assembly conditions of the IC. It is intended to provide a lead frame.
[0009]
[Means for Solving the Problems]
  The lead frame of the present invention has a copper alloy material as a base material, is subjected to partial noble metal plating made of silver for wire bonding or die bonding, and is subjected to copper strike plating as an undercoat for the partial noble metal plating. A lead frame for a resin-encapsulated semiconductor device, wherein a thin noble metal plating made of silver is applied to the entire surface of a copper alloy material, and the copper plating is formed on the thin noble metal plating. The partial noble metal plating is formed in a predetermined region on the plating,The thickness of the thin noble metal plating is less than 0.5 μm and 0.001 μm or more.It is characterized by this.
  The semiconductor device of the present invention is characterized by using the lead frame of the present invention, and at least in the entire copper oxide film forming region on the surface of the lead frame in contact with the sealing resin,ThinThe concentration of the noble metal is not less than 0.1 atomic% and less than 20 atomic% as measured by X-ray photoelectron spectroscopy.
  In the above, the partial noble metal plating is a method in which noble metal plating is applied to the surface of the inner lead tip portion or die pad portion of the lead frame for wire bonding or die bonding when manufacturing a semiconductor device using a lead frame. Thus, the predetermined area in the above refers to the surface area of the inner lead tip and the die pad.
  In general, a masking jig is used to immerse the entire lead frame in the plating solution by spraying the plating solution only on a predetermined area of the lead frame or by contacting only the predetermined area with the plating solution using an electrodeposition resist or the like. However, plating is applied only to a predetermined region of the lead frame.
[0010]
[Action]
The lead frame of the present invention can prevent the occurrence of delamination of the sealing resin in the semiconductor device due to the lead frame regardless of the IC assembling condition, and has the bonding property by adopting the configuration as described above. It is possible to provide a lead frame made of copper alloy that is not damaged.
Specifically, a thin noble metal plating is applied to all or a predetermined portion of the surface of the copper alloy material on the side in contact with the sealing resin, the copper plating is formed on the thin noble metal plating, and the predetermined on the copper plating is provided. By forming the partial noble metal plating in this area, delamination (peeling) due to the copper oxide film on the surface of the lead frame can be prevented.
That is, in the place where the thin noble metal plating is applied to the surface of the copper alloy material, the noble metal diffuses inside the copper oxide film by heating during the IC assembly process, so the thin noble metal plating applied to the surface of the copper alloy material is While suppressing the oxidation of the copper plating part and the copper alloy material, the oxide film thickness is reduced, and at the time of generating the oxide film, CU is added from CuO2The generation of O is prioritized, and the oxide film itself is less likely to be destroyed, and the occurrence of delamination with the sealing resin can be suppressed.
In particular, if thin noble metal plating and copper plating are sequentially applied to the copper part surface on the backside of the die pad that is not the side where the semiconductor element is mounted, at least delamination caused by the copper oxide film on the leadframe surface on the backside of the die pad (Peeling) can be effectively prevented.
In addition, when thin noble metal plating or copper plating is applied to the entire lead frame surface, it is caused by a copper oxide film on the lead frame surface at all interfaces between the lead frame and the sealing resin, including the back surface of the die pad. Lamination (peeling) can be prevented, and unlike the case where plating is performed only on the back surface of the die pad, a plating jig or the like is not required.
Further, by setting the thickness of the thin noble metal plating to 0.5 μm or less and 0.001 μm or more, it is set to an appropriate film thickness that can obtain an effect of preventing delamination (peeling).
That is, when the thickness of the thin noble metal plating is less than 0.001 μm, the concentration of silver diffused during the copper strike plating is small, and the above effect cannot be obtained. If the thickness is more than 0.5 μm, the plating time and cost are reduced. In addition to this, it is considered that the adhesion strength with the sealing resin is deteriorated because the precious metal is not sufficiently diffused into the copper oxide film in the IC assembly process.
In addition, since the thin noble metal plating is applied under the copper plating, the subsequent noble metal plating process and wire bonding process can be processed in the same process as the conventional process, and there is no problem with the adhesion of the noble metal plating. There is no problem in bonding suitability.
Further, regarding the solder plating property, since the copper oxide film is removed by acid cleaning or chemical polishing performed as a pretreatment for solder plating, it is good regardless of the conventional lead frame shown in FIG.
Furthermore, when performing partial noble metal plating, there are many cases where noble metal leakage occurs in unnecessary portions, and this may be removed by electrolytic peeling, but since a thin noble metal plating is applied under the copper plating, Only the noble metal mole part can be removed without affecting the thin noble metal plating part.
Moreover, since the thin noble metal plating is performed under the copper plating, the same appearance as the conventional one shown in FIG.
In addition, partial noble metal plating is partial silver plating, and thin noble metal plating is thin silver plating, so that plating can be performed relatively easily and easily by conventional electrolytic plating methods and electroless plating methods. The production cost can be reduced.
[0011]
  Of the present inventionLead frame relatedFor the lead frame partial precious metal plating method,At least one of silver, gold, platinum, and palladium having a thickness of 0.001 to 0.5 μm is formed on the entire surface or a predetermined portion of the surface of the lead frame material made of the copper alloy material that has been processed in outline (A). A step of performing a thin precious metal plating comprising: (B) a step of performing copper plating on the entire surface of the lead frame subjected to the thin precious metal plating or a portion including at least the partial precious metal plating region; and (C) a copper plating. And a step of performing partial noble metal plating on a predetermined region of the surface of the applied lead frame.
Here, a thin precious metal plating is applied by electrolytic plating or electroless plating, and a partial precious metal plating is a partial silver plating, and a thin precious metal plating is a thin silver plating.
ThisWith this configuration, the lead frame of the present invention can be manufactured.
  Then, by applying a thin noble metal plating by electrolytic plating or electroless plating, the control of the film thickness of the thin noble metal plating is simplified.
  In particular, in the above, when thin noble metal plating or copper plating is applied to the entire lead frame, a masking jig is not required, and the coating film generation work for each plating can be simplified.
  Electrolytic plating and electroless plating can be used for thin noble metal plating. However, in order to increase the plating speed and control the plating thickness with high accuracy, the electrolytic plating method is suitable and has a complicated shape. The electroless plating method is suitable for determining the throwing power of plating on a certain lead frame.
  In the above, the partial noble metal plating is partial silver plating, and the thin noble metal plating is thin silver plating, so that plating can be performed stably and relatively easily by the conventional electrolytic plating method and electroless plating method. It is supposed to be possible. At the same time, production costs can be reduced compared to gold plating and platinum plating.
[0012]
By using the lead frame of the present invention, the semiconductor device of the present invention is subjected to heat treatment or the like in the wire bonding process, so that the entire surface of the lead frame in contact with the sealing resin or a predetermined portion has gold, silver, platinum, palladium It is possible to form a surface portion having a region composed of at least one of the above and a copper oxide film, thereby preventing peeling of a portion in contact with the sealing resin.
Then, in the entire region of the lead frame in contact with the sealing resin or the copper oxide film formation region in a predetermined portion, the concentration of the noble metal is 0.1 atomic% or more as measured by X-ray photoelectron spectroscopy. The fracture strength at the boundary between the film or the copper oxide film and the copper alloy can be sufficient, and by being less than 20 atomic%, it is possible to cover the characteristics of silver with poor adhesion to the sealing resin, Adhesion between the copper oxide film and the sealing resin is sufficient.
[0013]
【Example】
Embodiments of the lead frame of the present invention will be described below with reference to the drawings.
First, the lead frame of Example 1 will be described.
FIG. 1 shows a first embodiment of a lead frame according to the present invention, FIG. 1 (b) is a plan view thereof, and FIG. 1 (a) is an enlarged view of a main portion of a cross section taken along A1-A2.
In FIG. 1, 110 is a lead frame, 111 is a die pad, 112 is an inner lead, 113 is an outer lead, 114 is a dam bar, 115 is a frame, 116 is a suspension bar, 120 is a lead frame material (copper alloy), and 130 is thin silver Plating, 140 is copper plating, and 150 is partial silver plating.
The lead frame 110 of this example was externally processed into a shape as shown in FIG. 1B by etching from a 0.15 mm thick copper alloy material (EFTEC64T-1 / 2H material manufactured by Furukawa Electric Co., Ltd.). A thin silver plating 130 and a copper plating 140 are sequentially applied to the entire surface of the lead frame on the lead frame material 120, and then a partial silver plating 150 is applied only to a predetermined region thereon.
In this embodiment, the thin silver plating is 0.01 μm thick, the copper plating is 0.1 μm thick, and the partial silver plating is 3 μm thick. 3 μm, the thickness of the partial silver plating is preferably 1.5 to 10 μm, and the thickness of the thin silver plating 130 is preferably 0.001 μm or more and 0.5 μm or less.
Moreover, although the Furukawa Electric Co., Ltd. copper alloy EFTEC64T-1 / 2H material is used as the lead frame material 120, this invention is not limited to this and another copper alloy may be sufficient.
[0014]
In the lead frame of this embodiment, as shown in FIG. 1 (a), a thin silver plating 130 and copper 140 are sequentially applied to the entire surface of the lead frame material 120 that has been subjected to external processing, and then a predetermined amount is formed thereon. The partial silver plating 150 is applied only to the region, and by providing the thin silver plating 130, the adhesion between the base metal (copper alloy material) and the oxide film is improved. As a result, the semiconductor device In the case of manufacturing, the occurrence of delamination with the sealing resin can be suppressed.
[0015]
Next, the lead frame of Example 2 will be described.
FIG. 2 shows a second embodiment of the lead frame of the present invention, FIG. 2 (b) is a bottom view thereof, and FIG. 2 (a) is an enlarged view of a main part of a cross section taken along A3-A4.
In FIG. 2, 110 is a lead frame, 111 is a die pad, 112 is an inner lead, 113 is an outer lead, 114 is a dam bar, 115 is a frame, 120 is a lead frame material (copper alloy), 130 is thin silver plating, and 140 is copper. Plating, 150 is partial silver plating.
The lead frame of the present embodiment is the same as that of the first embodiment except that the thin silver plating 130 is applied only to the back surface of the die pad 111 that is not on the side where the semiconductor element is mounted.
[0016]
Next, together with Example 1 and Example 2, the sealing resin adhesion strength and the oxide film peeling state of the modified example and the comparative example were evaluated.
The first modification, the second modification, and the third modification have the same configuration as that of the first embodiment, and the thickness of the thin silver plating is 0.1 μm, 0.5 μm, and 1.0 μm.
Further, as Comparative Example 1, the conventional example shown in FIG. 6 that was subjected to the discoloration prevention process was used, and as Comparative Example 2, the conventional example that was not subjected to the discoloration prevention process was used. In all of Examples 1, 2 and the modified examples and comparative examples, the thickness of the copper plating was 0.1 μm and the thickness of the partial silver plating was 3 μm.
The sealing resin adhesion strength was determined by subjecting a dedicated frame (solid plate) for evaluation of sealing resin adhesion strength to the same surface treatment as in Example 1, each modification and comparative example, and assumed heating conditions for wire bonding, 280 ° C, After heating for 3 minutes, a certain area of sealing resin was formed on the copper alloy material surface, and the adhesion strength was measured by the shear method.
Furthermore, the adhesion state of the oxide film to the sealing resin after the test was observed to evaluate the oxide film peeling from the base material.
Judgment of adhesion strength by the shear method, judgment of oxide film peeling is 2.0 N / mm2The above is acceptable (○), 2.0 N / mm2Less than was regarded as impossible (x).
Figure 0003701373
Figure 0003701373
[0017]
As shown in Table 1, Example 1, Example 2, Modification 1 and Modification 2 in which thin silver plating was performed are the methods shown in FIG. 6 in terms of sealing resin adhesion strength and oxide film peeling. It turned out that it is superior to the comparative example 1 by which partial silver plating was given by. Moreover, it turned out that the comparative example 2 is inferior to Example 1, Example 2, the modification 1, and the modification 2 in evaluation of oxide film peeling.
Modification 3 is inferior to Example 1, Example 2, Modification 1 and Modification 2 in terms of sealing resin adhesion strength, and it is possible to provide thin silver plating even if the thickness of the thin silver plating is too thick. You can also see that the effect disappears.
As a result, the lead frame according to the first embodiment, the second embodiment, the first variation, and the second variation of the present invention is used in a semiconductor device as compared with the conventional lead frame plated in the process shown in FIG. In such a case, it is determined that the occurrence of delamination of the IC package due to the formation of the copper oxide film can be effectively suppressed.
[0018]
  Next, the present inventionLead frame relatedLead frame precious metal partial plating methodreferenceAn example will be given and will be briefly described with reference to FIG.
  BookreferenceThe noble metal partial plating method of the lead frame of the embodiment is a plating method for producing the lead frame of Embodiment 1 of the present invention.
  Note that FIG. 3 shows a portion corresponding to FIG.
  First, the entire surface of the lead frame 110A made of a copper alloy that has been externally processed by etching is electrolytically degreased with an alkaline aqueous solution, washed with pure water, and then acid activated to remove the oxide film formed on the surface with an acidic solution. The surface of the copper alloy, which is the lead frame material 120, was activated and washed again with pure water. (Fig. 3 (a))
  Next, a thin silver plating 130 was formed to a thickness of 0.01 μm on the entire surface of the lead frame 110A. (Fig. 3 (b))
  The thin silver plating was performed by electrolytic plating by dipping in a silver cyanide aqueous solution. In the case of producing the second embodiment of the lead frame of the present invention, since thin silver plating is applied only to the die pad portion, it is necessary to perform plating while masking a predetermined portion.
  Next, the surface of the lead frame is washed with pure water after alkali neutralization treatment and acid activation treatment, and then the copper cyanide is plated on the entire surface of the lead frame 110A subjected to silver plating at a liquid temperature of 50 ° C. for about 20 seconds. Plating was performed, and copper plating 140 was applied with a thickness of 0.1 μm. (Fig. 3 (c))
  Next, after cleaning the surface of the lead frame 110A on which the copper plating 140 was applied with pure water, a silver replacement prevention treatment was performed on the entire surface so that silver was not deposited on unnecessary portions during the silver plating treatment.
  The substitution prevention treatment is performed by immersing in an organic sulfur-based solution at room temperature to form a thin film. Next, by covering the die frame part on the side of the lead frame where the semiconductor element is mounted and the inner lead tip region with a masking jig so that only the lead area is exposed, and using the lead frame as a cathode, the plating solution is sprayed from the nozzle by spraying. After silver plating with a thickness of 3 μm was applied to a predetermined region of the dead frame, the lead frame was washed with pure water and dried with warm air to obtain the lead frame of the example. (Fig. 3 (d))
[0019]
Next, examples of the semiconductor device of the present invention will be given and described with reference to the drawings.
The semiconductor device of Example 1 uses Example 1 of the lead frame of the present invention, FIG. 4A is a schematic cross-sectional view thereof, and FIG. 4B is B1 of FIG. 4A. , B2 is an enlarged cross-sectional view.
For easy understanding, the conventional lead frame shown in FIG. 6A is used to expand the state of positions corresponding to B1 and B2 in a semiconductor device manufactured under the same conditions as the semiconductor device of this example. This is shown in FIG.
The semiconductor device of this example is manufactured through the wire bonding step shown in FIG. 5C and the resin sealing step shown in FIG.
[0020]
The semiconductor device of Example 2 uses the above-described lead frame of Example 2 of the present invention, and is manufactured through a wire bonding process and a resin sealing process, similar to Example 1, but in appearance. Is the same as that of the first embodiment shown in FIG. 4, but the thickness of the surface copper oxide film and the region where the diffused silver exists are different.
In the semiconductor devices of Examples 1 and 2, no delamination was observed.
[0021]
A process of manufacturing a semiconductor device (IC package) using the lead frame of the above-described embodiment will be briefly described with reference to FIG.
First, the die pad 111 of the lead frame 110 of the embodiment shown in FIG. 1 is downset (FIG. 5A), and the semiconductor element 160 is bonded onto the die pad 111 via the silver paste 170. (Fig. 5 (b))
Next, after the silver paste 170 is heated and cured, the electrode pads (terminals) 161 of the semiconductor element 160 and the tips of the inner leads 112 to which the partial silver plating 140 of the lead frame 110 is applied are wire-bonded with wires (gold wires) 180. And connect them electrically. (Fig. 5 (c))
Next, the semiconductor device 200 is obtained through resin sealing, dam bar removal, outer lead forming processing, and solder plating. (Fig. 5 (d))
Through the above steps, the copper plating 140 on the surface of the lead frame 110 shown in FIG. 1 or a part of the lead frame material (copper alloy) 120 is oxidized to form a copper oxide film 190 shown in FIG. At the same time, the thin silver plating 130 under the copper plating 140 shown in FIG. 1 is diffused into the copper oxide film 190 and the lead frame material (copper alloy) 120.
[0022]
In the manufacturing method of the semiconductor device 200 using the lead frame of the above embodiment, the copper surface of the die pad 111 is observed by X-ray photoelectron spectroscopy (ESCA) by being heated at the stage of FIG. Then, it was as shown in FIG.4 (b).
In FIG. 4B, reference numeral 220 denotes a copper oxide film, 230 denotes a diffused silver existing region, and 120 denotes a lead frame material (copper alloy).
The silver of the thin silver plating 130 shown in FIG. 1 is diffused into the copper oxide film 220 and the lead frame material (copper alloy) 220, and the diffused silver existing region 230 is a copper as shown in FIG. 4B. It straddles the oxide film region 220 and a part of the lead frame material (copper alloy) 210. The copper oxide film region 220 has CuO 220B and CuO 220B and Cu2O220A is formed.
By changing the thickness of the thin silver plating 130 and the heating conditions, the state in which silver diffuses inside the copper oxide film is different. The diffusion of silver reaches not only the copper oxide film 220 but also the lead frame material (copper alloy) 120.
[0023]
On the other hand, when a semiconductor device is manufactured by using the lead frame which is only subjected to copper plating and partial silver plating shown in FIG. 6A in the same process as the process shown in FIG. The oxidation state of copper in the process corresponding to 5 (c) is as shown in FIG. 4 (c).
In the case of the conventional lead frame shown in FIG. 6A, since thin silver plating is not applied to the copper surface, the oxidation of copper is fast, and as a result, the oxide film thickness is compared with the case of this example. Since it is thicker and there is no silver diffusion, it is more Cu than CuO than when the lead frame of the example is used.2O generation has no priority.
[0024]
The lead frame 110 of the embodiment shown in FIGS. 1 and 2 is provided with a thin silver plating 130, thereby suppressing the formation of the copper oxide film 220 in the step of FIG. 5C. That is, as shown in FIGS. 4B and 4C, when a semiconductor device is manufactured using the lead frame of the embodiment, a conventional lead frame without thin silver plating is used. It can be seen that the thickness of the copper oxide film 220 is reduced as compared with FIG.
In addition, when the lead frame 110 of the example is used, the CuO film 220 is formed by using CuO instead of CuO.2In order to give priority to the generation of O, the copper oxide film itself is not easily destroyed. As a result, when resin sealing is performed, it is possible to suppress the occurrence of delamination with the sealing resin.
[0025]
Separately, in Example 1 of the lead frame of the present invention, instead of thin silver plating, thin palladium plating (hereinafter also referred to as Pd plating) is 0.001 μm, 0.01 μm, 0, 1 μm, 0.5 μm. The adhesion of the oxide film on the back surface of the die pad with respect to the thickness provided, the thickness of Pd plating on the lead frame material (copper alloy) with a thickness of 1.0 μm, and the thickness without the conventional thin plating, The adhesion strength of the sealing resin was evaluated. As shown in Table 2 below, almost the same results were obtained when the thin silver plating shown in Table 1 was provided and when the thin Pd plating was provided. .
The evaluation method and conditions are the same as those when the thin silver plating shown in Table 1 is provided.
Figure 0003701373
Figure 0003701373
[0026]
In the above description, the case where thin silver plating and thin Pd plating are applied to the lead frame has been described. It is judged that it is obtained. Furthermore, it is judged that the same effect can be obtained when thin plating composed of a plurality of types of silver, Pd (palladium), gold, and platinum is applied.
It is determined that the same operation and effect can be obtained for the semiconductor device using these lead frames as in the above embodiment.
Needless to say, it is also effective to provide the above thin plating even when partial gold plating or partial Pd plating is used instead of partial silver plating.
[0027]
【The invention's effect】
As described above, the present invention provides a semiconductor device using a copper alloy lead frame that can prevent the occurrence of delamination caused by the lead frame and does not impair the bondability regardless of the IC assembly conditions. At the same time, it is possible to provide a lead frame used in the semiconductor device of the present invention and a manufacturing method thereof.
In addition, the lead frame partial noble metal plating method of the present invention enables the manufacture of the lead frame of the present invention. In particular, a thin noble metal plating can be formed with a uniform thickness to a predetermined thickness. . When thin precious metal plating or copper plating is applied to the entire lead frame, a masking jig is not required, and the coating film generation work for each plating can be simplified.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a lead frame according to a first embodiment of the present invention.
FIG. 2 is a schematic view of a lead frame according to a second embodiment of the present invention.
FIG. 3 is a process chart of an embodiment of the lead frame partial plating method of the present invention.
FIG. 4 is a schematic view of a semiconductor device of the present invention.
FIG. 5 is a manufacturing process diagram of the semiconductor device of the present invention.
FIG. 6 is a diagram for explaining partial silver plating and a plating process of a conventional lead frame.
FIG. 7 is a diagram for explaining a semiconductor device and a lead frame;
[Explanation of symbols]
110 Lead frame
110A Lead frame made of externally processed copper alloy
111 die pad
112 Inner lead
113 Outer lead
114 Dam Bar
115 frames
116 Hanging bar
120 Lead frame material (copper alloy)
130 Thin silver plating
140 Copper plating
150 Partial silver plating
160 Semiconductor device
161 Electrode pad (terminal)
170 Silver paste
180 wire (gold wire)
190, 220 Copper oxide film
200 Semiconductor device
210 Sealing resin
220A Cu2O
220B CuO
230 Area of diffused silver
700 Resin-encapsulated semiconductor device
710 Lead frame
711 Dunpad
712 Innerlead
713 Outer lead
714 Dam Bar
715 frame part
720 Semiconductor element
721 Electrode pad (terminal)
730 wire
740 resin

Claims (3)

銅合金材を母材とし、ワイヤボンディング用ないしダイボンディング用の、銀からなる部分貴金属めっきが施され、且つ、該部分貴金属めっきの下地めっきとして銅ストライクめっきを施してある樹脂封止型の半導体装置用リードフレームであって、銅合金材表面の全部に、銀からなる薄い貴金属めっきが施され、該薄い貴金属めっき上に銅めっきが形成されており、且つ、銅めっき上の所定の領域に前記部分貴金属めっきが形成されており、前記薄い貴金属めっきの厚みが０．５μｍ未満、０．００１μｍ以上であることを特徴とするリードフレーム。Resin-encapsulated semiconductor using a copper alloy material as a base material, which is subjected to partial noble metal plating made of silver for wire bonding or die bonding, and copper strike plating as an undercoat for the partial noble metal plating A lead frame for a device, wherein a thin noble metal plating made of silver is applied to the entire surface of the copper alloy material, the copper plating is formed on the thin noble metal plating, and a predetermined region on the copper plating is formed. The lead frame, wherein the partial noble metal plating is formed, and the thickness of the thin noble metal plating is less than 0.5 μm and not less than 0.001 μm . 請求項１に記載のリードフレームを用いたことを特徴とする半導体装置。Semiconductor device characterized by using the serial mounting lead frame in claim 1. 請求項２における半導体装置の、少なくとも封止用樹脂と接するリードフレーム表面の全部の銅酸化膜形成領域において、前記薄い貴金属の濃度が、Ｘ線光電子分光による測定で、０．１原子％以上〜２０原子％未満であることを特徴とする半導体装置。The semiconductor device definitive to claim 2, in all of the copper oxide film forming region of the lead frame surface in contact with at least the sealing resin, the concentration of the thin noble metal, as measured by X-ray photoelectron spectroscopy, 0.1 atomic% or more A semiconductor device characterized by being less than ˜20 atomic%.
JP05531696A 1995-09-29 1996-02-20 Lead frame, lead frame partial noble metal plating method, and semiconductor device using the lead frame Expired - Fee Related JP3701373B2 (en)

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JP05531696A JP3701373B2 (en) 1995-11-17 1996-02-20 Lead frame, lead frame partial noble metal plating method, and semiconductor device using the lead frame
KR1019960043408A KR100266726B1 (en) 1995-09-29 1996-09-25 Lead frame, method for partially plating lead frame with noble meta and semiconductor device formed by using the lead frame
US08/721,265 US6034422A (en) 1995-09-29 1996-09-26 Lead frame, method for partial noble plating of said lead frame and semiconductor device having said lead frame
CA002186695A CA2186695C (en) 1995-09-29 1996-09-27 Lead frame, method for partial noble plating of said lead frame and semiconductor device having said lead frame
DE19640256A DE19640256B4 (en) 1995-09-29 1996-09-30 Lead frame, method for precious metal plating of the lead frame and semiconductor device with lead frame
SG1996010754A SG60018A1 (en) 1995-09-29 1996-09-30 Lead frame method for partial noble plating of said lead frame and semiconductor device having said lead frame
KR1020000009734A KR100271424B1 (en) 1995-09-29 2000-02-28 Method for partial noble plating of a lead frame and semiconductor device having said lead frame

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US20070001802A1 (en) * 2005-06-30 2007-01-04 Hsieh Ching H Electroplating method in the manufacture of the surface mount precision metal resistor
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