JPH09326470A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the AC characteristics of an open drain output circuit to be evaluated without deteriorating the integration degree in a semiconductor device having the open drain output circuit. SOLUTION: The output from an inverter circuit made of a P channel transistor 102 and an N transistor 103 is connected to the gate of an N channel transistor 104 and the source thereof is connected to the VSS potential. Besides, the output terminals of a plurality of open drain output circuits 101, 201 in such a constitution are connected to the drains of respective transmission gates 110, 111 through the intermediary of respective electrode pads 105, 205 while the source of respective transmission gates are connected to unused electrode pad 107 through the intermediary of a resistant element 108 formed on a scribe line. Accordingly, the DC characteristics and the AC characteristics of a plurality of open drain circuits can be evaluated by one resistor element 108 and one unused electrode pad 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit device in a semiconductor device.

[0002]

2. Description of the Related Art In a conventional semiconductor device, as shown in FIG. 2, an input circuit, an output circuit and a power supply circuit are formed in an input / output circuit cell region, and each circuit is connected to an electrode pad.

In the prior art shown in FIG. 2, a signal from an internal logic is connected to the gates of a P-channel type transistor (hereinafter referred to as Pch transistor) 102 and an N-channel type transistor (hereinafter referred to as Nch transistor) 103, The source of the Pch transistor 102 is the first
The source of the Nch transistor 103 is connected to a power supply line (hereinafter referred to as VDD potential), and the source of the Nch transistor 103 is connected to a second power supply line (hereinafter referred to as VSS potential) to connect the Pch transistor 102 and Nc.
The drain of the h transistor 103 is connected to form an inverter circuit, the output of the inverter circuit is connected to the gate of the Nch transistor 104, and the source of the Nch transistor 104 is connected to the VSS potential. The open drain circuit 101 is an input / output circuit. It is formed in the cell region. The output terminal of the open drain output circuit 101 is connected to the electrode pad 105, supplies an internal signal to the outside, and cuts the scribe line 109 to form each chip. In addition to the open drain output circuit 101, an input circuit, a power supply circuit, and an unused cell are formed in the input / output circuit cell region.

[0004]

However, in the above-mentioned conventional technique, as shown in FIG.
Since the drain of is connected to the electrode pad 105,
Since only the “L” level or “Z” (high impedance) signal can be obtained at the electrode pad 105, the delay time (AC characteristic) of the open drain circuit 101 cannot be obtained.

Therefore, the present invention is intended to solve such a problem, and an object thereof is to provide that the DC characteristic of an open drain circuit and the delay time (AC characteristic) can be obtained. Where it is.

[0006]

In order to solve the above-mentioned problems, the semiconductor device of the present invention has first to Nth open drain output circuits formed in the input / output circuit cell region formed in the periphery of the chip. The first to Nth electrode pads connected to the output terminals of the first to Nth open drain output circuits are connected to the first impurity diffusion regions of the first to Nth first conductivity type transistors formed on the scribe. And the first
The second impurity diffusion region of the first-conductivity-type transistor of .about.N through the resistance element formed on the scribe line,
It is characterized in that it is connected to the (N + 1) th electrode pad.

Also, the open drain output circuit is
It is characterized by being an output circuit of a P-channel type or N-channel type transistor.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A semiconductor device of the present invention will be described below with reference to FIG.

FIG. 1 is a diagram showing a main part of a semiconductor device according to the present invention.

As shown in FIG. 1, the signal from the internal logic is connected to the gates of the Pch transistor 102 and the Nch transistor 103, and the Pch transistor 102 is connected.
Of the Pch transistor 10 is connected to the VDD potential and the source of the Nch transistor 103 is connected to the VSS potential.
2 and the drain of the Nch transistor 103 are connected,
Construct an inverter circuit.

The output of the inverter circuit is connected to the gate of the Nch transistor 104, and the Nch transistor 10 is connected.
As for the source of No. 4, an open drain circuit 101 connected to the VSS potential is formed in the input / output circuit cell region. The output terminal of the open drain output circuit 101 is connected to the electrode pad 105, is connected to the drain of the transmission gate 110 formed on the scribe line 109 from the electrode pad 105, and is connected to the source of the transmission gate 110 from the source of the impurity diffusion layer and the poly. Scribe line 10 with silicon etc.
9 is connected to an unused electrode pad 107 via a resistance element 108 formed on the surface 9. Similarly, the output terminal of the open drain circuit 201 is the electrode pad 205.
To the scribe line 10 from the electrode pad 205.
9 is connected to the drain of the transmission gate 111 formed on the substrate 9, and the source of the transmission gate 111 is connected to the resistance element 108 formed on the scribe line 109 by an impurity diffusion layer, polysilicon, or the like. By adopting such a configuration, the pad
The potential of the open drain output circuit 101 can be "L" level or "H" level by supplying a potential to the transmission gate 110 to activate it. Therefore, it is possible to obtain the delay time when changing from the “L” level to the “H” level and the delay time when changing from the “H” level to the “L” level. Also, when evaluating the open drain output circuit 201, the transmission gate 1
The same evaluation can be performed by setting 11 to the operating state. Therefore, it is possible to evaluate the DC characteristics and AC characteristics of a plurality of open drain output circuits with one resistance element and one unused electrode pad.

The semiconductor device described here is Nc
Although it is an open drain output circuit of h transistor,
It goes without saying that the same applies to the open drain output circuit of the Pch transistor. It goes without saying that the same applies to the transmission gates regardless of the combination of Pch and Nch.

[0013]

As described above, according to the semiconductor device of the present invention, the AC characteristics of the open drain output circuit can be evaluated without impairing the degree of integration.

[Brief description of drawings]

FIG. 1 is a top view of an embodiment of an output circuit of the present invention.

FIG. 2 is a top view of a prior art output circuit.

[Explanation of symbols]

101, 201 ... Open drain output circuit 102 ... P-channel transistor of pre-buffer circuit 103 ... N-channel transistor of pre-buffer circuit 104 ... N-channel transistor of output driver 105, 205 ... Pad electrode 106 ... Input / output circuit cell region 107 ... Unused electrode pad 108 ... Resistive element 109 ... Scribing line 110, 111 ... Transmission gate

Claims (3)

[Claims] 1. A first to Nth open drain output circuit is formed in an input / output circuit cell region formed in a peripheral portion of a chip and is connected to an output terminal of the first to Nth open drain output circuit. The electrode pads 1 to N are connected to the first impurity diffusion regions of the first to N-th first conductivity type transistors formed on the scribe, and the second impurity diffusions of the first to N-th first conductivity type transistors are connected. A region is connected to the (N + 1) th electrode pad via a resistance element formed on the scribe line. 2. The semiconductor device according to claim 1, wherein the open drain output circuit is an N-channel transistor output circuit. 3. The semiconductor device according to claim 1, wherein the open drain output circuit is an output circuit of a P-channel type transistor.