KR890012399A - Semiconductor Integrated Circuits with CMOS Inverters - Google Patents

Semiconductor Integrated Circuits with CMOS Inverters Download PDF

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KR890012399A
KR890012399A KR1019890000244A KR890000244A KR890012399A KR 890012399 A KR890012399 A KR 890012399A KR 1019890000244 A KR1019890000244 A KR 1019890000244A KR 890000244 A KR890000244 A KR 890000244A KR 890012399 A KR890012399 A KR 890012399A
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Prior art keywords
insulating layer
channel
inverter
integrated circuit
semiconductor integrated
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KR1019890000244A
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Korean (ko)
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KR910009356B1 (en
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다이지 에마
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야마모도 다꾸마
후지쓰 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

내용 없음.No content.

Description

CMOS인버터를 갖는 반도체 집적회로Semiconductor Integrated Circuits with CMOS Inverters

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1(a)도는 종래의 이중단 인버터회로의 회로도,1 (a) is a circuit diagram of a conventional dual stage inverter circuit,

제1(b)도는 제1(a)도에 보인 이중단 인버터회로의 일부를 나타내는 IC칩상의 기본창지의 예시적 배열을 나타내는 개략평면도,FIG. 1 (b) is a schematic plan view showing an exemplary arrangement of base windows on an IC chip showing a part of the dual stage inverter circuit shown in FIG. 1 (a);

제2(a)도는 기본장치의 배열을 나타내는 도면으로서 제1(a)도에 보인 이중단인버터에 대응한 IC칩의 일부를 나타내는 본 발명의 제1실시예의 개략평면도,FIG. 2 (a) is a schematic plan view of the first embodiment of the present invention showing a part of the IC chip corresponding to the dual stage inverter shown in FIG.

제2(b)도는 제2(a)도에서 쇄선 XX'를 따라 취한 제2(a)도 장치의 개략횡단 단면도,FIG. 2 (b) is a schematic cross sectional view of the device of FIG. 2 (a) taken along the broken line XX 'in FIG. 2 (a),

제3(a)도는 제2(a)도에 대응하는 부분을 나타내는 본 발명의 제2실시예의 개략평면도,3 (a) is a schematic plan view of a second embodiment of the present invention showing a part corresponding to FIG. 2 (a);

제3(b)도는 제3(a)도에 점선 YY'를 따라 취한 제3(a)도의장치의 개략절취도,3 (b) is a schematic cutaway view of the apparatus of FIG. 3 (a) taken along the dashed line YY ′ in FIG. 3 (a),

제4도는 본 발명의 적용될 수 있는 DRAM셀의 부분횡단면도.4 is a partial cross-sectional view of a DRAM cell to which the present invention can be applied.

Claims (10)

콤프리멘타리 금속산화막 반도체(CMOS)형 인버터를 갖는 반도체 집적회로에서, 상기 인버터는 상기 인버터에 전원을 공급하기 위한 제1 및 제2전원선들과, 한쌍의 p-채널 및 n-채널 금속산화막 반도체형 전계효과 트랜지스터(MOS FETs)를 포함하며, 상기 MOS FETs는 상기 제1 및 제2전원선들 간에 직렬로 서로 연결되며 각 MOS FETs의 게이트는 입력신호를 공통 수신하기 위한 게이트전극으로 서로 연결되며, 상기 p-채널 MOS FET의 소오스영역은 상기 제1전원선에 연결되며, 상기 n-채널 MOS FET의 소오스영역은 상기 제2전원선에 연결되며, 또한 상기 p-채널 MOS FET와 n-채널 MOS FET의 드레인들은 드레인 접촉전극으로 서로 연결되며, 상기 드레인 접촉전극은 고용융점 금속의 실리사이드를 포함하는 도전체로 구성되며, 상기 제1 및 제2전원선들은 인버터의 다른 소자들을 피복하는 절연층상에 비치되는 것이 특징인 CMOS인버터를 갖는 반도체 집적회로.In a semiconductor integrated circuit having a complimentary metal oxide semiconductor (CMOS) type inverter, the inverter includes first and second power lines for supplying power to the inverter, a pair of p-channel and n-channel metal oxide films. Semiconductor field effect transistors (MOS FETs), wherein the MOS FETs are connected to each other in series between the first and second power lines, and the gates of each of the MOS FETs are connected to each other as a gate electrode for receiving a common input signal. And a source region of the p-channel MOS FET is connected to the first power line, and a source region of the n-channel MOS FET is connected to the second power line, and the p-channel MOS FET and n-channel Drains of the MOS FETs are connected to each other by a drain contact electrode, and the drain contact electrode is formed of a conductor including a silicide of a high melting point metal, and the first and second power lines avoid the other elements of the inverter. A semiconductor integrated circuit having a CMOS inverter characterized in that the copy is provided on an insulating layer. 제1항에서, 제1절연층과 제2절연층을 더 포함하되, 상기 드레인 접촉전극은 상기 게이트전극과 상기 p-채널 및 n-채널 MOS FETs를 피복하는 상기 제1절연층상에 배치되고, 상기 제1 및 제2전원선들은 상기 접촉전극과 상기 제1절연층을 피복하는 상기 제2절연층상에 배치되는 것이 특징인 CMOS인버터를 갖는 반도체 직접회로The semiconductor device of claim 1, further comprising a first insulating layer and a second insulating layer, wherein the drain contact electrode is disposed on the first insulating layer covering the gate electrode and the p-channel and n-channel MOS FETs. And the first and second power lines are disposed on the second insulating layer covering the contact electrode and the first insulating layer. 콤프리멘타리 금속산화막 반도체(CMOS)형 인버터를 갖는 반도체 집적회로에서, 상기 인버터는 상기 인버터에 전원을 공급하기 위한 제1 및 제2전원선들과, 한쌍의 p-채널 및 n-채널 금속산화막 반도체형 전계효과 트랜지스터(MOS FETs)를 포함하며, 상기 MOS FETs는 상기 제1 및 제2전원선들 간에 직렬로 서로 연결되며 각 MOS FETs의 게이트는 입력신호를 공통 수신하기 위한 게이트전극으로 서로 연결되며, 상기 p-채널 MOS FET의 소오스영역은 상기 제1전원시에 연결되며, 상기 n-채널 MOS FET의 소오스영역은 상기 제2전원선에 연결되며, 또한 상기 p-채널 MOS FET와 n-채널 MOS FET의 드레인들은 서로 연결되며, 상기 p-채널 MOS FET와 n-채널 MOS FET의 드레인들은 고용융점 금속의 실리사이드를 포함하는 도전체로 구성되며, 상기 드레인 접촉전극들은 또 다른 도전금속으로 서로 연결되며, 상기 제1 및 제2전원선과 상기 또 다른 도전체는 인버터의 다른 소자를 피복하는 절연층상에 배치되는 것이 특징인 CMOS인버터를 갖는 반도체 집적회로.In a semiconductor integrated circuit having a complimentary metal oxide semiconductor (CMOS) type inverter, the inverter includes first and second power lines for supplying power to the inverter, a pair of p-channel and n-channel metal oxide films. Semiconductor field effect transistors (MOS FETs), wherein the MOS FETs are connected to each other in series between the first and second power lines, and the gates of each of the MOS FETs are connected to each other as a gate electrode for receiving a common input signal. And a source region of the p-channel MOS FET is connected at the first power supply, a source region of the n-channel MOS FET is connected to the second power supply line, and the p-channel MOS FET and n-channel The drains of the MOS FETs are connected to each other, and the drains of the p-channel MOS FET and the n-channel MOS FET are composed of a conductor including silicide of a high melting point metal, and the drain contact electrodes are made of another conductive metal. Is connected, it said first and second power supply lines and the other conductor is a semiconductor integrated circuit having a CMOS inverter which is characterized by being disposed on the insulating layer covering the other element of the inverter. 제3항에서, 제1절연층과 제2절연층을 더 포함하되, 상기 드레인 접촉전극은 상기 게이트전극과 상기 p-채널 및 n-채널 MOS FETs를 피복하는 상기 제1절연층상에 배치되고, 상기 제1 및 제2전원선과 상기 또 다른 도전체는 상기 접촉전극과 상기 제1절연층을 피복하는 제2절연층상에 배치되는 것이 특징인 CMOS인버터를 갖는 반도체 집적회로.The semiconductor device of claim 3, further comprising a first insulating layer and a second insulating layer, wherein the drain contact electrode is disposed on the first insulating layer covering the gate electrode and the p-channel and n-channel MOS FETs. And the first and second power lines and the other conductor are disposed on a second insulating layer covering the contact electrode and the first insulating layer. 제1 또는 3항에서, 상기 실리사이드는 텅스텐과 몰리브데늄 중 적어도 하나를 포함하는 금속류와 실리콘으로 구성되는 것이 특징인 CMOS인버터를 갖는 반도체 집적회로.4. The semiconductor integrated circuit as claimed in claim 1 or 3, wherein the silicide is made of metal and silicon including at least one of tungsten and molybdenum. 제2 또는 4항에서, 상기 또 다른 도전체는 상기 인버터의 출력신호를 상기 인버터의 연속단회로에 전송하기 위한 신호선을 구성하는 것이 특징인 CMOS인버터를 갖는 반도체 집적회로.5. The semiconductor integrated circuit according to claim 2 or 4, wherein the another conductor constitutes a signal line for transmitting an output signal of the inverter to a continuous end circuit of the inverter. 제2 또는 4항에서, 상기 제1절연층은 이산화 실리콘층이며, 상기 제2절연층은 포스포 실리케이트 글라스(PSG) 또는 보론실리케이트 글라스(BSG)층인 것이 특징인 CMOS인버터를 갖는 반도체 집적회로.The semiconductor integrated circuit of claim 2, wherein the first insulating layer is a silicon dioxide layer, and the second insulating layer is a phosphosilicate glass (PSG) or boron silicate glass (BSG) layer. 제1 또는 3항에서, 상기 실리사이드는 집적회로의 다른 회로들을 구성하기 위해 사용되는 동일한 실리사이드층인 것이 특징인 CMOS인버터를 갖는 반도체 집적회로.4. The semiconductor integrated circuit as claimed in claim 1 or 3, wherein the silicide is the same silicide layer used to configure other circuits of the integrated circuit. 제8항에 있어서, 상기 다른 회로는 다이나믹 메모리 셀들의 비트선들인 것이 특징인 CMOS인버터를 갖는 반도체 집적회로.10. The semiconductor integrated circuit as claimed in claim 8, wherein the other circuit is bit lines of dynamic memory cells. 제8항에 있어서, 상기 다른 회로는 스태틱 메모리 셀들을 구성하는 접지선인 것이 특징인 CMOS인버터를 갖는 반도체 집적회로.10. The semiconductor integrated circuit of claim 8, wherein the other circuit is a ground line constituting static memory cells. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the initial application.
KR1019890000244A 1988-01-14 1989-01-12 Semiconductor integrated circuit with cmos inverter KR910009356B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP63-5954 1988-01-14
JP63-005954 1988-01-14
JP63005944A JP2638866B2 (en) 1988-01-14 1988-01-14 Stacker for work cloth in sewing machine

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KR890012399A true KR890012399A (en) 1989-08-26
KR910009356B1 KR910009356B1 (en) 1991-11-12

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JP4722331B2 (en) * 2001-06-15 2011-07-13 Ｊｕｋｉ株式会社 Sewing machine stacker equipment
JP4681967B2 (en) * 2005-07-26 2011-05-11 Ｊｕｋｉ株式会社 Sewing sewing machine
CN109468759B (en) * 2018-12-24 2023-11-07 浙江翔科缝纫机股份有限公司 Automatic material collecting device and sewing machine

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JPS56117949A (en) * 1980-02-19 1981-09-16 Okura Yusoki Co Ltd Sheets piling device
DE3428833A1 (en) * 1984-08-04 1986-02-13 Henkel KGaA, 4000 Düsseldorf DISHWASHER

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JPH01181897A (en) 1989-07-19
KR910009356B1 (en) 1991-11-12

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