JPH09307429A - Integrator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrator which can be transformed into an IC and also can freely set both upper and lower limit levels of the count value of an up-down counter. SOLUTION: This integrator consists of an up-down counter 2 which performs its operation based on an up-down signal S1 and outputs a digital signal D, an edge sense circuit 4 which detects the up-down switching time of the signal S1 and outputs a detection signal S2, a limiter circuit 7 which outputs a limit signal S4 when the count value of the counter 2 reaches its set upper and lower limit levels, a gate controller 5 which opens an input line of a clock signal CLK to the counter 2 by the signal S2 and closes the input line by the signal S4, and an AND circuit 6. Then the upper and lower limit levels of the count value can be freely changed by changing the connection states between the input terminals of a NAND circuit 10 and a NOR circuit 11 and the counter 2 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrator using an up / down counter.

[0002]

2. Description of the Related Art Conventional integrators include one that obtains an integrated value of a signal input to an operational amplifier by connecting a capacitor to an operational amplifier in parallel, and one that uses an up-down counter. An integrator using an up-down counter counts up when an H-level up-down signal is input, and down-counts when an L-level up-down signal is input, a digital signal indicating the count value. Are sequentially generated, and the digital signal D is converted into an analog signal and output.

[0003]

However, the conventional integrator has the following problems. In an integrator in which a capacitor is connected to an operational amplifier, the capacitance of the capacitor is too large to be taken in as an IC, so it is difficult to integrate the integrator including the capacitor into an IC. Therefore, the number of IC pins and the number of external parts are increased, and the integrator is increased in size. Further, in the integrator using the up-down counter, since it is controlled by the carry, the upper limit value and the lower limit value of the count value are limited, and the upper limit value and the lower limit value cannot be freely set. It was inconvenient.

The present invention has been made to solve the above problems, and it is an object of the present invention to provide an integrator which can be integrated into an IC and which can freely set the upper limit value and the lower limit value of the count value. Has an aim.

[0005]

In order to solve the above-mentioned problems, the integrator according to the invention of claim 1 receives an input clock signal based on an up-down signal formed at H level and L level. A measuring unit that counts and outputs a digital signal indicating the count value in units of a plurality of bits, a converting unit that converts the digital signal from the measuring unit into an analog signal, and switching between the H level and the L level of the up / down signal. A detection unit that detects a time point and outputs a detection signal, and a limit unit that outputs a limit signal when the count value of the measurement unit reaches a settable upper limit value or a lower limit value, and the detection from the detection unit A signal is used to open the input path to the measuring section for the clock signal, and a gate section for closing the input path by the limit signal from the limit section.

According to a second aspect of the present invention, in the integrator according to the first aspect, the gate section receives an input of the clock signal from one input terminal and outputs the AND signal to the measuring section, and the detection signal. And a gate controller for inputting an H level gate opening / closing signal to the other input terminal of the AND circuit and inputting an L level gate opening / closing signal to the other input terminal of the AND circuit by the limit signal. Has a same number of input terminals as the number of bits of the digital signal, and the first NAND capable of inputting bits of the digital signal from all or any of these input terminals.
A circuit, a NOR circuit having the same number of input terminals as the number of bits of the digital signal, and capable of inputting the bits of the digital signal from all or any of these input terminals;
An inverter connected to the output side of the R circuit, and a second NAND having two input terminals connected to the inverter and the output side of the first NAND circuit, respectively, and outputting the limit signal from one output terminal to the gate controller. And a circuit.

According to the first aspect of the present invention, when the up / down signal and the clock signal are input to the measuring unit, a digital signal indicating a count value in units of a plurality of bits is output,
This digital signal is converted into an analog signal in the converter. In addition, in the detection unit, the up / down signal H
When the switching point between the level and the L level is detected, the detection signal is output to the gate section. Then, the gate section opens the input path of the clock signal to the measuring section, and the measuring section counts based on the up / down signal.
Then, when the count value of the measurement unit reaches the set upper limit value or the lower limit value, the limit signal is output from the limit unit to the gate unit, and the input path of the clock signal to the measurement unit is closed. As a result, the count value in the measuring unit is held at the set upper limit value or lower limit value.

According to the invention of claim 2, the first NA is provided.
When the bits of the digital signal are set to be input from all the input terminals of the ND circuit and the NOR circuit, when the bits of the digital signal are all “1” or “0”, the second NA is set.
The limit signal of "1" is output from the ND circuit to the gate controller. Then, an L level gate opening / closing signal is input from the gate controller to the other input terminal of the AND circuit, and the input path of the clock signal to the measuring unit is closed.
As a result, the count value of the measuring unit becomes the upper limit value when the bits of the digital signal are all "1", and the count value of the measuring unit becomes the lower limit value when the bits of the digital signal are all "0". In addition, the bit of the digital signal is set by inputting the bit of the digital signal from one of the input terminals of the first NAND circuit and the NOR circuit and holding the remaining input terminal at a predetermined level. When the value is smaller than all "1" or larger than all "0", the limit signal of "1" is output from the second NAND circuit to the gate controller, and the input path of the clock signal to the measurement unit is closed. . As a result, the upper limit value and the lower limit value of the count value change.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a CVSD (Continuously) integrator 1 according to an embodiment of the present invention.
It is a block diagram which shows the example applied to the module part of Variable Slope Delta. This module unit includes a comparator 20 that compares an analog audio signal V with a processed signal, and a shift register 21 that generates a digital signal based on an output from the comparator 20.
And a logic circuit 22 (denoted as “LOG” in the figure) that generates an up / down signal S1 based on a digital signal from the shift register 21 and an output signal from the integrator 1 that is close to the analog audio signal V. And a slope polarity switch 24 (denoted as “SW” in the figure).

The integrator 1 is provided between the logic circuits 22 and 23. The integrator 1 generates an analog signal V1 indicating the slope of the audio signal wave from the up / down signal S1 from the logic circuit 22 and supplies it to the comparator 23. It is designed to output. Specifically, the up / down counter 2 as a measuring unit and the digital-analog converter 3 as a converting unit
(Indicated as “D / A” in the figure), an edge sense circuit 4 as a detection unit, a gate controller 5 and an AND circuit 6 as a gate unit, and a limiter circuit 7 as a limit unit. .

The up-down counter 2 is connected to the output side of the logic circuit 22, counts the input clock signal CLK based on the up-down signal S1 from the logic circuit 22, and counts the count value to 10 bits. It is a counter that outputs a digital signal D shown in units. Specifically, the up-down signal S1 counts up when it is at H level, and the up-down signal S1 counts down when it is at L level.

The digital-analog converter 3 is connected to the output side of the up / down counter 2 and converts the digital signal D from the up / down counter 2 into an analog signal and outputs it to the comparator 23.

The edge sensing circuit 4 is also connected to the output side of the logic circuit 22, detects the switching time point of the H level and the L level of the up / down signal S1 from the logic circuit 22, and outputs the detection signal S2 of one pulse. This is a circuit for outputting to the gate controller 5.

Gate controller 5 and AND circuit 6
Are connected in series. Specifically, the AND circuit 6 is a two-input one-output AND circuit, one input end of which is connected to the clock generator 30 (denoted as “CLK GEN” in the figure) and the output end of which is connected to the up / down counter 2. Has been done. On the other hand, the gate controller 5 is composed of a flip-flop or the like, the input side thereof is connected to the output sides of the edge sensing circuit 4 and the limiter circuit 7, and the output side thereof is connected to the other input end of the AND circuit 6. Has been done. This gate controller 5 is an edge sensing circuit 4
When the detection signal S2 is input, the H-level gate opening / closing signal S3 is output to the AND circuit 6, and when the limit signal S4 is input from the limiter circuit 7, the flip-flop or the like is reset to open the L-level gate opening / closing. Signal S3 is A
The data is output to the ND circuit 6. That is, the gate controller 5 opens the AND circuit 6 to pass the clock signal CLK from the clock generator 30 to the up / down counter 2 when the detection signal S2 from the edge sense circuit 4 is input. Then, when the limit signal S4 is input from the limiter circuit 7, the AND circuit 6 is closed,
It has a control function of stopping the clock signal CLK from the clock generator 30.

The limiter circuit 7 is a part which receives the digital signal D from the up / down counter 2 and outputs a limit signal S4 to the gate controller 5 when the count value reaches the set upper limit value or the set lower limit value. NAND circuit 10 (first NAND circuit) as an upper limiter
And a NOR circuit 11 as a lower limiter. FIG. 2 is a circuit diagram specifically showing the limiter circuit 7. As shown in FIG. 2, the NAND circuit 10 is a ten-input one-output NAND circuit, and has ten input terminals 10-
All of 1 to 10-10 are connected to the bit bus 14 which passes the digital signal D from the up / down counter 2. The NOR circuit 11 is also a NOR circuit having ten inputs and one output, and the input terminals 11-1 to 11 of the NOR circuit 11 are also included.
-10 are also all connected to the bit bus 14. In addition, the last digit of the digital signal D is input to the input terminals 10-1 and 11-1, and the input terminals 10-10 and 11-1.
In 0, the most significant 10th digit bit is input. In the output stage of the NAND circuit 10 and the NOR circuit 11 as described above,
An inverter 12 and a 2-input 1-output NAND circuit 13 (second NAND circuit) are provided. And NO
The output side of the R circuit 11 receives the NAN via the inverter 12.
The NAND circuit 10 is connected to one output terminal of the D circuit 13.
Is connected to the other input end of the NAND circuit 13.

Next, the operation of the integrator of this embodiment will be described. FIG. 4 is a time chart of each signal during operation. Here, in order to facilitate understanding, as shown in FIG. 4B, after the H level state is maintained, the state is switched to the L level state at T1 and H level at T2.
A case where the up / down signal S1 switching to the level state is output from the logic circuit 22 will be described.

In FIG. 1, while the H-level up / down signal S1 is being input to the up / down counter 2,
The up / down counter 2 counts up based on the clock signal CLK. As a result, as shown in (f) of FIG. 4, hexadecimal numbers "001", "002", "00"
A digital signal D indicating "3", "004" is sequentially output from the up / down counter 2 to the digital-analog converter 3 and the limiter circuit 7, and the analog signal V1 converted by the digital-analog converter 3 is input to the comparator 23. To be done.

Then, as shown in FIG. 4B, when the up / down signal S1 switches from H level to L level at T1, as shown in FIG. 4C, one pulse of the detection signal S2 is detected. Is output from the edge sensing circuit 4 to the gate controller 5. As a result, as shown in (d) of FIG. 4, the H level gate opening / closing signal S3 is continuously output from the gate controller 5 to the AND circuit 6, and the AND circuit 6
The open state of is maintained. As a result, the up / down counter 2 down-counts based on the clock signal CLK, and as shown in (f) of FIG.
Digital signals D indicating 3 ”,“ 002 ”,“ 001 ”, and“ 000 ”are sequentially output from the up / down counter 2 to the digital / analog converter 3 and the limiter circuit 7.

The count value of hexadecimal number "000", that is, 2
When the digital signal D of the decimal number "0000000000" is input to the bit bus 14 of the limiter circuit 7 shown in FIG. 2, the input terminals 10- of the NAND circuit 10 and the NOR circuit 11 are
The levels of 1 to 10-10 and 11-1 to 11-10 are all "0". Therefore, as shown in (e) of FIG.
The limit signal S4 of level “1” is output from the NAND circuit 13 to the gate controller 5. As a result, the flip-flops and the like of the gate controller 5 are inverted,
As shown in FIG. 4D, the L level gate open / close signal S3 is output to the AND circuit 6, and the AND circuit 6 is closed. As a result, the down count operation of the up / down counter 2 is stopped, and the count value is held at "000" (hexadecimal number) as shown in (f) of FIG.

When the up / down signal S1 switches from the L level to the H level at T2 as shown in FIG. 4B, the detection signal S2 is output as shown in FIG. 4C.
Is output from the edge sensing circuit 4 to the gate controller 5, and as shown in FIG. 4D, the H level gate opening / closing signal S3 is output from the gate controller 5 to the AND circuit 6. As a result, the AND circuit 6 is opened, the operation of the up-down counter 2 is restarted, and the up-down counter 2 counts up based on the input H-level up-down signal S1. Thereby, as shown in (f) of FIG. 4, hexadecimal numbers "001" and "00"
A digital signal D indicating "2" ... "3FF" is sequentially output from the up-down counter 2 to the limiter circuit 7.

A hexadecimal "3FF" count value, that is, 2
When the digital signal D of the decimal number "1111111111" is input to the bit bus 14 of the limiter circuit 7 shown in FIG. 2, the input terminals 10- of the NAND circuit 10 and the NOR circuit 11-
The levels of 1 to 10-10 and 11-1 to 11-10 all become "1", and the limit signal S4 of "1" is output from the NAND circuit 13 to the gate controller 5 as shown in (e) of FIG. To be done. As a result, as shown in (d) of FIG. 4, the L level gate opening / closing signal S3 changes to the AND circuit 6
Is output to the AND circuit 6 and the AND circuit 6 is closed, as shown in FIG.
As shown in, the count value is held at “3FF” (hexadecimal number).

That is, the input terminals 10-1 to 10-10 and 11-1 to 11 of the NAND circuit 10 and the NOR circuit 11 are connected.
By connecting all -10 to the bit bus 14, the upper limit value of the count value of the up / down counter 2 is set to the hexadecimal number "3FF", and the lower limit value is set to the hexadecimal number "0".
00 "is set. When changing the setting of the upper limit value and the lower limit value, the connection state between the input ends 10-1 to 10-10, 11-1 to 11-10 of the NAND circuit 10 and the NOR circuit 11 and the bit bus 14 can be changed. Good.

FIG. 3 is a circuit diagram showing an example of changing the setting of the upper limit value and the lower limit value. In this modification, the input terminals 10-1 and 10-2 of the NAND circuit 10 are short-circuited to constantly supply the voltage VDD of level "1", and the input terminal 11- of the NOR circuit 11 is
By short-circuiting 1 and 11-2 and keeping them at the voltage Vss of level “0”, the upper limit value of the up / down counter 2 is changed to the hexadecimal number “3FC”, and the lower limit value is set to the hexadecimal number. The setting is changed to "003". That is, when the count value of hexadecimal number “003”, that is, the digital signal D of binary number “0000000011” is input to the bit bus 14 of the limiter circuit 7 during down counting, the input terminals 11-1 and 11 of the NOR circuit 11 are input. -2 is held at "0", the last two digits of the binary number "0000000011" of the digital signal D are not input to the input terminals 11-1, 11-2 of the NOR circuit 11 and are in a neglected state. Become. Therefore, the digital signal D of “0000000000” is input to the input terminals 11-1 to 11- of the NOR circuit 11.
It will be in the state entered in 10. As a result, the limit signal S4 of "1" is output from the NAND circuit 13 to the gate controller 5, and the count value is the binary number "0000000".
011 ”, that is, the hexadecimal number“ 003 ”is held. When the count value of the hexadecimal number “3FC”, that is, the digital signal D of the binary number “1111111100” is input to the bit bus 14 of the limiter circuit 7 at the time of up-counting, the input terminals 10-1 and 10 of the NAND circuit 10 are input. −
Since 2 is held at “1”, the last two digits of the digital signal D are not input to the input terminals 10-1 and 10-2 of the NAND circuit 10 and are in a neglected state. Therefore, "11
The digital signal D of “11111111” is the NAND circuit 1
0 is input to the input terminals 10-1 to 10-10. As a result, the limit signal S4 of "1" is output from the NAND circuit 13 to the gate controller 5, and the count value is binary "1111111100", that is, hexadecimal "3".
FC will be held.

As described above, according to the integrator of the present embodiment, since the capacitor is not included inside, it is easy to make the integrator IC. For this reason, pins for capacitors and external parts are not required, and the integrator can be downsized. In addition, the NAND circuit 1 of the limiter circuit 7
0 and the input terminals 10-1 to 10-10 of the NOR circuit 11,
Since the upper limit value and the lower limit value of the count value can be easily set and changed only by changing the connection state between 11-1 to 11-10 and the bit bus 14, the integrator is used in the full dynamic range. It is possible to adjust the DC offset easily, which is very convenient.

In the present embodiment, the limiter circuit 7 is provided with the NAND circuit 10 and the NOR circuit 11,
Although the digital signal D from the up / down counter 2 is input to these circuits via the bit bus 14, a NAND circuit is provided in place of the NOR circuit 11 to allow the digital signal D from the up / down counter 2 to the NAND circuit 10. Is input to the NAND circuit instead of the NOR circuit 11 and the inverted digital signal D ′ of the digital signal D (for example,
When the digital signal D is "1111111100",
It is needless to say that the same effect as described above can be obtained by inputting "(000000111)".

[0026]

As described above in detail, according to the integrator of the present invention, the measuring section, the converting section, the detecting section, the limit section and the gate section are formed, and the internal capacitor is not included. Therefore, the whole integrator can be easily integrated into an IC, and as a result, there is no need for a pin for a capacitor or an external component, and there is an excellent effect that the integrator can be downsized. Further, since the upper limit value and the lower limit value of the count value can be easily changed by the limiter, the integrator can be used in the full dynamic range and the DC offset can be easily adjusted. It can and is very convenient.

[Brief description of drawings]

FIG. 1 illustrates a CVSD integrator 1 according to an embodiment of the present invention.
3 is a block diagram showing an example applied to the module unit of FIG.

FIG. 2 is a circuit diagram specifically showing a limiter circuit.

FIG. 3 is a circuit diagram showing an example of changing the setting of the upper limit value and the lower limit value of the count value.

FIG. 4 is a time chart diagram of each signal during the operation of the integrator.

[Explanation of symbols]

1 ... integrator, 2 ... up / down counter,
3 ... Digital-analog converter, 4 ... Edge sensing circuit, 5 ... Gate controller, 6 ... A
ND circuit, 7 ... Limiter circuit, 10, 13 ...
・ NAND circuit, 11 ... NOR circuit, 12 ...
・ Inverter.

Claims (2)

[Claims] 1. A measuring unit that counts an input clock signal based on an up-down signal formed at an H level and an L level and outputs a digital signal indicating the count value in a unit of a plurality of bits, said measuring unit. The conversion unit for converting the digital signal from the unit into an analog signal, the detection unit for detecting the switching time point of the H level and the L level of the up / down signal and outputting the detection signal, and the count value of the measuring unit are When the settable upper limit value or lower limit value is reached, the limit section that outputs the limit signal and the detection signal from the detection section opens the input path of the clock signal to the measurement section, and the limit signal from the limit section A gate unit for closing the input path, and an integrator. 2. The integrator according to claim 1, wherein the gate unit is an AND circuit capable of inputting the clock signal from one input terminal and outputting the clock signal to the measuring unit, and an H level gate based on the detection signal. Opening / closing signal is the above A
A gate controller for inputting to the other input end of the ND circuit and for inputting an L level gate opening / closing signal to the other input end of the AND circuit according to the limit signal, wherein the limit section is the number of bits of the digital signal And a first NAND circuit capable of inputting the bits of the digital signal from all or any of these input terminals, and the same number of input terminals as the number of bits of the digital signal, A NOR circuit capable of inputting the bits of the digital signal from all or any of these input terminals, an inverter connected to the output side of the NOR circuit, and two input terminals of the inverter and the output of the first NAND circuit. A second NAND circuit which is connected to the gate controller and outputs the limit signal from one output terminal to the gate controller. The integrator to collect.