JP3136593B2 - Semiconductor device with built-in regulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a built-in regulator <br/> semiconductor device, in particular, the reference voltages for the regulator internal semiconductor device variable.

[0002]

2. Description of the Related Art Conventionally, some integrated circuits for generating a reference voltage use a voltage dividing resistor circuit. FIG. 8 shows an example of such an integrated circuit.
No. 5 (“Device for Correcting Operating Characteristics of Electronic Circuits”).

Referring to FIG. 8, the power supply circuit disclosed in the above publication includes an operational amplifier 32, a resistor voltage dividing circuit 34 in which resistors R1 to R6 are connected in series, and one end of the resistor R6 is grounded. The resistance voltage dividing circuit 34 and the external power supply V
It includes a P-channel MOSFET connected to DD1, and analog switches SW1 to SW5 provided between a connection point of each resistor and a non-inverting input terminal of the operational amplifier 32. Switching of the analog switch is performed based on the drive data 28 based on the control register 38 and the decoder 4.
This is performed by the drive circuit 42 via “0”. This circuit always outputs a constant reference voltage VDD2 based on the drive data 28 even if the threshold value of the P-channel MOSFET 36 varies or the ambient temperature changes. In particular, when the power is turned on, the drive data 28 is transmitted by detecting that the reference voltage VDD2 has entered a predetermined range by a detection circuit (not shown).

[0004]

However, in recent years, with an increase in demand for mobile products and the like, it has become essential to reduce power consumption in semiconductor devices. In particular, a microcontroller or the like sometimes has a built-in regulator to reduce power consumption by using a reference voltage for an internal circuit. In such a case, in the related art, the reference voltage is a fixed value, so that further reduction in power consumption cannot be achieved.

Further, if the reference voltage changes rapidly, the internal circuit cannot follow the voltage fluctuation, which may cause malfunction as an incorrect voltage.

Therefore, an object of the present invention is to make a reference voltage variable in a semiconductor device with a built- in regulator.

Another object of the present invention is to gradually change a reference voltage in order to prevent a malfunction of a semiconductor device.

[0008]

According to the present invention, there is provided an operational amplifier for inputting a constant voltage Vs to one input terminal, a transistor for inputting the output of the operational amplifier, and two or more transistors connected in series. A semiconductor device with a built-in regulator comprising: a resistor, two or more switches connected in parallel to each of the resistors, a control circuit that opens and closes the switch, and a resistance value setting register that inputs a set resistance value to the control circuit. Wherein one end of the series connection resistor is connected to the source of the transistor, the other end is grounded via another resistor, and the non-grounded end of the other resistor is connected to another input terminal of the operational amplifier; The control circuit applies another constant voltage to the drain of the transistor, and the control circuit applies a different delay to the output of each digit of the resistance value setting register. And so as to open and close each of the switches in.

Further, according to the present invention, the data of the resistance value setting register is converted from parallel to serial and inputted to a shift register which is a control circuit, and each switch is opened and closed with the output of each digit of the shift register. Good.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor device with a built- in regulator according to the present invention. As shown in FIG. 1, a semiconductor device with a built- in regulator according to the present invention includes an operational amplifier 1 for inputting a constant voltage Vs, a P-channel MOS transistor 2 for inputting the output of the operational amplifier 1, a resistor R1 connected in series,
R2,. . . , Rn and switches SW1, SW2,. . . , SWn and switch S
W1, SW2,. . . , SWn, a resistance value setting register 4 for inputting a set resistance value to the control circuit 3, and an internal circuit 5.

One end of the series connection resistor is connected to the source of the P-channel MOS transistor 2 and the other end is grounded via a resistor R. The non-grounded end of the resistor R is input to the operational amplifier 1. Furthermore, P channel M
The power supply voltage Vd is applied to the drain of the OS transistor 2.

Accordingly, the regulator of the present invention shown in FIG.
In the built-in semiconductor circuit, the source voltage Vr of the P-channel MOS transistor 2 is (Σ (Rj) + R) · V
s / R. Here, Σ (Rj) means the sum of the resistance values of the resistors that are not short-circuited. That is,
Switches SW1 and SW
2,. . . , SWn, the reference voltage Vr applied to the internal circuit 5 is made variable.

FIG. 2 is a circuit diagram of the control circuit 3. As shown in FIG. 2, the control circuit 3 includes switches SW1, SW2,. . . , SWn, and latches 11 and 13 and inverters 12 and 14, respectively. Further, the clock signals CLK1 and CLK2 are supplied to the NAND circuits 17 and 1 together with the select signal SEL.
6 and serve as clocks for the latches 11 and 13, respectively. The latches 11 and 13 are set latches, and use a reset signal (RESET) as a latch set signal.

Output signals from the inverter 14 are provided by switches SW1 and SW for turning on / off a resistor.
2,. . . , SWn. For this switch element, an N-channel MOS transistor or the like is preferably used.

FIG. 3 is a circuit diagram of a control circuit in the case where four levels of reference voltages Vr are generated using the resistors R1 and R2.

The reference voltage Vr can take four values, Vr1, Vr2, Vr3, Vr4, depending on the combination of switching. Here, Vr1 = (R1 + R2 + R) · Vs / R Vr2 = (R1 + R) · Vs / R Vr3 = (R2 + R) · Vs / R Vr4 = R · Vs / R = Vs.

FIG. 4 is a timing chart for explaining the operation of the control circuit shown in FIG. 3 when the resistors R1 and R2 are used. Here, the resistance setting register 4 is set to “0”.
Consider the case where "0" is output. This control circuit 3
Since a NAND type latch is used, RES
When ET enters, SW1 and SW2 are turned off, and the resistors R1 and R2 are both in a non-short circuit state. The reference voltage Vr at this point becomes Vr1.

Next, when both the resistors R1 and R2 are in a non-short circuit state, the resistance value setting register 4 sets "11".
Is output. The buses 0 and 1 are latched in the latch circuits 11 and 19 by the CLK1 in which the select signal SEL is 1, and are latched by the latch circuits 13 and 21 via the inverters 12 and 20 at the next rising edge of the CLK2. Since the inverter on the bus 0 has one stage and the inverter on the bus 1 has three stages, first, the switch SW1 of the resistor on the bus 0 is turned on, and at this time, R1 changes to a short circuit state, but R2 does not short circuit. It remains in a state. Therefore,
The reference voltage Vr at this point becomes Vr3.

Next, the switch SW2 of the resistor on the bus 1 side is turned on and R2 is also short-circuited, so that the reference voltage Vr at this point is Vr4, that is, Vs.

As described above, by giving a delay to the ON / OFF of the switch according to the number of inverters of the bus 0 and the bus 1, the combined resistance value is temporarily changed from (R1 + R2) to R2.
And finally settles to zero. Therefore, a rapid change of Vr, that is, an illegal voltage is prevented.

Generally, the switches SW1, SW
2,. . . , SWn, a different odd number of inverters are connected.

In the above, the method in which the inverter is multi-staged in order to produce a delay in the control circuit 3 has been described. However, a delay element may be used instead of the inverter.

Further, the delay may be made by changing the wiring length and the wiring delay.

Although the embodiment of the present invention has been described above, it is also possible to prevent illegal voltage without relying on delay.

FIG. 5 is a block diagram of another embodiment of the present invention to which a parallel-serial converter 6 is added. As shown in FIG. 5, in this embodiment, a parallel-serial converter 6 is connected between the control circuit 31 and the resistance value setting register 4.

FIG. 6 shows the control circuit 3 shown in FIG.
1 is a circuit diagram of FIG.

As shown in FIG. 6, in the control circuit 31, the output of the latch 13 is input to the latch 19 to form a shift register.

FIG. 7 shows the control circuit 3 shown in FIG.
3 is a time chart for explaining the operation of FIG. FIG.
As shown in FIG.
Is sequentially reduced for each clock, and the ON / OFF of the resistor is changed to sequentially change the reference voltage, thereby preventing an incorrect voltage.

The value "A" of the resistance value setting register 4 input from the bus is switched to the switch S by the clocks CLK1 and CLK2.
Turn W1 ON / OFF.

Then, at the next CLK1 and CLK2, "A"
Turns on / off the next switch SW2. At this time, the next value "B" turns on / off the switch SW1. In this way, the value of the resistance value setting register 4 is shifted by the clocks CLK1 and CLK2, and SW1 and SW2 are sequentially turned ON / O.
FF.

In the above description, a P-channel MOSFET is exemplified as the transistor 2, but the present invention is not limited to this, and an N-channel MOSFET may be used. Further, a junction transistor, a bipolar transistor or the like can be used regardless of the channel.

[0033]

According to the present invention described above, power consumption can be reduced because the reference voltage is variable. The reason is that the reference voltage can be set to a voltage suitable for use, for example, a high voltage when the operation speed of an internal circuit such as a micro CPU or a display drive circuit is high, and a low voltage when the operation speed is low.

Further, according to the present invention, even if the reference voltage is changed, no illegal voltage is obtained. The reason is that the reference voltage can be gradually changed by providing a control circuit and turning on / off the resistance switches in order so as not to change the reference voltage abruptly. In particular, if a control circuit having a shift register configuration is used, a delay is created for each bit of the register, so that the problem of different layouts between the register and the switch can be avoided. Further, since the reference voltage is changed by the clock, the reference voltage can be changed more slowly.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor device with a built- in regulator according to the present invention.

FIG. 2 is a circuit diagram of a control circuit according to the present invention.

FIG. 3 is a circuit diagram of a control circuit according to the present invention for generating four-stage reference voltages with two resistors.

FIG. 4 is a time chart for explaining the operation of the control circuit of the present invention for generating four-stage reference voltages with two resistors.

FIG. 5 is a block diagram of another semiconductor device with a built- in regulator according to the present invention.

FIG. 6 is a circuit diagram of a control circuit provided in another semiconductor device with a built- in regulator according to the present invention.

FIG. 7 is a time chart for explaining the operation of a control circuit provided in another semiconductor device with a built- in regulator according to the present invention.

FIG. 8 shows a conventional reference voltage generation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Operational amplifier 2 P-channel MOS transistor 3 Control circuit 4 Resistance setting register 5 Internal circuit 6 Parallel-serial converter R1, R2, Rn, R Resistance SW1, SW2, SWn Switch

Claims (5)

(57) [Claims] An operational amplifier for inputting a constant voltage Vs to one input terminal, a transistor for inputting the output of the operational amplifier, two or more resistors connected in series, and two or more resistors connected in parallel to each of the resistors A switch, a control circuit that opens and closes the switch, and a semiconductor device with a built-in regulator comprising a resistance setting register that inputs a set resistance value to the control circuit, wherein one end of the series-connected resistor is connected to a source of a transistor. Connected, the other end is grounded via another resistor, the non-grounded end of the other resistor is connected to another input terminal of the operational amplifier, and another constant voltage is applied to a drain of the transistor; The control circuit opens and closes each of the switches with a signal obtained by giving a different delay to the output of each digit of the resistance value setting register. Semiconductor device with built- in regulator. 2. The control circuit according to claim 1, further comprising: a set latch for inputting a signal of each digit of the resistance value setting register, and a first latch for inputting an output of the first set latch.
An inverter, a latch with a second set for receiving an output of the first inverter, a second inverter for receiving an output of the latch with the second set, and a delay element for receiving an output of the second inverter The regulator according to claim 1, wherein each of the delay elements gives a different delay to the input signal.
Built-in semiconductor device. 3. The semiconductor device with a built -in regulator according to claim 2, wherein the delay element is one inverter or a series connection of three or more odd-numbered inverters. . 4. An operational amplifier for inputting a constant voltage Vs to one input terminal, a transistor for inputting the output of the operational amplifier, two or more resistors connected in series, and two or more resistors connected in parallel to each of the resistors A semiconductor device with a built-in regulator, comprising: a switch, a control circuit for opening and closing the switch, and a resistance setting register for inputting a set resistance value to the control circuit via a parallel-serial converter. Connecting one end of the series-connected resistor to the source of the transistor, connecting the other end to ground via another resistor, connecting the non-grounded end of the other resistor to another input terminal of the operational amplifier, Another constant voltage is applied to the drain of the transistor 2, and the control circuit is configured to set the resistor
The value of the constant register to the internal clock of the control circuit.
Each time the switch is turned off, each of the switches is opened and closed sequentially.
Te, Regulator semiconductor device characterized by sequentially changing the reference voltage. 5. The control circuit includes a shift register, and each of the switches is provided at each digit output of the shift register.
5. The semiconductor device with a built- in regulator according to claim 4, wherein the semiconductor devices are sequentially opened and closed.