JPH0497621A - A/d conversion circuit - Google Patents

Abstract

PURPOSE:To shorten the conversion time by generating a difference between an input voltage and a reference voltage, deciding the MSB of an output based on the voltage difference and applying A/D conversion of remaining (N-1)bits with an integration method. CONSTITUTION:The A/D conversion circuit consists of an amplifier(AMP) 1, a comparator(COMP) 2, a resistance element 3, capacitive elements 4, 11, switches 5, 6, 12-19, a control circuit 7, a counter 8, a logic circuit 9 and a buffer amplifier 10. Then the MSB is decided by a difference voltage between an input voltage and a reference voltage (a half of a maximum input voltage) and the remaining (N-1) bits are A/D-converted by the integration. Thus, the conversion time is halved in comparison with that of a conventional circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D conversion circuit, and particularly to an integral type A/D conversion circuit in an LSI.

[Conventional technology]

Conventionally, such an integrating type A/D conversion circuit includes an amplifier that switches and amplifies an input voltage and a reference voltage, a comparator that compares the output of this amplifier with a reference voltage, and a control circuit that drives a switching means using the output of this comparator. It is equipped with

FIG. 4 is a diagram of an integral type A/D conversion circuit showing an example of such a conventional method.

As shown in Figure 4, the conventional integral type A/D conversion circuit is
Switches 5 and 6 connected to terminals supplying input voltage and reference voltage, respectively;
A resistor 3 is connected to the point where the other ends are commonly connected, and the other end of this resistor 3 is connected to (-) inputs, and GND is connected to (+).
An amplifier (AMP) 1 connected to each input, and this amplifier 1
A comparator (COMF) 2 that compares the capacitive element 4 connected between (=) inputs and outputs with the output of the amplifier l and GND, and controls the plow switches 5, 6, etc. based on the output of this COMF 2. It has a control circuit 7 and a counter 8 that counts digital signals from the control circuit 7 based on the period of the clock. Here, the operation when the clock period is T and the A/D conversion output is N pips (N: integer) will be explained with reference to FIG.

FIG. 5 is an output characteristic diagram of the amplifier in FIG. 4.

As shown in FIG. 5, when the switch 5 is first turned on and the switch 6 is turned off, integration (charging) is performed according to the input until the counter 8 counts 2N. Next, when the switch 5 is turned off and the switch 6 is turned on, integration (discharge) is performed using the reference voltage. The output of amplifier 1 is G
Judging by comparator 2 when the voltage crosses the ND potential,
Stop counter 8. That is, n (n: integer) counted from the time when the discharge starts until the counter 8 stops becomes the output of the A/D conversion circuit.

[Problem to be solved by the invention]

The above-mentioned conventional integral type A/D conversion circuit has the disadvantage that it takes more than 2X2''XT conversion time at maximum input because it is necessary to perform integration until counting 2N in order to obtain an N-bit output. In addition, the longer the conversion time, the larger the capacitance is required for such an A/D conversion circuit, especially in LSIs where it is difficult to create a large capacitance.
Since it cannot be built into an LSI, it has the disadvantage of being externally attached. Furthermore, the conventional A/D conversion circuit requires a reference voltage that is the same voltage as the maximum input voltage and has a different polarity, and therefore has the disadvantage of requiring a wide range.

An object of the present invention is to provide an A/D conversion circuit that can shorten the conversion time, reduce the capacity, and reduce the voltage range.

[Means to solve the problem]

The A/D conversion circuit of the present invention includes a difference circuit including a first capacitive element and a comparator for obtaining a difference between an input voltage and a reference voltage having 1/2 of the maximum voltage of the input voltage; a conversion unit comprising a resistive element, an amplifier, and a second capacitive element for A/D converting the MSB of the output and (N-1) bits smaller than the MSB using an integral method; a plurality of switches and control circuits for switching and controlling; a counter for counting data from the control circuit; and the MSB.
and a logic circuit that inverts the output of the counter according to the value of and obtains an A/D conversion output.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the basic configuration of an A/D conversion circuit for explaining one embodiment of the present invention.

As shown in FIG. 1, this embodiment includes a differential circuit consisting of a first capacitive element 11 and a comparator 2 for obtaining a difference between an input voltage IN and a reference voltage REF having a maximum input voltage IN-MAX of 172. , this difference (IN-RE
3.F) for A/D converting the MSB of the output OUT and (N-1) bits smaller than this MSB in an integral manner; A conversion section consisting of an amplifier 1 and a second capacitive element 4, and a plurality of switches 5, 6 and 12 to 19 that perform switching for A/D conversion using the above-mentioned integration method,
A control circuit 7 that controls these switches;
a counter 8 that counts data from
It has a logic circuit 9 for obtaining an A/D conversion output OUT which inverts the output of the counter 8 according to the value of B.

To explain this in detail, the first switch 12 whose one end is connected to the input terminal IN, and the reference voltage terminal RE
second and third switches 13 and 6, one end of which is connected to the second switch 13; a fourth and a fifth capacitive element 11 whose one ends are connected to the connection point of the first switch 12 and the first capacitive element 11;
switches 14 and 16, sixth and seventh switches 17 and 15 whose ends are connected to the connection point of the second switch 13 and the first capacitive element 11, and fourth and seventh switches 14 and 15. an eighth switch 5 whose other end is grounded and whose one end is connected to the connection point to which the other ends of the fifth and sixth switches 16 and 17 are connected;
a buffer amplifier lO whose input side is connected to the other ends of the third and eighth switches; a resistor element 3 and a ninth switch 19 whose one end is connected to the output of this buffer amplifier 10; An amplifier (AMP) 1 having (-) inputs connected to the other end and having (+) inputs grounded, and a second capacitive element 4 connected between the (-) inputs and the output of this amplifier 1. , one end is connected to the output of the amplifier 1 and the other end is connected to the other end of the ninth switch 19, and the (-) input is the connection point of the ninth and disciple switches 19 and 18. connected to and (+)
A comparator (COMF) 2 whose inputs are grounded, a logic circuit 9 with an N-bit output whose output side is connected to the output terminal OUT, and an output side connected to the input side of the logic circuit 90 (
N-1) bit parallel output counter (N: integer) 8;
Based on the output of the comparator 2, the clock input from the clock terminal C, and the signal from the counter 8,
~ Disciple's Switch 2 Counter 8. The control circuit 7 controls the logic circuit 9. Moreover, this control circuit 7
creates a voltage difference between the input voltage and the reference voltage, determines the MSB of the output based on the difference voltage, and controls the remaining (N-1) bits to be A/D converted by the integral method.

FIG. 2 is an output characteristic diagram of the amplifier in FIG. 1.

As shown in FIG. 2, the operation when the clock period is T, the output of the A/D conversion circuit is N pins I- (N; integer), and the counter 8 is an up counter, the switch 12.
3 is turned on, and the difference between the input voltage and the reference voltage (1/2 of the maximum input voltage) is supplied to the first capacitive element 11. Next, turn off switches 12 and 13, and switch 5, 15, 1
6゜19 is turned ON, the output M is set by comparator 2.
Determine SB. Switches 14 to 17 are controlled by the value, so that the output of the buffer amplifier becomes negative (switch 5 is ON, switch 6 is OFF), switch 18 is turned ON, and integration is performed until counter 8 counts 2N-1. (charging). Next, switch 5 is turned OFF and switch 6 is turned ON to perform integration (discharge), and the comparator 2 determines when the output of the amplifier 1 crosses the ground potential, and the control circuit 7 controls the counter 8 to stop. do.

After that, the logic circuit 9 outputs the A/D conversion, and when the MSB is "1", the output of the counter 8 is output as is, and when the MSB is "0", the inverted version of the output of the counter 8 is output. Output.

According to this, compared to the conventional integral type A/D conversion circuit that requires a conversion time of 2NxTx2 at the maximum input, the circuit of this embodiment requires a conversion time of 2N-IXTx at the maximum input. 2
conversion time, twice the conversion speed (half the conversion time)
becomes.

FIG. 3 is a specific configuration diagram of the A/D conversion circuit shown in FIG. 1.

As shown in FIG.
Realized by a transfer gate consisting of S-FET,
It is constructed by using an amplifier 10A for the buffer amplifier 10, using inverters 11 to 6 for the control line from the control circuit 7, and using EX-NOR gates 9A to 9N for the logic circuit 9.

In this specific example, the switch 5°6.12 in FIG.
~19, the buffer amplifier 10, and the logic circuit 9 are connected to transfer gates, inverters, amplifiers, and EX-Ns.
By configuring with OR gate etc., 0MO8-L
SI also has the advantage that the conversion time can be shortened and the second capacitive element 4 can be made small.

〔Effect of the invention〕

As explained above, the A/D conversion circuit of the present invention consists of an amplifier, a comparator, a resistor, a capacitive switch, a control circuit, a counter, a buffer amplifier, and a logic circuit, and includes an input voltage and a reference voltage (1/1/2 of the maximum input voltage). By determining the MSB based on the differential voltage in 2) and controlling the remaining (N-1) bits to be A/D converted by integration, there is an effect that the conversion time can be halved compared to the conventional method. Furthermore, since the conversion time is shortened, there is also the effect that the integration capacitance can be reduced. Furthermore, unlike the conventional technique, the reference voltage has the same polarity as the input voltage, so there is an effect that the range of the power supply voltage can be made smaller than in the conventional technique.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of an A/D conversion circuit for explaining an embodiment of the present invention, FIG. 2 is an output characteristic diagram of the amplifier in FIG. 1, and FIG. FIG. 4 is a diagram of an integral type A/D conversion circuit showing a conventional example, and FIG. 5 is an output characteristic diagram of the amplifier in FIG. 4. 1...411 amplifiers (AMP), 2...
Comparator (COMP), 3... Resistance element,
4, 11...Capacitive element, 5, 6.12-19.
...Switch, 7...Control circuit, 8...
...Counter, 9...Logic circuit, 10...
... Buffer amplifier, ■ 1 ~ Engineering 6 ... Inverter. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] 1. A differential circuit comprising a first capacitive element and a comparator for obtaining a difference between an input voltage and a reference voltage having 1/2 of the maximum voltage of the input voltage; a conversion unit comprising a resistive element, an amplifier, and a second capacitive element for A/D converting the MSB and (N-1) bits smaller than the MSB in an integral manner; a switching unit for A/D converting in the integral manner; It has a plurality of switches and a control circuit for performing control, a counter that counts data from the control circuit, and a logic circuit that inverts the output of the counter based on the value of the MSB and obtains an A/D conversion output. An A/D conversion circuit characterized by: 2. A first switch whose one end is connected to the input terminal, second and third switches whose one end is connected to the reference terminal, and whose one end is connected to the other end of the first switch and whose other end is connected to the reference terminal. a first capacitive element connected to the other end of the second switch; fourth and fifth switches each having one end connected to a connection point between the first switch and the first capacitive element; sixth and seventh switches, one end of which is connected to the connection point of the second switch and the first capacitive element, and the other ends of the fourth and seventh switches are grounded, and the fifth and sixth an eighth switch whose one end is connected to the connection point to which the other end of the switch is connected; a buffer amplifier whose input side is connected to the other ends of the third and eighth switches; and an output of the buffer amplifier. between a resistive element and a ninth switch connected to one end, an amplifier having a (-) input connected to the other end of the resistive element and a (+) input grounded, and the (-) input and output of the amplifier; a tenth switch having one end connected to the output of the amplifier and the other end connected to the other end of the ninth switch; a (-) input connected to the ninth switch; a comparator connected to the connection point of the tenth switch and whose (+) input is grounded; a logic circuit whose output side is connected to the output terminal; and a logic circuit whose output side is connected to the input side of the logic circuit (N-1 ) a bit parallel output counter (N; integer); controlling the first to tenth switches, the counter, and the logic circuit based on the output of the comparator, the clock input from the clock terminal, and the signal from the counter; A control circuit that determines the MSB of the output based on the voltage difference between the input voltage and the reference voltage, and controls the remaining (N-1) bits to be A/D converted using an integral method. A/D conversion circuit.